diff options
| author | Ilkka Koskinen <ilkka.koskinen@nokia.com> | 2009-11-10 10:26:15 -0500 |
|---|---|---|
| committer | Samuel Ortiz <sameo@linux.intel.com> | 2009-12-13 13:21:41 -0500 |
| commit | 1920a61e208fac73d1a30a7cf4005701802fe69f (patch) | |
| tree | 2282d5b842d46f5b48144d9950a89a7b78fb930a /include/linux | |
| parent | 6a6127462eb9096419fd4b3115ec5971d83a600f (diff) | |
mfd: Initial support for twl5031
TWL5031 introduces two new interrupts in PIH. Moreover, BCI
has changed remarkably and, thus, it's disabled when TWL5031
is in use.
Signed-off-by: Ilkka Koskinen <ilkka.koskinen@nokia.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Diffstat (limited to 'include/linux')
| -rw-r--r-- | include/linux/i2c/twl4030.h | 47 |
1 files changed, 41 insertions, 6 deletions
diff --git a/include/linux/i2c/twl4030.h b/include/linux/i2c/twl4030.h index 0c84cfa059e9..efa62eb497b8 100644 --- a/include/linux/i2c/twl4030.h +++ b/include/linux/i2c/twl4030.h | |||
| @@ -61,13 +61,16 @@ | |||
| 61 | #define TWL4030_MODULE_PWMA 0x0E | 61 | #define TWL4030_MODULE_PWMA 0x0E |
| 62 | #define TWL4030_MODULE_PWMB 0x0F | 62 | #define TWL4030_MODULE_PWMB 0x0F |
| 63 | 63 | ||
| 64 | #define TWL5031_MODULE_ACCESSORY 0x10 | ||
| 65 | #define TWL5031_MODULE_INTERRUPTS 0x11 | ||
| 66 | |||
| 64 | /* Slave 3 (i2c address 0x4b) */ | 67 | /* Slave 3 (i2c address 0x4b) */ |
| 65 | #define TWL4030_MODULE_BACKUP 0x10 | 68 | #define TWL4030_MODULE_BACKUP 0x12 |
| 66 | #define TWL4030_MODULE_INT 0x11 | 69 | #define TWL4030_MODULE_INT 0x13 |
| 67 | #define TWL4030_MODULE_PM_MASTER 0x12 | 70 | #define TWL4030_MODULE_PM_MASTER 0x14 |
| 68 | #define TWL4030_MODULE_PM_RECEIVER 0x13 | 71 | #define TWL4030_MODULE_PM_RECEIVER 0x15 |
| 69 | #define TWL4030_MODULE_RTC 0x14 | 72 | #define TWL4030_MODULE_RTC 0x16 |
| 70 | #define TWL4030_MODULE_SECURED_REG 0x15 | 73 | #define TWL4030_MODULE_SECURED_REG 0x17 |
| 71 | 74 | ||
| 72 | /* | 75 | /* |
| 73 | * Read and write single 8-bit registers | 76 | * Read and write single 8-bit registers |
| @@ -221,6 +224,38 @@ int twl4030_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes); | |||
| 221 | 224 | ||
| 222 | /*----------------------------------------------------------------------*/ | 225 | /*----------------------------------------------------------------------*/ |
| 223 | 226 | ||
| 227 | /* | ||
| 228 | * Accessory Interrupts | ||
| 229 | */ | ||
| 230 | #define TWL5031_ACIIMR_LSB 0x05 | ||
| 231 | #define TWL5031_ACIIMR_MSB 0x06 | ||
| 232 | #define TWL5031_ACIIDR_LSB 0x07 | ||
| 233 | #define TWL5031_ACIIDR_MSB 0x08 | ||
| 234 | #define TWL5031_ACCISR1 0x0F | ||
| 235 | #define TWL5031_ACCIMR1 0x10 | ||
| 236 | #define TWL5031_ACCISR2 0x11 | ||
| 237 | #define TWL5031_ACCIMR2 0x12 | ||
| 238 | #define TWL5031_ACCSIR 0x13 | ||
| 239 | #define TWL5031_ACCEDR1 0x14 | ||
| 240 | #define TWL5031_ACCSIHCTRL 0x15 | ||
| 241 | |||
| 242 | /*----------------------------------------------------------------------*/ | ||
| 243 | |||
| 244 | /* | ||
| 245 | * Battery Charger Controller | ||
| 246 | */ | ||
| 247 | |||
| 248 | #define TWL5031_INTERRUPTS_BCIISR1 0x0 | ||
| 249 | #define TWL5031_INTERRUPTS_BCIIMR1 0x1 | ||
| 250 | #define TWL5031_INTERRUPTS_BCIISR2 0x2 | ||
| 251 | #define TWL5031_INTERRUPTS_BCIIMR2 0x3 | ||
| 252 | #define TWL5031_INTERRUPTS_BCISIR 0x4 | ||
| 253 | #define TWL5031_INTERRUPTS_BCIEDR1 0x5 | ||
| 254 | #define TWL5031_INTERRUPTS_BCIEDR2 0x6 | ||
| 255 | #define TWL5031_INTERRUPTS_BCISIHCTRL 0x7 | ||
| 256 | |||
| 257 | /*----------------------------------------------------------------------*/ | ||
| 258 | |||
| 224 | /* Power bus message definitions */ | 259 | /* Power bus message definitions */ |
| 225 | 260 | ||
| 226 | /* The TWL4030/5030 splits its power-management resources (the various | 261 | /* The TWL4030/5030 splits its power-management resources (the various |
