Merge tag 'for-linus-20121009' of git://git.infradead.org/mtd-2.6

Pull MTD updates from David Woodhouse:

 - Disable broken mtdchar mmap() on MMU systems
 - Additional ECC tests for NAND flash, and some test cleanups
 - New NAND and SPI chip support
 - Fixes/cleanup for SH FLCTL NAND controller driver
 - Improved hardware support for GPMI NAND controller
 - Conversions to device-tree support for various drivers
 - Removal of obsolete drivers (sbc8xxx, bcmring, etc.)
 - New LPC32xx drivers for MLC and SLC NAND
 - Further cleanup of NAND OOB/ECC handling
 - UAPI cleanup merge from David Howells (just moving files, since MTD
   headers were sorted out long ago to separate user-visible from kernel
   bits)

* tag 'for-linus-20121009' of git://git.infradead.org/mtd-2.6: (168 commits)
  mtd: Disable mtdchar mmap on MMU systems
  UAPI: (Scripted) Disintegrate include/mtd
  mtd: nand: detect Samsung K9GBG08U0A, K9GAG08U0F ID
  mtd: nand: decode Hynix MLC, 6-byte ID length
  mtd: nand: increase max OOB size to 640
  mtd: nand: add generic READ ID length calculation functions
  mtd: nand: split simple ID decode into its own function
  mtd: nand: split extended ID decoding into its own function
  mtd: nand: split BB marker options decoding into its own function
  mtd: nand: remove redundant ID read
  mtd: nand: remove unnecessary variable
  mtd: docg4: add missing HAS_IOMEM dependency
  mtd: gpmi: initialize the timing registers only one time
  mtd: gpmi: add EDO feature for imx6q
  mtd: gpmi: do not set the default values for the extra clocks
  mtd: gpmi: simplify the DLL setting code
  mtd: gpmi: add a new field for HW_GPMI_CTRL1
  mtd: gpmi: do not get the clock frequency in gpmi_begin()
  mtd: gpmi: add a new field for HW_GPMI_TIMING1
  mtd: add helpers to get the supportted ONFI timing mode
  ...

7 files changed, 115 insertions, 38 deletions

diff --git a/include/linux/bcma/bcma_driver_chipcommon.h b/include/linux/bcma/bcma_driver_chipcommon.h
index 6ba45d2b99db..1cf1749440ac 100644
--- a/include/linux/bcma/bcma_driver_chipcommon.h
+++ b/include/linux/bcma/bcma_driver_chipcommon.h
@@ -522,6 +522,8 @@ struct bcma_sflash {
         u32 blocksize;
         u16 numblocks;
         u32 size;
+
+        struct mtd_info *mtd;
 };
 #endif
 
diff --git a/include/linux/mtd/bbm.h b/include/linux/mtd/bbm.h
index 650ef352f045..211ff67e8b0d 100644
--- a/include/linux/mtd/bbm.h
+++ b/include/linux/mtd/bbm.h
@@ -78,8 +78,6 @@ struct nand_bbt_descr {
 #define NAND_BBT_LASTBLOCK      0x00000010
 /* The bbt is at the given page, else we must scan for the bbt */
 #define NAND_BBT_ABSPAGE        0x00000020
-/* The bbt is at the given page, else we must scan for the bbt */
-#define NAND_BBT_SEARCH         0x00000040
 /* bbt is stored per chip on multichip devices */
 #define NAND_BBT_PERCHIP        0x00000080
 /* bbt has a version counter at offset veroffs */
@@ -110,7 +108,10 @@ struct nand_bbt_descr {
  * OOB area. This option is passed to the default bad block table function.
  */
 #define NAND_BBT_USE_FLASH      0x00020000
-/* Do not store flash based bad block table in OOB area; store it in-band */
+/*
+ * Do not store flash based bad block table marker in the OOB area; store it
+ * in-band.
+ */
 #define NAND_BBT_NO_OOB         0x00040000
 /*
  * Do not write new bad block markers to OOB; useful, e.g., when ECC covers
diff --git a/include/linux/mtd/lpc32xx_mlc.h b/include/linux/mtd/lpc32xx_mlc.h
new file mode 100644
index 000000000000..d91b1e35631e
--- /dev/null
+++ b/include/linux/mtd/lpc32xx_mlc.h
@@ -0,0 +1,20 @@
+/*
+ * Platform data for LPC32xx SoC MLC NAND controller
+ *
+ * Copyright © 2012 Roland Stigge
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_MTD_LPC32XX_MLC_H
+#define __LINUX_MTD_LPC32XX_MLC_H
+
+#include <linux/dmaengine.h>
+
+struct lpc32xx_mlc_platform_data {
+        bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
+};
+
+#endif  /* __LINUX_MTD_LPC32XX_MLC_H */
diff --git a/include/linux/mtd/lpc32xx_slc.h b/include/linux/mtd/lpc32xx_slc.h
new file mode 100644
index 000000000000..1169548a1535
--- /dev/null
+++ b/include/linux/mtd/lpc32xx_slc.h
@@ -0,0 +1,20 @@
+/*
+ * Platform data for LPC32xx SoC SLC NAND controller
+ *
+ * Copyright © 2012 Roland Stigge
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_MTD_LPC32XX_SLC_H
+#define __LINUX_MTD_LPC32XX_SLC_H
+
+#include <linux/dmaengine.h>
+
+struct lpc32xx_slc_platform_data {
+        bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
+};
+
+#endif  /* __LINUX_MTD_LPC32XX_SLC_H */
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 63dadc0dfb62..81d61e704599 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -265,14 +265,7 @@ int mtd_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
 int mtd_panic_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
                     const u_char *buf);
 
-static inline int mtd_read_oob(struct mtd_info *mtd, loff_t from,
-                               struct mtd_oob_ops *ops)
-{
-        ops->retlen = ops->oobretlen = 0;
-        if (!mtd->_read_oob)
-                return -EOPNOTSUPP;
-        return mtd->_read_oob(mtd, from, ops);
-}
+int mtd_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops);
 
 static inline int mtd_write_oob(struct mtd_info *mtd, loff_t to,
                                 struct mtd_oob_ops *ops)
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 57977c640529..24e915957e4f 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -56,7 +56,7 @@ extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
  * is supported now. If you add a chip with bigger oobsize/page
  * adjust this accordingly.
  */
-#define NAND_MAX_OOBSIZE        576
+#define NAND_MAX_OOBSIZE        640
 #define NAND_MAX_PAGESIZE       8192
 
 /*
@@ -92,6 +92,8 @@ extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
 #define NAND_CMD_READID         0x90
 #define NAND_CMD_ERASE2         0xd0
 #define NAND_CMD_PARAM          0xec
+#define NAND_CMD_GET_FEATURES   0xee
+#define NAND_CMD_SET_FEATURES   0xef
 #define NAND_CMD_RESET          0xff
 
 #define NAND_CMD_LOCK           0x2a
@@ -185,12 +187,6 @@ typedef enum {
  * This happens with the Renesas AG-AND chips, possibly others.
  */
 #define BBT_AUTO_REFRESH        0x00000080
-/*
- * Chip does not require ready check on read. True
- * for all large page devices, as they do not support
- * autoincrement.
- */
-#define NAND_NO_READRDY         0x00000100
 /* Chip does not allow subpage writes */
 #define NAND_NO_SUBPAGE_WRITE   0x00000200
 
@@ -200,6 +196,9 @@ typedef enum {
 /* Device behaves just like nand, but is readonly */
 #define NAND_ROM                0x00000800
 
+/* Device supports subpage reads */
+#define NAND_SUBPAGE_READ       0x00001000
+
 /* Options valid for Samsung large page devices */
 #define NAND_SAMSUNG_LP_OPTIONS \
         (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
@@ -208,12 +207,7 @@ typedef enum {
 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
-/* Large page NAND with SOFT_ECC should support subpage reads */
-#define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \
-                                        && (chip->page_shift > 9))
-
-/* Mask to zero out the chip options, which come from the id table */
-#define NAND_CHIPOPTIONS_MSK    0x0000ffff
+#define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
 
 /* Non chip related options */
 /* This option skips the bbt scan during initialization. */
@@ -237,6 +231,21 @@ typedef enum {
 /* Keep gcc happy */
 struct nand_chip;
 
+/* ONFI timing mode, used in both asynchronous and synchronous mode */
+#define ONFI_TIMING_MODE_0              (1 << 0)
+#define ONFI_TIMING_MODE_1              (1 << 1)
+#define ONFI_TIMING_MODE_2              (1 << 2)
+#define ONFI_TIMING_MODE_3              (1 << 3)
+#define ONFI_TIMING_MODE_4              (1 << 4)
+#define ONFI_TIMING_MODE_5              (1 << 5)
+#define ONFI_TIMING_MODE_UNKNOWN        (1 << 6)
+
+/* ONFI feature address */
+#define ONFI_FEATURE_ADDR_TIMING_MODE   0x1
+
+/* ONFI subfeature parameters length */
+#define ONFI_SUBFEATURE_PARAM_LEN       4
+
 struct nand_onfi_params {
         /* rev info and features block */
         /* 'O' 'N' 'F' 'I'  */
@@ -334,8 +343,10 @@ struct nand_hw_control {
  * @read_page_raw:      function to read a raw page without ECC
  * @write_page_raw:     function to write a raw page without ECC
  * @read_page:  function to read a page according to the ECC generator
- *              requirements.
- * @read_subpage:       function to read parts of the page covered by ECC.
+ *              requirements; returns maximum number of bitflips corrected in
+ *              any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
+ * @read_subpage:       function to read parts of the page covered by ECC;
+ *                      returns same as read_page()
  * @write_page: function to write a page according to the ECC generator
  *              requirements.
  * @write_oob_raw:      function to write chip OOB data without ECC
@@ -361,13 +372,13 @@ struct nand_ecc_ctrl {
                         uint8_t *calc_ecc);
         int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
                         uint8_t *buf, int oob_required, int page);
-        void (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
+        int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
                         const uint8_t *buf, int oob_required);
         int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
                         uint8_t *buf, int oob_required, int page);
         int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
                         uint32_t offs, uint32_t len, uint8_t *buf);
-        void (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
+        int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
                         const uint8_t *buf, int oob_required);
         int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
                         int page);
@@ -403,8 +414,6 @@ struct nand_buffers {
  * @read_word:          [REPLACEABLE] read one word from the chip
  * @write_buf:          [REPLACEABLE] write data from the buffer to the chip
  * @read_buf:           [REPLACEABLE] read data from the chip into the buffer
- * @verify_buf:         [REPLACEABLE] verify buffer contents against the chip
- *                      data.
  * @select_chip:        [REPLACEABLE] select chip nr
  * @block_bad:          [REPLACEABLE] check, if the block is bad
  * @block_markbad:      [REPLACEABLE] mark the block bad
@@ -462,6 +471,8 @@ struct nand_buffers {
  *                      non 0 if ONFI supported.
  * @onfi_params:        [INTERN] holds the ONFI page parameter when ONFI is
  *                      supported, 0 otherwise.
+ * @onfi_set_features   [REPLACEABLE] set the features for ONFI nand
+ * @onfi_get_features   [REPLACEABLE] get the features for ONFI nand
  * @ecclayout:          [REPLACEABLE] the default ECC placement scheme
  * @bbt:                [INTERN] bad block table pointer
  * @bbt_td:             [REPLACEABLE] bad block table descriptor for flash
@@ -487,7 +498,6 @@ struct nand_chip {
         u16 (*read_word)(struct mtd_info *mtd);
         void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
         void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
-        int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
         void (*select_chip)(struct mtd_info *mtd, int chip);
         int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
         int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
@@ -505,6 +515,10 @@ struct nand_chip {
         int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
                         const uint8_t *buf, int oob_required, int page,
                         int cached, int raw);
+        int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
+                        int feature_addr, uint8_t *subfeature_para);
+        int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
+                        int feature_addr, uint8_t *subfeature_para);
 
         int chip_delay;
         unsigned int options;
@@ -559,6 +573,7 @@ struct nand_chip {
 #define NAND_MFR_MICRON         0x2c
 #define NAND_MFR_AMD            0x01
 #define NAND_MFR_MACRONIX       0xc2
+#define NAND_MFR_EON            0x92
 
 /**
  * struct nand_flash_dev - NAND Flash Device ID Structure
@@ -641,6 +656,7 @@ struct platform_device;
  *                      ALE/CLE/nCE. Also used to write command and address
  * @write_buf:          platform specific function for write buffer
  * @read_buf:           platform specific function for read buffer
+ * @read_byte:          platform specific function to read one byte from chip
  * @priv:               private data to transport driver specific settings
  *
  * All fields are optional and depend on the hardware driver requirements
@@ -677,4 +693,20 @@ struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
         return chip->priv;
 }
 
+/* return the supported asynchronous timing mode. */
+static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
+{
+        if (!chip->onfi_version)
+                return ONFI_TIMING_MODE_UNKNOWN;
+        return le16_to_cpu(chip->onfi_params.async_timing_mode);
+}
+
+/* return the supported synchronous timing mode. */
+static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
+{
+        if (!chip->onfi_version)
+                return ONFI_TIMING_MODE_UNKNOWN;
+        return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
+}
+
 #endif /* __LINUX_MTD_NAND_H */
diff --git a/include/linux/mtd/sh_flctl.h b/include/linux/mtd/sh_flctl.h
index a38e1fa8af01..01e4b15b280e 100644
--- a/include/linux/mtd/sh_flctl.h
+++ b/include/linux/mtd/sh_flctl.h
@@ -49,7 +49,6 @@
 #define FLERRADR(f)             (f->reg + 0x98)
 
 /* FLCMNCR control bits */
-#define ECCPOS2         (0x1 << 25)
 #define _4ECCCNTEN      (0x1 << 24)
 #define _4ECCEN         (0x1 << 23)
 #define _4ECCCORRECT    (0x1 << 22)
@@ -59,9 +58,6 @@
 #define QTSEL_E         (0x1 << 17)
 #define ENDIAN          (0x1 << 16)     /* 1 = little endian */
 #define FCKSEL_E        (0x1 << 15)
-#define ECCPOS_00       (0x00 << 12)
-#define ECCPOS_01       (0x01 << 12)
-#define ECCPOS_02       (0x02 << 12)
 #define ACM_SACCES_MODE (0x01 << 10)
 #define NANWF_E         (0x1 << 9)
 #define SE_D            (0x1 << 8)      /* Spare area disable */
@@ -107,6 +103,14 @@
 #define DOCMD2_E        (0x1 << 17)     /* 2nd cmd stage execute */
 #define DOCMD1_E        (0x1 << 16)     /* 1st cmd stage execute */
 
+/* FLINTDMACR control bits */
+#define ESTERINTE       (0x1 << 24)     /* ECC error interrupt enable */
+#define AC1CLR          (0x1 << 19)     /* ECC FIFO clear */
+#define AC0CLR          (0x1 << 18)     /* Data FIFO clear */
+#define ECERB           (0x1 << 9)      /* ECC error */
+#define STERB           (0x1 << 8)      /* Status error */
+#define STERINTE        (0x1 << 4)      /* Status error enable */
+
 /* FLTRCR control bits */
 #define TRSTRT          (0x1 << 0)      /* translation start */
 #define TREND           (0x1 << 1)      /* translation end */
@@ -125,9 +129,15 @@
 #define _4ECCEND        (0x1 << 1)      /* 4 symbols end */
 #define _4ECCEXST       (0x1 << 0)      /* 4 symbols exist */
 
-#define INIT_FL4ECCRESULT_VAL   0x03FF03FF
 #define LOOP_TIMEOUT_MAX        0x00010000
 
+enum flctl_ecc_res_t {
+        FL_SUCCESS,
+        FL_REPAIRABLE,
+        FL_ERROR,
+        FL_TIMEOUT
+};
+
 struct sh_flctl {
         struct mtd_info         mtd;
         struct nand_chip        chip;
@@ -145,8 +155,7 @@ struct sh_flctl {
         uint32_t erase_ADRCNT;          /* bits of FLCMDCR in ERASE1 cmd */
         uint32_t rw_ADRCNT;     /* bits of FLCMDCR in READ WRITE cmd */
         uint32_t flcmncr_base;  /* base value of FLCMNCR */
-
-        int     hwecc_cant_correct[4];
+        uint32_t flintdmacr_base;       /* irq enable bits */
 
         unsigned page_size:1;   /* NAND page size (0 = 512, 1 = 2048) */
         unsigned hwecc:1;       /* Hardware ECC (0 = disabled, 1 = enabled) */