PCI: Add support for PASID capability

Devices supporting Process Address Space Identifiers
(PASIDs) can use an IOMMU to access multiple IO address
spaces at the same time. A PCIe device indicates support for
this feature by implementing the PASID capability. This
patch adds support for the capability to the Linux kernel.

Reviewed-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

2 files changed, 39 insertions, 0 deletions

diff --git a/include/linux/pci-ats.h b/include/linux/pci-ats.h
index 071395251abf..e3d0b3890249 100644
--- a/include/linux/pci-ats.h
+++ b/include/linux/pci-ats.h
@@ -93,4 +93,35 @@ static inline int pci_pri_status(struct pci_dev *pdev)
 }
 #endif /* CONFIG_PCI_PRI */
 
+#ifdef CONFIG_PCI_PASID
+
+extern int pci_enable_pasid(struct pci_dev *pdev, int features);
+extern void pci_disable_pasid(struct pci_dev *pdev);
+extern int pci_pasid_features(struct pci_dev *pdev);
+extern int pci_max_pasids(struct pci_dev *pdev);
+
+#else  /* CONFIG_PCI_PASID */
+
+static inline int pci_enable_pasid(struct pci_dev *pdev, int features)
+{
+        return -EINVAL;
+}
+
+static inline void pci_disable_pasid(struct pci_dev *pdev)
+{
+}
+
+static inline int pci_pasid_features(struct pci_dev *pdev)
+{
+        return -EINVAL;
+}
+
+static inline int pci_max_pasids(struct pci_dev *pdev)
+{
+        return -EINVAL;
+}
+
+#endif /* CONFIG_PCI_PASID */
+
+
 #endif /* LINUX_PCI_ATS_H*/
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index 7fc32aff94d2..b5d9657f3100 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -675,6 +675,14 @@
 #define PCI_PRI_MAX_REQ_OFF     0x08    /* Cap offset for max reqs supported */
 #define PCI_PRI_ALLOC_REQ_OFF   0x0c    /* Cap offset for max reqs allowed */
 
+/* PASID capability */
+#define PCI_PASID_CAP           0x1b    /* PASID capability ID */
+#define PCI_PASID_CAP_OFF       0x04    /* PASID feature register */
+#define PCI_PASID_CONTROL_OFF   0x06    /* PASID control register */
+#define PCI_PASID_ENABLE        0x01    /* Enable/Supported bit */
+#define PCI_PASID_EXEC          0x02    /* Exec permissions Enable/Supported */
+#define PCI_PASID_PRIV          0x04    /* Priviledge Mode Enable/Support */
+
 /* Single Root I/O Virtualization */
 #define PCI_SRIOV_CAP           0x04    /* SR-IOV Capabilities */
 #define  PCI_SRIOV_CAP_VFM      0x01    /* VF Migration Capable */