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authorJeff Garzik <jeff@garzik.org>2007-10-23 20:15:54 -0400
committerJeff Garzik <jeff@garzik.org>2007-10-23 20:15:54 -0400
commit02bae2129710018883f9536969de7e6acf9304ca (patch)
treec2f3b120b4c48288e2735fa7136895da3ff8615a /include/linux
parentc7ffb6bb7a1b6fe5912a009d561733911769d32b (diff)
parentc1f395f1c76b115c9691e1546942651fedb08c37 (diff)
Merge branch 'features' of git://farnsworth.org/dale/linux-2.6-mv643xx_eth into upstream
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/mv643xx.h328
-rw-r--r--include/linux/mv643xx_eth.h31
2 files changed, 32 insertions, 327 deletions
diff --git a/include/linux/mv643xx.h b/include/linux/mv643xx.h
index 9c8049005052..d2ae6185f03b 100644
--- a/include/linux/mv643xx.h
+++ b/include/linux/mv643xx.h
@@ -14,6 +14,7 @@
14#define __ASM_MV643XX_H 14#define __ASM_MV643XX_H
15 15
16#include <asm/types.h> 16#include <asm/types.h>
17#include <linux/mv643xx_eth.h>
17 18
18/****************************************/ 19/****************************************/
19/* Processor Address Space */ 20/* Processor Address Space */
@@ -658,120 +659,6 @@
658/* Ethernet Unit Registers */ 659/* Ethernet Unit Registers */
659/****************************************/ 660/****************************************/
660 661
661#define MV643XX_ETH_SHARED_REGS 0x2000
662#define MV643XX_ETH_SHARED_REGS_SIZE 0x2000
663
664#define MV643XX_ETH_PHY_ADDR_REG 0x2000
665#define MV643XX_ETH_SMI_REG 0x2004
666#define MV643XX_ETH_UNIT_DEFAULT_ADDR_REG 0x2008
667#define MV643XX_ETH_UNIT_DEFAULTID_REG 0x200c
668#define MV643XX_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080
669#define MV643XX_ETH_UNIT_INTERRUPT_MASK_REG 0x2084
670#define MV643XX_ETH_UNIT_INTERNAL_USE_REG 0x24fc
671#define MV643XX_ETH_UNIT_ERROR_ADDR_REG 0x2094
672#define MV643XX_ETH_BAR_0 0x2200
673#define MV643XX_ETH_BAR_1 0x2208
674#define MV643XX_ETH_BAR_2 0x2210
675#define MV643XX_ETH_BAR_3 0x2218
676#define MV643XX_ETH_BAR_4 0x2220
677#define MV643XX_ETH_BAR_5 0x2228
678#define MV643XX_ETH_SIZE_REG_0 0x2204
679#define MV643XX_ETH_SIZE_REG_1 0x220c
680#define MV643XX_ETH_SIZE_REG_2 0x2214
681#define MV643XX_ETH_SIZE_REG_3 0x221c
682#define MV643XX_ETH_SIZE_REG_4 0x2224
683#define MV643XX_ETH_SIZE_REG_5 0x222c
684#define MV643XX_ETH_HEADERS_RETARGET_BASE_REG 0x2230
685#define MV643XX_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234
686#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_0 0x2280
687#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_1 0x2284
688#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_2 0x2288
689#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_3 0x228c
690#define MV643XX_ETH_BASE_ADDR_ENABLE_REG 0x2290
691#define MV643XX_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2))
692#define MV643XX_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7))
693#define MV643XX_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10))
694#define MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10))
695#define MV643XX_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10))
696#define MV643XX_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10))
697#define MV643XX_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10))
698#define MV643XX_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10))
699#define MV643XX_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10))
700#define MV643XX_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10))
701#define MV643XX_ETH_DSCP_0(port) (0x2420 + (port<<10))
702#define MV643XX_ETH_DSCP_1(port) (0x2424 + (port<<10))
703#define MV643XX_ETH_DSCP_2(port) (0x2428 + (port<<10))
704#define MV643XX_ETH_DSCP_3(port) (0x242c + (port<<10))
705#define MV643XX_ETH_DSCP_4(port) (0x2430 + (port<<10))
706#define MV643XX_ETH_DSCP_5(port) (0x2434 + (port<<10))
707#define MV643XX_ETH_DSCP_6(port) (0x2438 + (port<<10))
708#define MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10))
709#define MV643XX_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10))
710#define MV643XX_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10))
711#define MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10))
712#define MV643XX_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10))
713#define MV643XX_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10))
714#define MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10))
715#define MV643XX_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10))
716#define MV643XX_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10))
717#define MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10))
718#define MV643XX_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10))
719#define MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10))
720#define MV643XX_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10))
721#define MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10))
722#define MV643XX_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10))
723#define MV643XX_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10))
724#define MV643XX_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10))
725#define MV643XX_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10))
726#define MV643XX_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10))
727#define MV643XX_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10))
728#define MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10))
729#define MV643XX_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10))
730#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10))
731#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10))
732#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10))
733#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10))
734#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10))
735#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10))
736#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10))
737#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10))
738#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10))
739#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10))
740#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10))
741#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10))
742#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10))
743#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10))
744#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10))
745#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10))
746#define MV643XX_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10))
747#define MV643XX_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10))
748#define MV643XX_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10))
749#define MV643XX_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10))
750#define MV643XX_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10))
751#define MV643XX_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10))
752#define MV643XX_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10))
753#define MV643XX_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10))
754#define MV643XX_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10))
755#define MV643XX_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10))
756#define MV643XX_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10))
757#define MV643XX_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10))
758#define MV643XX_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10))
759#define MV643XX_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10))
760#define MV643XX_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10))
761#define MV643XX_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10))
762#define MV643XX_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10))
763#define MV643XX_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10))
764#define MV643XX_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10))
765#define MV643XX_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10))
766#define MV643XX_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10))
767#define MV643XX_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10))
768#define MV643XX_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10))
769#define MV643XX_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10))
770#define MV643XX_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10))
771#define MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10))
772#define MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10))
773#define MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10))
774
775/*******************************************/ 662/*******************************************/
776/* CUNIT Registers */ 663/* CUNIT Registers */
777/*******************************************/ 664/*******************************************/
@@ -1089,219 +976,6 @@ struct mv64xxx_i2c_pdata {
1089 u32 retries; 976 u32 retries;
1090}; 977};
1091 978
1092/* These macros describe Ethernet Port configuration reg (Px_cR) bits */
1093#define MV643XX_ETH_UNICAST_NORMAL_MODE 0
1094#define MV643XX_ETH_UNICAST_PROMISCUOUS_MODE (1<<0)
1095#define MV643XX_ETH_DEFAULT_RX_QUEUE_0 0
1096#define MV643XX_ETH_DEFAULT_RX_QUEUE_1 (1<<1)
1097#define MV643XX_ETH_DEFAULT_RX_QUEUE_2 (1<<2)
1098#define MV643XX_ETH_DEFAULT_RX_QUEUE_3 ((1<<2) | (1<<1))
1099#define MV643XX_ETH_DEFAULT_RX_QUEUE_4 (1<<3)
1100#define MV643XX_ETH_DEFAULT_RX_QUEUE_5 ((1<<3) | (1<<1))
1101#define MV643XX_ETH_DEFAULT_RX_QUEUE_6 ((1<<3) | (1<<2))
1102#define MV643XX_ETH_DEFAULT_RX_QUEUE_7 ((1<<3) | (1<<2) | (1<<1))
1103#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_0 0
1104#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_1 (1<<4)
1105#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_2 (1<<5)
1106#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_3 ((1<<5) | (1<<4))
1107#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_4 (1<<6)
1108#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_5 ((1<<6) | (1<<4))
1109#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_6 ((1<<6) | (1<<5))
1110#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_7 ((1<<6) | (1<<5) | (1<<4))
1111#define MV643XX_ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
1112#define MV643XX_ETH_REJECT_BC_IF_NOT_IP_OR_ARP (1<<7)
1113#define MV643XX_ETH_RECEIVE_BC_IF_IP 0
1114#define MV643XX_ETH_REJECT_BC_IF_IP (1<<8)
1115#define MV643XX_ETH_RECEIVE_BC_IF_ARP 0
1116#define MV643XX_ETH_REJECT_BC_IF_ARP (1<<9)
1117#define MV643XX_ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY (1<<12)
1118#define MV643XX_ETH_CAPTURE_TCP_FRAMES_DIS 0
1119#define MV643XX_ETH_CAPTURE_TCP_FRAMES_EN (1<<14)
1120#define MV643XX_ETH_CAPTURE_UDP_FRAMES_DIS 0
1121#define MV643XX_ETH_CAPTURE_UDP_FRAMES_EN (1<<15)
1122#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_0 0
1123#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_1 (1<<16)
1124#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_2 (1<<17)
1125#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_3 ((1<<17) | (1<<16))
1126#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_4 (1<<18)
1127#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_5 ((1<<18) | (1<<16))
1128#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_6 ((1<<18) | (1<<17))
1129#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_7 ((1<<18) | (1<<17) | (1<<16))
1130#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_0 0
1131#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_1 (1<<19)
1132#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_2 (1<<20)
1133#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_3 ((1<<20) | (1<<19))
1134#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_4 (1<<21)
1135#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_5 ((1<<21) | (1<<19))
1136#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_6 ((1<<21) | (1<<20))
1137#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_7 ((1<<21) | (1<<20) | (1<<19))
1138#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_0 0
1139#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_1 (1<<22)
1140#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_2 (1<<23)
1141#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_3 ((1<<23) | (1<<22))
1142#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_4 (1<<24)
1143#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_5 ((1<<24) | (1<<22))
1144#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_6 ((1<<24) | (1<<23))
1145#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_7 ((1<<24) | (1<<23) | (1<<22))
1146
1147#define MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE \
1148 MV643XX_ETH_UNICAST_NORMAL_MODE | \
1149 MV643XX_ETH_DEFAULT_RX_QUEUE_0 | \
1150 MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_0 | \
1151 MV643XX_ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
1152 MV643XX_ETH_RECEIVE_BC_IF_IP | \
1153 MV643XX_ETH_RECEIVE_BC_IF_ARP | \
1154 MV643XX_ETH_CAPTURE_TCP_FRAMES_DIS | \
1155 MV643XX_ETH_CAPTURE_UDP_FRAMES_DIS | \
1156 MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_0 | \
1157 MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_0 | \
1158 MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_0
1159
1160/* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/
1161#define MV643XX_ETH_CLASSIFY_EN (1<<0)
1162#define MV643XX_ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
1163#define MV643XX_ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 (1<<1)
1164#define MV643XX_ETH_PARTITION_DISABLE 0
1165#define MV643XX_ETH_PARTITION_ENABLE (1<<2)
1166
1167#define MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE \
1168 MV643XX_ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
1169 MV643XX_ETH_PARTITION_DISABLE
1170
1171/* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */
1172#define MV643XX_ETH_RIFB (1<<0)
1173#define MV643XX_ETH_RX_BURST_SIZE_1_64BIT 0
1174#define MV643XX_ETH_RX_BURST_SIZE_2_64BIT (1<<1)
1175#define MV643XX_ETH_RX_BURST_SIZE_4_64BIT (1<<2)
1176#define MV643XX_ETH_RX_BURST_SIZE_8_64BIT ((1<<2) | (1<<1))
1177#define MV643XX_ETH_RX_BURST_SIZE_16_64BIT (1<<3)
1178#define MV643XX_ETH_BLM_RX_NO_SWAP (1<<4)
1179#define MV643XX_ETH_BLM_RX_BYTE_SWAP 0
1180#define MV643XX_ETH_BLM_TX_NO_SWAP (1<<5)
1181#define MV643XX_ETH_BLM_TX_BYTE_SWAP 0
1182#define MV643XX_ETH_DESCRIPTORS_BYTE_SWAP (1<<6)
1183#define MV643XX_ETH_DESCRIPTORS_NO_SWAP 0
1184#define MV643XX_ETH_TX_BURST_SIZE_1_64BIT 0
1185#define MV643XX_ETH_TX_BURST_SIZE_2_64BIT (1<<22)
1186#define MV643XX_ETH_TX_BURST_SIZE_4_64BIT (1<<23)
1187#define MV643XX_ETH_TX_BURST_SIZE_8_64BIT ((1<<23) | (1<<22))
1188#define MV643XX_ETH_TX_BURST_SIZE_16_64BIT (1<<24)
1189
1190#define MV643XX_ETH_IPG_INT_RX(value) ((value & 0x3fff) << 8)
1191
1192#define MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE \
1193 MV643XX_ETH_RX_BURST_SIZE_4_64BIT | \
1194 MV643XX_ETH_IPG_INT_RX(0) | \
1195 MV643XX_ETH_TX_BURST_SIZE_4_64BIT
1196
1197/* These macros describe Ethernet Port serial control reg (PSCR) bits */
1198#define MV643XX_ETH_SERIAL_PORT_DISABLE 0
1199#define MV643XX_ETH_SERIAL_PORT_ENABLE (1<<0)
1200#define MV643XX_ETH_FORCE_LINK_PASS (1<<1)
1201#define MV643XX_ETH_DO_NOT_FORCE_LINK_PASS 0
1202#define MV643XX_ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
1203#define MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX (1<<2)
1204#define MV643XX_ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
1205#define MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1<<3)
1206#define MV643XX_ETH_ADV_NO_FLOW_CTRL 0
1207#define MV643XX_ETH_ADV_SYMMETRIC_FLOW_CTRL (1<<4)
1208#define MV643XX_ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
1209#define MV643XX_ETH_FORCE_FC_MODE_TX_PAUSE_DIS (1<<5)
1210#define MV643XX_ETH_FORCE_BP_MODE_NO_JAM 0
1211#define MV643XX_ETH_FORCE_BP_MODE_JAM_TX (1<<7)
1212#define MV643XX_ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1<<8)
1213#define MV643XX_ETH_SERIAL_PORT_CONTROL_RESERVED (1<<9)
1214#define MV643XX_ETH_FORCE_LINK_FAIL 0
1215#define MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL (1<<10)
1216#define MV643XX_ETH_RETRANSMIT_16_ATTEMPTS 0
1217#define MV643XX_ETH_RETRANSMIT_FOREVER (1<<11)
1218#define MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII (1<<13)
1219#define MV643XX_ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
1220#define MV643XX_ETH_DTE_ADV_0 0
1221#define MV643XX_ETH_DTE_ADV_1 (1<<14)
1222#define MV643XX_ETH_DISABLE_AUTO_NEG_BYPASS 0
1223#define MV643XX_ETH_ENABLE_AUTO_NEG_BYPASS (1<<15)
1224#define MV643XX_ETH_AUTO_NEG_NO_CHANGE 0
1225#define MV643XX_ETH_RESTART_AUTO_NEG (1<<16)
1226#define MV643XX_ETH_MAX_RX_PACKET_1518BYTE 0
1227#define MV643XX_ETH_MAX_RX_PACKET_1522BYTE (1<<17)
1228#define MV643XX_ETH_MAX_RX_PACKET_1552BYTE (1<<18)
1229#define MV643XX_ETH_MAX_RX_PACKET_9022BYTE ((1<<18) | (1<<17))
1230#define MV643XX_ETH_MAX_RX_PACKET_9192BYTE (1<<19)
1231#define MV643XX_ETH_MAX_RX_PACKET_9700BYTE ((1<<19) | (1<<17))
1232#define MV643XX_ETH_SET_EXT_LOOPBACK (1<<20)
1233#define MV643XX_ETH_CLR_EXT_LOOPBACK 0
1234#define MV643XX_ETH_SET_FULL_DUPLEX_MODE (1<<21)
1235#define MV643XX_ETH_SET_HALF_DUPLEX_MODE 0
1236#define MV643XX_ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1<<22)
1237#define MV643XX_ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
1238#define MV643XX_ETH_SET_GMII_SPEED_TO_10_100 0
1239#define MV643XX_ETH_SET_GMII_SPEED_TO_1000 (1<<23)
1240#define MV643XX_ETH_SET_MII_SPEED_TO_10 0
1241#define MV643XX_ETH_SET_MII_SPEED_TO_100 (1<<24)
1242
1243#define MV643XX_ETH_MAX_RX_PACKET_MASK (0x7<<17)
1244
1245#define MV643XX_ETH_PORT_SERIAL_CONTROL_DEFAULT_VALUE \
1246 MV643XX_ETH_DO_NOT_FORCE_LINK_PASS | \
1247 MV643XX_ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
1248 MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
1249 MV643XX_ETH_ADV_SYMMETRIC_FLOW_CTRL | \
1250 MV643XX_ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
1251 MV643XX_ETH_FORCE_BP_MODE_NO_JAM | \
1252 (1<<9) /* reserved */ | \
1253 MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL | \
1254 MV643XX_ETH_RETRANSMIT_16_ATTEMPTS | \
1255 MV643XX_ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
1256 MV643XX_ETH_DTE_ADV_0 | \
1257 MV643XX_ETH_DISABLE_AUTO_NEG_BYPASS | \
1258 MV643XX_ETH_AUTO_NEG_NO_CHANGE | \
1259 MV643XX_ETH_MAX_RX_PACKET_9700BYTE | \
1260 MV643XX_ETH_CLR_EXT_LOOPBACK | \
1261 MV643XX_ETH_SET_FULL_DUPLEX_MODE | \
1262 MV643XX_ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
1263
1264/* These macros describe Ethernet Serial Status reg (PSR) bits */
1265#define MV643XX_ETH_PORT_STATUS_MODE_10_BIT (1<<0)
1266#define MV643XX_ETH_PORT_STATUS_LINK_UP (1<<1)
1267#define MV643XX_ETH_PORT_STATUS_FULL_DUPLEX (1<<2)
1268#define MV643XX_ETH_PORT_STATUS_FLOW_CONTROL (1<<3)
1269#define MV643XX_ETH_PORT_STATUS_GMII_1000 (1<<4)
1270#define MV643XX_ETH_PORT_STATUS_MII_100 (1<<5)
1271/* PSR bit 6 is undocumented */
1272#define MV643XX_ETH_PORT_STATUS_TX_IN_PROGRESS (1<<7)
1273#define MV643XX_ETH_PORT_STATUS_AUTONEG_BYPASSED (1<<8)
1274#define MV643XX_ETH_PORT_STATUS_PARTITION (1<<9)
1275#define MV643XX_ETH_PORT_STATUS_TX_FIFO_EMPTY (1<<10)
1276/* PSR bits 11-31 are reserved */
1277
1278#define MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
1279#define MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
1280
1281#define MV643XX_ETH_DESC_SIZE 64
1282
1283#define MV643XX_ETH_SHARED_NAME "mv643xx_eth_shared"
1284#define MV643XX_ETH_NAME "mv643xx_eth"
1285
1286struct mv643xx_eth_platform_data {
1287 int port_number;
1288 u16 force_phy_addr; /* force override if phy_addr == 0 */
1289 u16 phy_addr;
1290
1291 /* If speed is 0, then speed and duplex are autonegotiated. */
1292 int speed; /* 0, SPEED_10, SPEED_100, SPEED_1000 */
1293 int duplex; /* DUPLEX_HALF or DUPLEX_FULL */
1294
1295 /* non-zero values of the following fields override defaults */
1296 u32 tx_queue_size;
1297 u32 rx_queue_size;
1298 u32 tx_sram_addr;
1299 u32 tx_sram_size;
1300 u32 rx_sram_addr;
1301 u32 rx_sram_size;
1302 u8 mac_addr[6]; /* mac address if non-zero*/
1303};
1304
1305/* Watchdog Platform Device, Driver Data */ 979/* Watchdog Platform Device, Driver Data */
1306#define MV64x60_WDT_NAME "mv64x60_wdt" 980#define MV64x60_WDT_NAME "mv64x60_wdt"
1307 981
diff --git a/include/linux/mv643xx_eth.h b/include/linux/mv643xx_eth.h
new file mode 100644
index 000000000000..3f272396642b
--- /dev/null
+++ b/include/linux/mv643xx_eth.h
@@ -0,0 +1,31 @@
1/*
2 * MV-643XX ethernet platform device data definition file.
3 */
4#ifndef __LINUX_MV643XX_ETH_H
5#define __LINUX_MV643XX_ETH_H
6
7#define MV643XX_ETH_SHARED_NAME "mv643xx_eth_shared"
8#define MV643XX_ETH_NAME "mv643xx_eth"
9#define MV643XX_ETH_SHARED_REGS 0x2000
10#define MV643XX_ETH_SHARED_REGS_SIZE 0x2000
11
12struct mv643xx_eth_platform_data {
13 int port_number;
14 u16 force_phy_addr; /* force override if phy_addr == 0 */
15 u16 phy_addr;
16
17 /* If speed is 0, then speed and duplex are autonegotiated. */
18 int speed; /* 0, SPEED_10, SPEED_100, SPEED_1000 */
19 int duplex; /* DUPLEX_HALF or DUPLEX_FULL */
20
21 /* non-zero values of the following fields override defaults */
22 u32 tx_queue_size;
23 u32 rx_queue_size;
24 u32 tx_sram_addr;
25 u32 tx_sram_size;
26 u32 rx_sram_addr;
27 u32 rx_sram_size;
28 u8 mac_addr[6]; /* mac address if non-zero*/
29};
30
31#endif /* __LINUX_MV643XX_ETH_H */
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-05 14:18:37 -0400