litmus-rt.git - The LITMUS^RT kernel.

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author	Amit Kucheria <amit.kucheria@verdurent.com>	2008-11-25 18:11:12 -0500
committer	Tony Lindgren <tony@atomide.com>	2008-11-25 18:11:12 -0500
commit	147dcf5489fb86c4bfe400520186f9f11b304783 (patch)
tree	4ca9f7129caaae9d281b99a5dbc2156787af788b /include/linux/sysdev.h
parent	7953031da4200323ab5d85bd514054ca4ba9d225 (diff)

ARM: OMAP: Typo fix for clock_allow_idle

The second clk_deny_idle instance should be clk_allow_idle instead. Signed-off-by: Amit Kucheria <amit.kucheria@verdurent.com> Signed-off-by: Tony Lindgren <tony@atomide.com>

Diffstat (limited to 'include/linux/sysdev.h')

0 files changed, 0 insertions, 0 deletions

/* * Driver for Atmel Pulse Width Modulation Controller * * Copyright (C) 2013 Atmel Corporation * Bo Shen <voice.shen@atmel.com> * * Licensed under GPLv2. */ #include <linux/clk.h> #include <linux/delay.h> #include <linux/err.h> #include <linux/io.h> #include <linux/module.h> #include <linux/mutex.h> #include <linux/of.h> #include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/pwm.h> #include <linux/slab.h> /* The following is global registers for PWM controller */ #define PWM_ENA 0x04 #define PWM_DIS 0x08 #define PWM_SR 0x0C #define PWM_ISR 0x1C /* Bit field in SR */ #define PWM_SR_ALL_CH_ON 0x0F /* The following register is PWM channel related registers */ #define PWM_CH_REG_OFFSET 0x200 #define PWM_CH_REG_SIZE 0x20 #define PWM_CMR 0x0 /* Bit field in CMR */ #define PWM_CMR_CPOL (1 << 9) #define PWM_CMR_UPD_CDTY (1 << 10) #define PWM_CMR_CPRE_MSK 0xF /* The following registers for PWM v1 */ #define PWMV1_CDTY 0x04 #define PWMV1_CPRD 0x08 #define PWMV1_CUPD 0x10 /* The following registers for PWM v2 */ #define PWMV2_CDTY 0x04 #define PWMV2_CDTYUPD 0x08 #define PWMV2_CPRD 0x0C #define PWMV2_CPRDUPD 0x10 /* * Max value for duty and period * * Although the duty and period register is 32 bit, * however only the LSB 16 bits are significant. */ #define PWM_MAX_DTY 0xFFFF #define PWM_MAX_PRD 0xFFFF #define PRD_MAX_PRES 10 struct atmel_pwm_registers { u8 period; u8 period_upd; u8 duty; u8 duty_upd; }; struct atmel_pwm_chip { struct pwm_chip chip; struct clk *clk; void __iomem *base; const struct atmel_pwm_registers *regs; unsigned int updated_pwms; /* ISR is cleared when read, ensure only one thread does that */ struct mutex isr_lock; }; static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip) { return container_of(chip, struct atmel_pwm_chip, chip); } static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip, unsigned long offset) { return readl_relaxed(chip->base + offset); } static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip, unsigned long offset, unsigned long val) { writel_relaxed(val, chip->base + offset); } static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip, unsigned int ch, unsigned long offset) { unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE; return readl_relaxed(chip->base + base + offset); } static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip, unsigned int ch, unsigned long offset, unsigned long val) { unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE; writel_relaxed(val, chip->base + base + offset); } static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip, const struct pwm_state *state, unsigned long *cprd, u32 *pres) { struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip); unsigned long long cycles = state->period; /* Calculate the period cycles and prescale value */ cycles *= clk_get_rate(atmel_pwm->clk); do_div(cycles, NSEC_PER_SEC); for (*pres = 0; cycles > PWM_MAX_PRD; cycles >>= 1) (*pres)++; if (*pres > PRD_MAX_PRES) { dev_err(chip->dev, "pres exceeds the maximum value\n"); return -EINVAL; } *cprd = cycles; return 0; } static void atmel_pwm_calculate_cdty(const struct pwm_state *state, unsigned long cprd, unsigned long *cdty) { unsigned long long cycles = state->duty_cycle; cycles *= cprd; do_div(cycles, state->period); *cdty = cprd - cycles; } static void atmel_pwm_update_cdty(struct pwm_chip *chip, struct pwm_device *pwm, unsigned long cdty) { struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip); u32 val; if (atmel_pwm->regs->duty_upd == atmel_pwm->regs->period_upd) { val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); val &= ~PWM_CMR_UPD_CDTY; atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); } atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, atmel_pwm->regs->duty_upd, cdty); } static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip, struct pwm_device *pwm, unsigned long cprd, unsigned long cdty) { struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip); atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, atmel_pwm->regs->duty, cdty); atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, atmel_pwm->regs->period, cprd); } static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm, bool disable_clk) { struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip); unsigned long timeout = jiffies + 2 * HZ; /* * Wait for at least a complete period to have passed before disabling a * channel to be sure that CDTY has been updated */ mutex_lock(&atmel_pwm->isr_lock); atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR); while (!(atmel_pwm->updated_pwms & (1 << pwm->hwpwm)) && time_before(jiffies, timeout)) { usleep_range(10, 100); atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR); } mutex_unlock(&atmel_pwm->isr_lock); atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm); /* * Wait for the PWM channel disable operation to be effective before * stopping the clock. */ timeout = jiffies + 2 * HZ; while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) && time_before(jiffies, timeout)) usleep_range(10, 100); if (disable_clk) clk_disable(atmel_pwm->clk); } static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, struct pwm_state *state) { struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip); struct pwm_state cstate; unsigned long cprd, cdty; u32 pres, val; int ret; pwm_get_state(pwm, &cstate); if (state->enabled) { if (cstate.enabled && cstate.polarity == state->polarity && cstate.period == state->period) { cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, atmel_pwm->regs->period); atmel_pwm_calculate_cdty(state, cprd, &cdty); atmel_pwm_update_cdty(chip, pwm, cdty); return 0; } ret = atmel_pwm_calculate_cprd_and_pres(chip, state, &cprd, &pres); if (ret) { dev_err(chip->dev, "failed to calculate cprd and prescaler\n"); return ret; } atmel_pwm_calculate_cdty(state, cprd, &cdty);


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