diff options
| author | Rafał Miłecki <zajec5@gmail.com> | 2014-07-15 10:18:57 -0400 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2014-07-18 13:45:24 -0400 |
| commit | 6ad59343ecd72dd3f83c4db3bcddbb0beabb4c4c (patch) | |
| tree | fb55cc9354e5bee07815ce73f042ed911e2e065d /include/linux/ssb | |
| parent | 72269146afabf1656f867f715f40a7dd470499fb (diff) | |
ssb: extract power info from SPROM revs 4 and 5
This is needed to properly handle early 802.11n devices like BCM4321.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'include/linux/ssb')
| -rw-r--r-- | include/linux/ssb/ssb_regs.h | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/include/linux/ssb/ssb_regs.h b/include/linux/ssb/ssb_regs.h index f9f931c89e3e..f7b9100686c3 100644 --- a/include/linux/ssb/ssb_regs.h +++ b/include/linux/ssb/ssb_regs.h | |||
| @@ -345,6 +345,43 @@ | |||
| 345 | #define SSB_SPROM4_TXPID5GH2_SHIFT 0 | 345 | #define SSB_SPROM4_TXPID5GH2_SHIFT 0 |
| 346 | #define SSB_SPROM4_TXPID5GH3 0xFF00 | 346 | #define SSB_SPROM4_TXPID5GH3 0xFF00 |
| 347 | #define SSB_SPROM4_TXPID5GH3_SHIFT 8 | 347 | #define SSB_SPROM4_TXPID5GH3_SHIFT 8 |
| 348 | |||
| 349 | /* There are 4 blocks with power info sharing the same layout */ | ||
| 350 | #define SSB_SPROM4_PWR_INFO_CORE0 0x0080 | ||
| 351 | #define SSB_SPROM4_PWR_INFO_CORE1 0x00AE | ||
| 352 | #define SSB_SPROM4_PWR_INFO_CORE2 0x00DC | ||
| 353 | #define SSB_SPROM4_PWR_INFO_CORE3 0x010A | ||
| 354 | |||
| 355 | #define SSB_SPROM4_2G_MAXP_ITSSI 0x00 /* 2 GHz ITSSI and 2 GHz Max Power */ | ||
| 356 | #define SSB_SPROM4_2G_MAXP 0x00FF | ||
| 357 | #define SSB_SPROM4_2G_ITSSI 0xFF00 | ||
| 358 | #define SSB_SPROM4_2G_ITSSI_SHIFT 8 | ||
| 359 | #define SSB_SPROM4_2G_PA_0 0x02 /* 2 GHz power amp */ | ||
| 360 | #define SSB_SPROM4_2G_PA_1 0x04 | ||
| 361 | #define SSB_SPROM4_2G_PA_2 0x06 | ||
| 362 | #define SSB_SPROM4_2G_PA_3 0x08 | ||
| 363 | #define SSB_SPROM4_5G_MAXP_ITSSI 0x0A /* 5 GHz ITSSI and 5.3 GHz Max Power */ | ||
| 364 | #define SSB_SPROM4_5G_MAXP 0x00FF | ||
| 365 | #define SSB_SPROM4_5G_ITSSI 0xFF00 | ||
| 366 | #define SSB_SPROM4_5G_ITSSI_SHIFT 8 | ||
| 367 | #define SSB_SPROM4_5GHL_MAXP 0x0C /* 5.2 GHz and 5.8 GHz Max Power */ | ||
| 368 | #define SSB_SPROM4_5GH_MAXP 0x00FF | ||
| 369 | #define SSB_SPROM4_5GL_MAXP 0xFF00 | ||
| 370 | #define SSB_SPROM4_5GL_MAXP_SHIFT 8 | ||
| 371 | #define SSB_SPROM4_5G_PA_0 0x0E /* 5.3 GHz power amp */ | ||
| 372 | #define SSB_SPROM4_5G_PA_1 0x10 | ||
| 373 | #define SSB_SPROM4_5G_PA_2 0x12 | ||
| 374 | #define SSB_SPROM4_5G_PA_3 0x14 | ||
| 375 | #define SSB_SPROM4_5GL_PA_0 0x16 /* 5.2 GHz power amp */ | ||
| 376 | #define SSB_SPROM4_5GL_PA_1 0x18 | ||
| 377 | #define SSB_SPROM4_5GL_PA_2 0x1A | ||
| 378 | #define SSB_SPROM4_5GL_PA_3 0x1C | ||
| 379 | #define SSB_SPROM4_5GH_PA_0 0x1E /* 5.8 GHz power amp */ | ||
| 380 | #define SSB_SPROM4_5GH_PA_1 0x20 | ||
| 381 | #define SSB_SPROM4_5GH_PA_2 0x22 | ||
| 382 | #define SSB_SPROM4_5GH_PA_3 0x24 | ||
| 383 | |||
| 384 | /* TODO: Make it deprecated */ | ||
| 348 | #define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */ | 385 | #define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */ |
| 349 | #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */ | 386 | #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */ |
| 350 | #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */ | 387 | #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */ |
