diff options
author | Paul Mundt <lethal@linux-sh.org> | 2012-04-10 23:05:50 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2012-04-10 23:05:50 -0400 |
commit | 4d6ddb08acc48368c5b7ac431f9d00db7227d2ed (patch) | |
tree | 5030162ef3c2f9954e43baf02cff7f8794a8ba74 /include/linux/sh_clk.h | |
parent | a9e1e53bcfb29b3b503a5e75ce498d9a64f32c1e (diff) |
sh: clkfwk: Support variable size accesses for MSTP clocks.
The bulk of the MSTP users require 32-bit access, but this isn't the case
for some of the SH-2A parts, so add in some basic infrastructure to let
the CPU define its required access size in preparation.
Requested-by: Phil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/linux/sh_clk.h')
-rw-r--r-- | include/linux/sh_clk.h | 34 |
1 files changed, 31 insertions, 3 deletions
diff --git a/include/linux/sh_clk.h b/include/linux/sh_clk.h index 0a9d8f2ac519..c513b73cd7cb 100644 --- a/include/linux/sh_clk.h +++ b/include/linux/sh_clk.h | |||
@@ -59,7 +59,15 @@ struct clk { | |||
59 | unsigned int nr_freqs; | 59 | unsigned int nr_freqs; |
60 | }; | 60 | }; |
61 | 61 | ||
62 | #define CLK_ENABLE_ON_INIT (1 << 0) | 62 | #define CLK_ENABLE_ON_INIT BIT(0) |
63 | |||
64 | #define CLK_ENABLE_REG_32BIT BIT(1) /* default access size */ | ||
65 | #define CLK_ENABLE_REG_16BIT BIT(2) | ||
66 | #define CLK_ENABLE_REG_8BIT BIT(3) | ||
67 | |||
68 | #define CLK_ENABLE_REG_MASK (CLK_ENABLE_REG_32BIT | \ | ||
69 | CLK_ENABLE_REG_16BIT | \ | ||
70 | CLK_ENABLE_REG_8BIT) | ||
63 | 71 | ||
64 | /* drivers/sh/clk.c */ | 72 | /* drivers/sh/clk.c */ |
65 | unsigned long followparent_recalc(struct clk *); | 73 | unsigned long followparent_recalc(struct clk *); |
@@ -102,7 +110,7 @@ long clk_round_parent(struct clk *clk, unsigned long target, | |||
102 | unsigned long *best_freq, unsigned long *parent_freq, | 110 | unsigned long *best_freq, unsigned long *parent_freq, |
103 | unsigned int div_min, unsigned int div_max); | 111 | unsigned int div_min, unsigned int div_max); |
104 | 112 | ||
105 | #define SH_CLK_MSTP32(_parent, _enable_reg, _enable_bit, _flags) \ | 113 | #define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _flags) \ |
106 | { \ | 114 | { \ |
107 | .parent = _parent, \ | 115 | .parent = _parent, \ |
108 | .enable_reg = (void __iomem *)_enable_reg, \ | 116 | .enable_reg = (void __iomem *)_enable_reg, \ |
@@ -110,7 +118,27 @@ long clk_round_parent(struct clk *clk, unsigned long target, | |||
110 | .flags = _flags, \ | 118 | .flags = _flags, \ |
111 | } | 119 | } |
112 | 120 | ||
113 | int sh_clk_mstp32_register(struct clk *clks, int nr); | 121 | #define SH_CLK_MSTP32(_p, _r, _b, _f) \ |
122 | SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_32BIT) | ||
123 | |||
124 | #define SH_CLK_MSTP16(_p, _r, _b, _f) \ | ||
125 | SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_16BIT) | ||
126 | |||
127 | #define SH_CLK_MSTP8(_p, _r, _b, _f) \ | ||
128 | SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_8BIT) | ||
129 | |||
130 | int sh_clk_mstp_register(struct clk *clks, int nr); | ||
131 | |||
132 | /* | ||
133 | * MSTP registration never really cared about access size, despite the | ||
134 | * original enable/disable pairs assuming a 32-bit access. Clocks are | ||
135 | * responsible for defining their access sizes either directly or via the | ||
136 | * clock definition wrappers. | ||
137 | */ | ||
138 | static inline int __deprecated sh_clk_mstp32_register(struct clk *clks, int nr) | ||
139 | { | ||
140 | return sh_clk_mstp_register(clks, nr); | ||
141 | } | ||
114 | 142 | ||
115 | #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \ | 143 | #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \ |
116 | { \ | 144 | { \ |