Merge branch 'master' into for-next

Fast-forward merge with Linus to be able to merge patches
based on more recent version of the tree.

1 files changed, 75 insertions, 0 deletions

diff --git a/include/linux/serial_sci.h b/include/linux/serial_sci.h
index a2afc9fbe186..8bffe9ae2ca0 100644
--- a/include/linux/serial_sci.h
+++ b/include/linux/serial_sci.h
@@ -8,6 +8,8 @@
  * Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts)
  */
 
+#define SCIx_NOT_SUPPORTED      (-1)
+
 enum {
         SCBRR_ALGO_1,           /* ((clk + 16 * bps) / (16 * bps) - 1) */
         SCBRR_ALGO_2,           /* ((clk + 16 * bps) / (32 * bps) - 1) */
@@ -25,6 +27,28 @@ enum {
 #define SCSCR_CKE1      (1 << 1)
 #define SCSCR_CKE0      (1 << 0)
 
+/* SCxSR SCI */
+#define SCI_TDRE  0x80
+#define SCI_RDRF  0x40
+#define SCI_ORER  0x20
+#define SCI_FER   0x10
+#define SCI_PER   0x08
+#define SCI_TEND  0x04
+
+#define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)
+
+/* SCxSR SCIF */
+#define SCIF_ER    0x0080
+#define SCIF_TEND  0x0040
+#define SCIF_TDFE  0x0020
+#define SCIF_BRK   0x0010
+#define SCIF_FER   0x0008
+#define SCIF_PER   0x0004
+#define SCIF_RDF   0x0002
+#define SCIF_DR    0x0001
+
+#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
+
 /* Offsets into the sci_port->irqs array */
 enum {
         SCIx_ERI_IRQ,
@@ -32,6 +56,24 @@ enum {
         SCIx_TXI_IRQ,
         SCIx_BRI_IRQ,
         SCIx_NR_IRQS,
+
+        SCIx_MUX_IRQ = SCIx_NR_IRQS,    /* special case */
+};
+
+enum {
+        SCIx_PROBE_REGTYPE,
+
+        SCIx_SCI_REGTYPE,
+        SCIx_IRDA_REGTYPE,
+        SCIx_SCIFA_REGTYPE,
+        SCIx_SCIFB_REGTYPE,
+        SCIx_SH3_SCIF_REGTYPE,
+        SCIx_SH4_SCIF_REGTYPE,
+        SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
+        SCIx_SH4_SCIF_FIFODATA_REGTYPE,
+        SCIx_SH7705_SCIF_REGTYPE,
+
+        SCIx_NR_REGTYPES,
 };
 
 #define SCIx_IRQ_MUXED(irq)             \
@@ -42,8 +84,29 @@ enum {
         [SCIx_BRI_IRQ]  = (irq),        \
 }
 
+#define SCIx_IRQ_IS_MUXED(port)                 \
+        ((port)->cfg->irqs[SCIx_ERI_IRQ] ==     \
+         (port)->cfg->irqs[SCIx_RXI_IRQ]) ||    \
+        ((port)->cfg->irqs[SCIx_ERI_IRQ] &&     \
+         !(port)->cfg->irqs[SCIx_RXI_IRQ])
+/*
+ * SCI register subset common for all port types.
+ * Not all registers will exist on all parts.
+ */
+enum {
+        SCSMR, SCBRR, SCSCR, SCxSR,
+        SCFCR, SCFDR, SCxTDR, SCxRDR,
+        SCLSR, SCTFDR, SCRFDR, SCSPTR,
+
+        SCIx_NR_REGS,
+};
+
 struct device;
 
+struct plat_sci_port_ops {
+        void (*init_pins)(struct uart_port *, unsigned int cflag);
+};
+
 /*
  * Platform device specific platform_data struct
  */
@@ -56,6 +119,18 @@ struct plat_sci_port {
         unsigned int    scbrr_algo_id;          /* SCBRR calculation algo */
         unsigned int    scscr;                  /* SCSCR initialization */
 
+        /*
+         * Platform overrides if necessary, defaults otherwise.
+         */
+        int             overrun_bit;
+        unsigned int    error_mask;
+
+        int             port_reg;
+        unsigned char   regshift;
+        unsigned char   regtype;
+
+        struct plat_sci_port_ops        *ops;
+
         struct device   *dma_dev;
 
         unsigned int    dma_slave_tx;