rtc: add driver for DS1685 family of real time clocks

This adds a driver for the Dallas/Maxim DS1685-family of RTC chips.  It
supports the DS1685/DS1687, DS1688/DS1691, DS1689/DS1693, DS17285/DS17287,
DS17485/DS17487, and DS17885/DS17887 RTC chips.  These chips are commonly
found in SGI O2 and SGI Octane systems.  It was originally derived from a
driver patch submitted by Matthias Fuchs many years ago for use in
EPPC-405-UC modules, which also used these RTCs.  In addition to the
time-keeping functions, this RTC also handles the shutdown mechanism of
the O2 and Octane and acts as a partial NVRAM for the boot PROMS in these
systems.

Verified on both an SGI O2 and an SGI Octane.

Signed-off-by: Joshua Kinard <kumba@gentoo.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Alessandro Zummo <a.zummo@towertech.it>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

1 files changed, 375 insertions, 0 deletions

diff --git a/include/linux/rtc/ds1685.h b/include/linux/rtc/ds1685.h
new file mode 100644
index 000000000000..e6337a56d741
--- /dev/null
+++ b/include/linux/rtc/ds1685.h
@@ -0,0 +1,375 @@
+/*
+ * Definitions for the registers, addresses, and platform data of the
+ * DS1685/DS1687-series RTC chips.
+ *
+ * This Driver also works for the DS17X85/DS17X87 RTC chips.  Functionally
+ * similar to the DS1685/DS1687, they support a few extra features which
+ * include larger, battery-backed NV-SRAM, burst-mode access, and an RTC
+ * write counter.
+ *
+ * Copyright (C) 2011-2014 Joshua Kinard <kumba@gentoo.org>.
+ * Copyright (C) 2009 Matthias Fuchs <matthias.fuchs@esd-electronics.com>.
+ *
+ * References:
+ *    DS1685/DS1687 3V/5V Real-Time Clocks, 19-5215, Rev 4/10.
+ *    DS17x85/DS17x87 3V/5V Real-Time Clocks, 19-5222, Rev 4/10.
+ *    DS1689/DS1693 3V/5V Serialized Real-Time Clocks, Rev 112105.
+ *    Application Note 90, Using the Multiplex Bus RTC Extended Features.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _LINUX_RTC_DS1685_H_
+#define _LINUX_RTC_DS1685_H_
+
+#include <linux/rtc.h>
+#include <linux/platform_device.h>
+#include <linux/workqueue.h>
+
+/**
+ * struct ds1685_priv - DS1685 private data structure.
+ * @dev: pointer to the rtc_device structure.
+ * @regs: iomapped base address pointer of the RTC registers.
+ * @regstep: padding/step size between registers (optional).
+ * @baseaddr: base address of the RTC device.
+ * @size: resource size.
+ * @lock: private lock variable for spin locking/unlocking.
+ * @work: private workqueue.
+ * @irq: IRQ number assigned to the RTC device.
+ * @prepare_poweroff: pointer to platform pre-poweroff function.
+ * @wake_alarm: pointer to platform wake alarm function.
+ * @post_ram_clear: pointer to platform post ram-clear function.
+ */
+struct ds1685_priv {
+        struct rtc_device *dev;
+        void __iomem *regs;
+        u32 regstep;
+        resource_size_t baseaddr;
+        size_t size;
+        spinlock_t lock;
+        struct work_struct work;
+        int irq_num;
+        bool bcd_mode;
+        bool no_irq;
+        bool uie_unsupported;
+        bool alloc_io_resources;
+        u8 (*read)(struct ds1685_priv *, int);
+        void (*write)(struct ds1685_priv *, int, u8);
+        void (*prepare_poweroff)(void);
+        void (*wake_alarm)(void);
+        void (*post_ram_clear)(void);
+};
+
+
+/**
+ * struct ds1685_rtc_platform_data - platform data structure.
+ * @plat_prepare_poweroff: platform-specific pre-poweroff function.
+ * @plat_wake_alarm: platform-specific wake alarm function.
+ * @plat_post_ram_clear: platform-specific post ram-clear function.
+ *
+ * If your platform needs to use a custom padding/step size between
+ * registers, or uses one or more of the extended interrupts and needs special
+ * handling, then include this header file in your platform definition and
+ * set regstep and the plat_* pointers as appropriate.
+ */
+struct ds1685_rtc_platform_data {
+        const u32 regstep;
+        const bool bcd_mode;
+        const bool no_irq;
+        const bool uie_unsupported;
+        const bool alloc_io_resources;
+        u8 (*plat_read)(struct ds1685_priv *, int);
+        void (*plat_write)(struct ds1685_priv *, int, u8);
+        void (*plat_prepare_poweroff)(void);
+        void (*plat_wake_alarm)(void);
+        void (*plat_post_ram_clear)(void);
+};
+
+
+/*
+ * Time Registers.
+ */
+#define RTC_SECS                0x00    /* Seconds 00-59 */
+#define RTC_SECS_ALARM          0x01    /* Alarm Seconds 00-59 */
+#define RTC_MINS                0x02    /* Minutes 00-59 */
+#define RTC_MINS_ALARM          0x03    /* Alarm Minutes 00-59 */
+#define RTC_HRS                 0x04    /* Hours 01-12 AM/PM || 00-23 */
+#define RTC_HRS_ALARM           0x05    /* Alarm Hours 01-12 AM/PM || 00-23 */
+#define RTC_WDAY                0x06    /* Day of Week 01-07 */
+#define RTC_MDAY                0x07    /* Day of Month 01-31 */
+#define RTC_MONTH               0x08    /* Month 01-12 */
+#define RTC_YEAR                0x09    /* Year 00-99 */
+#define RTC_CENTURY             0x48    /* Century 00-99 */
+#define RTC_MDAY_ALARM          0x49    /* Alarm Day of Month 01-31 */
+
+
+/*
+ * Bit masks for the Time registers in BCD Mode (DM = 0).
+ */
+#define RTC_SECS_BCD_MASK       0x7f    /* - x x x x x x x */
+#define RTC_MINS_BCD_MASK       0x7f    /* - x x x x x x x */
+#define RTC_HRS_12_BCD_MASK     0x1f    /* - - - x x x x x */
+#define RTC_HRS_24_BCD_MASK     0x3f    /* - - x x x x x x */
+#define RTC_MDAY_BCD_MASK       0x3f    /* - - x x x x x x */
+#define RTC_MONTH_BCD_MASK      0x1f    /* - - - x x x x x */
+#define RTC_YEAR_BCD_MASK       0xff    /* x x x x x x x x */
+
+/*
+ * Bit masks for the Time registers in BIN Mode (DM = 1).
+ */
+#define RTC_SECS_BIN_MASK       0x3f    /* - - x x x x x x */
+#define RTC_MINS_BIN_MASK       0x3f    /* - - x x x x x x */
+#define RTC_HRS_12_BIN_MASK     0x0f    /* - - - - x x x x */
+#define RTC_HRS_24_BIN_MASK     0x1f    /* - - - x x x x x */
+#define RTC_MDAY_BIN_MASK       0x1f    /* - - - x x x x x */
+#define RTC_MONTH_BIN_MASK      0x0f    /* - - - - x x x x */
+#define RTC_YEAR_BIN_MASK       0x7f    /* - x x x x x x x */
+
+/*
+ * Bit masks common for the Time registers in BCD or BIN Mode.
+ */
+#define RTC_WDAY_MASK           0x07    /* - - - - - x x x */
+#define RTC_CENTURY_MASK        0xff    /* x x x x x x x x */
+#define RTC_MDAY_ALARM_MASK     0xff    /* x x x x x x x x */
+#define RTC_HRS_AMPM_MASK       BIT(7)  /* Mask for the AM/PM bit */
+
+
+
+/*
+ * Control Registers.
+ */
+#define RTC_CTRL_A              0x0a    /* Control Register A */
+#define RTC_CTRL_B              0x0b    /* Control Register B */
+#define RTC_CTRL_C              0x0c    /* Control Register C */
+#define RTC_CTRL_D              0x0d    /* Control Register D */
+#define RTC_EXT_CTRL_4A         0x4a    /* Extended Control Register 4A */
+#define RTC_EXT_CTRL_4B         0x4b    /* Extended Control Register 4B */
+
+
+/*
+ * Bit names in Control Register A.
+ */
+#define RTC_CTRL_A_UIP          BIT(7)  /* Update In Progress */
+#define RTC_CTRL_A_DV2          BIT(6)  /* Countdown Chain */
+#define RTC_CTRL_A_DV1          BIT(5)  /* Oscillator Enable */
+#define RTC_CTRL_A_DV0          BIT(4)  /* Bank Select */
+#define RTC_CTRL_A_RS2          BIT(2)  /* Rate-Selection Bit 2 */
+#define RTC_CTRL_A_RS3          BIT(3)  /* Rate-Selection Bit 3 */
+#define RTC_CTRL_A_RS1          BIT(1)  /* Rate-Selection Bit 1 */
+#define RTC_CTRL_A_RS0          BIT(0)  /* Rate-Selection Bit 0 */
+#define RTC_CTRL_A_RS_MASK      0x0f    /* RS3 + RS2 + RS1 + RS0 */
+
+/*
+ * Bit names in Control Register B.
+ */
+#define RTC_CTRL_B_SET          BIT(7)  /* SET Bit */
+#define RTC_CTRL_B_PIE          BIT(6)  /* Periodic-Interrupt Enable */
+#define RTC_CTRL_B_AIE          BIT(5)  /* Alarm-Interrupt Enable */
+#define RTC_CTRL_B_UIE          BIT(4)  /* Update-Ended Interrupt-Enable */
+#define RTC_CTRL_B_SQWE         BIT(3)  /* Square-Wave Enable */
+#define RTC_CTRL_B_DM           BIT(2)  /* Data Mode */
+#define RTC_CTRL_B_2412         BIT(1)  /* 12-Hr/24-Hr Mode */
+#define RTC_CTRL_B_DSE          BIT(0)  /* Daylight Savings Enable */
+#define RTC_CTRL_B_PAU_MASK     0x70    /* PIE + AIE + UIE */
+
+
+/*
+ * Bit names in Control Register C.
+ *
+ * BIT(0), BIT(1), BIT(2), & BIT(3) are unused, always return 0, and cannot
+ * be written to.
+ */
+#define RTC_CTRL_C_IRQF         BIT(7)  /* Interrupt-Request Flag */
+#define RTC_CTRL_C_PF           BIT(6)  /* Periodic-Interrupt Flag */
+#define RTC_CTRL_C_AF           BIT(5)  /* Alarm-Interrupt Flag */
+#define RTC_CTRL_C_UF           BIT(4)  /* Update-Ended Interrupt Flag */
+#define RTC_CTRL_C_PAU_MASK     0x70    /* PF + AF + UF */