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authorKishon Vijay Abraham I <kishon@ti.com>2014-06-25 13:52:57 -0400
committerKishon Vijay Abraham I <kishon@ti.com>2014-07-22 03:16:10 -0400
commitf0e2cf7b912522c9c7146d9d6e99d1b0ea5c97c6 (patch)
tree61081c79d550c40df4aa0f684e198c72eb4784d5 /include/linux/phy/omap_control_phy.h
parent99bbd48c2065552fd2d224c9f065dcac9b7e25ce (diff)
phy: pipe3: insert delay to enumerate in GEN2 mode
8-bit delay value (0xF1) is required for GEN2 devices to be enumerated consistently. Added an API to be called from PHY drivers to set this delay value and called it from PIPE3 driver to set the delay value. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Roger Quadros <rogerq@ti.com>
Diffstat (limited to 'include/linux/phy/omap_control_phy.h')
-rw-r--r--include/linux/phy/omap_control_phy.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/include/linux/phy/omap_control_phy.h b/include/linux/phy/omap_control_phy.h
index 5450403c7546..e9e6cfbfbb58 100644
--- a/include/linux/phy/omap_control_phy.h
+++ b/include/linux/phy/omap_control_phy.h
@@ -23,6 +23,7 @@ enum omap_control_phy_type {
23 OMAP_CTRL_TYPE_OTGHS = 1, /* Mailbox OTGHS_CONTROL */ 23 OMAP_CTRL_TYPE_OTGHS = 1, /* Mailbox OTGHS_CONTROL */
24 OMAP_CTRL_TYPE_USB2, /* USB2_PHY, power down in CONTROL_DEV_CONF */ 24 OMAP_CTRL_TYPE_USB2, /* USB2_PHY, power down in CONTROL_DEV_CONF */
25 OMAP_CTRL_TYPE_PIPE3, /* PIPE3 PHY, DPLL & seperate Rx/Tx power */ 25 OMAP_CTRL_TYPE_PIPE3, /* PIPE3 PHY, DPLL & seperate Rx/Tx power */
26 OMAP_CTRL_TYPE_PCIE, /* RX TX control of ACSPCIE */
26 OMAP_CTRL_TYPE_DRA7USB2, /* USB2 PHY, power and power_aux e.g. DRA7 */ 27 OMAP_CTRL_TYPE_DRA7USB2, /* USB2 PHY, power and power_aux e.g. DRA7 */
27 OMAP_CTRL_TYPE_AM437USB2, /* USB2 PHY, power e.g. AM437x */ 28 OMAP_CTRL_TYPE_AM437USB2, /* USB2 PHY, power e.g. AM437x */
28}; 29};
@@ -33,6 +34,7 @@ struct omap_control_phy {
33 u32 __iomem *otghs_control; 34 u32 __iomem *otghs_control;
34 u32 __iomem *power; 35 u32 __iomem *power;
35 u32 __iomem *power_aux; 36 u32 __iomem *power_aux;
37 u32 __iomem *pcie_pcs;
36 38
37 struct clk *sys_clk; 39 struct clk *sys_clk;
38 40
@@ -63,6 +65,9 @@ enum omap_control_usb_mode {
63#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3 65#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3
64#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0 66#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0
65 67
68#define OMAP_CTRL_PCIE_PCS_MASK 0xff
69#define OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT 0x8
70
66#define OMAP_CTRL_USB2_PHY_PD BIT(28) 71#define OMAP_CTRL_USB2_PHY_PD BIT(28)
67 72
68#define AM437X_CTRL_USB2_PHY_PD BIT(0) 73#define AM437X_CTRL_USB2_PHY_PD BIT(0)
@@ -74,6 +79,7 @@ enum omap_control_usb_mode {
74void omap_control_phy_power(struct device *dev, int on); 79void omap_control_phy_power(struct device *dev, int on);
75void omap_control_usb_set_mode(struct device *dev, 80void omap_control_usb_set_mode(struct device *dev,
76 enum omap_control_usb_mode mode); 81 enum omap_control_usb_mode mode);
82void omap_control_pcie_pcs(struct device *dev, u8 id, u8 delay);
77#else 83#else
78 84
79static inline void omap_control_phy_power(struct device *dev, int on) 85static inline void omap_control_phy_power(struct device *dev, int on)
@@ -84,6 +90,10 @@ static inline void omap_control_usb_set_mode(struct device *dev,
84 enum omap_control_usb_mode mode) 90 enum omap_control_usb_mode mode)
85{ 91{
86} 92}
93
94static inline void omap_control_pcie_pcs(struct device *dev, u8 id, u8 delay)
95{
96}
87#endif 97#endif
88 98
89#endif /* __OMAP_CONTROL_PHY_H__ */ 99#endif /* __OMAP_CONTROL_PHY_H__ */