PCI: PCIE ASPM support

PCI Express ASPM defines a protocol for PCI Express components in the D0
state to reduce Link power by placing their Links into a low power state
and instructing the other end of the Link to do likewise. This
capability allows hardware-autonomous, dynamic Link power reduction
beyond what is achievable by software-only controlled power management.
However, The device should be configured by software appropriately.
Enabling ASPM will save power, but will introduce device latency.

This patch adds ASPM support in Linux. It introduces a global policy for
ASPM, a sysfs file /sys/module/pcie_aspm/parameters/policy can control
it. The interface can be used as a boot option too. Currently we have
below setting:
        -default, BIOS default setting
        -powersave, highest power saving mode, enable all available ASPM
state
and clock power management
        -performance, highest performance, disable ASPM and clock power
management
By default, the 'default' policy is used currently.

In my test, power difference between powersave mode and performance mode
is about 1.3w in a system with 3 PCIE links.

Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

1 files changed, 8 insertions, 0 deletions

diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index c1914a8b94a9..c0c1223c9194 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -395,9 +395,17 @@
 #define  PCI_EXP_DEVSTA_AUXPD   0x10    /* AUX Power Detected */
 #define  PCI_EXP_DEVSTA_TRPND   0x20    /* Transactions Pending */
 #define PCI_EXP_LNKCAP          12      /* Link Capabilities */
+#define  PCI_EXP_LNKCAP_ASPMS   0xc00   /* ASPM Support */
+#define  PCI_EXP_LNKCAP_L0SEL   0x7000  /* L0s Exit Latency */
+#define  PCI_EXP_LNKCAP_L1EL    0x38000 /* L1 Exit Latency */
+#define  PCI_EXP_LNKCAP_CLKPM   0x40000 /* L1 Clock Power Management */
 #define PCI_EXP_LNKCTL          16      /* Link Control */
+#define  PCI_EXP_LNKCTL_RL      0x20    /* Retrain Link */
+#define  PCI_EXP_LNKCTL_CCC     0x40    /* Common Clock COnfiguration */
 #define  PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */
 #define PCI_EXP_LNKSTA          18      /* Link Status */
+#define  PCI_EXP_LNKSTA_LT      0x800   /* Link Training */
+#define  PCI_EXP_LNKSTA_SLC     0x1000  /* Slot Clock Configuration */
 #define PCI_EXP_SLTCAP          20      /* Slot Capabilities */
 #define PCI_EXP_SLTCTL          24      /* Slot Control */
 #define PCI_EXP_SLTSTA          26      /* Slot Status */