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authorLinus Torvalds <torvalds@linux-foundation.org>2009-06-23 00:38:22 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-06-23 00:38:22 -0400
commit687d680985b1438360a9ba470ece8b57cd205c3b (patch)
treeae253608531e5c3e823600974c610e722e7de759 /include/linux/pci_regs.h
parent1053414068bad659479e6efa62a67403b8b1ec0a (diff)
parent008fe148cb0fb51d266baabe2c09997b21cf90c6 (diff)
Merge git://git.infradead.org/~dwmw2/iommu-2.6.31
* git://git.infradead.org/~dwmw2/iommu-2.6.31: intel-iommu: Fix one last ia64 build problem in Pass Through Support VT-d: support the device IOTLB VT-d: cleanup iommu_flush_iotlb_psi and flush_unmaps VT-d: add device IOTLB invalidation support VT-d: parse ATSR in DMA Remapping Reporting Structure PCI: handle Virtual Function ATS enabling PCI: support the ATS capability intel-iommu: dmar_set_interrupt return error value intel-iommu: Tidy up iommu->gcmd handling intel-iommu: Fix tiny theoretical race in write-buffer flush. intel-iommu: Clean up handling of "caching mode" vs. IOTLB flushing. intel-iommu: Clean up handling of "caching mode" vs. context flushing. VT-d: fix invalid domain id for KVM context flush Fix !CONFIG_DMAR build failure introduced by Intel IOMMU Pass Through Support Intel IOMMU Pass Through Support Fix up trivial conflicts in drivers/pci/{intel-iommu.c,intr_remapping.c}
Diffstat (limited to 'include/linux/pci_regs.h')
-rw-r--r--include/linux/pci_regs.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index 83b02f5a25b2..fcaee42c7ac2 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -502,6 +502,7 @@
502#define PCI_EXT_CAP_ID_DSN 3 502#define PCI_EXT_CAP_ID_DSN 3
503#define PCI_EXT_CAP_ID_PWR 4 503#define PCI_EXT_CAP_ID_PWR 4
504#define PCI_EXT_CAP_ID_ARI 14 504#define PCI_EXT_CAP_ID_ARI 14
505#define PCI_EXT_CAP_ID_ATS 15
505#define PCI_EXT_CAP_ID_SRIOV 16 506#define PCI_EXT_CAP_ID_SRIOV 16
506 507
507/* Advanced Error Reporting */ 508/* Advanced Error Reporting */
@@ -620,6 +621,15 @@
620#define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */ 621#define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */
621#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */ 622#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */
622 623
624/* Address Translation Service */
625#define PCI_ATS_CAP 0x04 /* ATS Capability Register */
626#define PCI_ATS_CAP_QDEP(x) ((x) & 0x1f) /* Invalidate Queue Depth */
627#define PCI_ATS_MAX_QDEP 32 /* Max Invalidate Queue Depth */
628#define PCI_ATS_CTRL 0x06 /* ATS Control Register */
629#define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */
630#define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) /* Smallest Translation Unit */
631#define PCI_ATS_MIN_STU 12 /* shift of minimum STU block */
632
623/* Single Root I/O Virtualization */ 633/* Single Root I/O Virtualization */
624#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ 634#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
625#define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */ 635#define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */