diff options
| author | Linus Walleij <linus.walleij@stericsson.com> | 2010-11-29 07:52:27 -0500 |
|---|---|---|
| committer | David Woodhouse <David.Woodhouse@intel.com> | 2010-12-03 11:35:40 -0500 |
| commit | b5602e86432aaf0cc90dd207bf74e3a2bfb5078b (patch) | |
| tree | d6c1a8c931bf299a1eaf57ebbe59af6c690e1c5a /include/linux/mtd | |
| parent | 593cd8711221c9661dbf9beb2fb42fecca03e693 (diff) | |
mtd: FSMC NAND fix obvious speling errors
Fix spelling in the interface file.
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'include/linux/mtd')
| -rw-r--r-- | include/linux/mtd/fsmc.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/include/linux/mtd/fsmc.h b/include/linux/mtd/fsmc.h index 96e8e67a053e..6987995ad3cf 100644 --- a/include/linux/mtd/fsmc.h +++ b/include/linux/mtd/fsmc.h | |||
| @@ -28,7 +28,7 @@ | |||
| 28 | 28 | ||
| 29 | /* | 29 | /* |
| 30 | * The placement of the Command Latch Enable (CLE) and | 30 | * The placement of the Command Latch Enable (CLE) and |
| 31 | * Address Latch Enable (ALE) is twised around in the | 31 | * Address Latch Enable (ALE) is twisted around in the |
| 32 | * SPEAR310 implementation. | 32 | * SPEAR310 implementation. |
| 33 | */ | 33 | */ |
| 34 | #if defined(CONFIG_MACH_SPEAR310) | 34 | #if defined(CONFIG_MACH_SPEAR310) |
| @@ -63,7 +63,7 @@ struct fsmc_nor_bank_regs { | |||
| 63 | 63 | ||
| 64 | /* ctrl_tim register definitions */ | 64 | /* ctrl_tim register definitions */ |
| 65 | 65 | ||
| 66 | struct fsms_nand_bank_regs { | 66 | struct fsmc_nand_bank_regs { |
| 67 | uint32_t pc; | 67 | uint32_t pc; |
| 68 | uint32_t sts; | 68 | uint32_t sts; |
| 69 | uint32_t comm; | 69 | uint32_t comm; |
| @@ -79,7 +79,7 @@ struct fsms_nand_bank_regs { | |||
| 79 | struct fsmc_regs { | 79 | struct fsmc_regs { |
| 80 | struct fsmc_nor_bank_regs nor_bank_regs[FSMC_MAX_NOR_BANKS]; | 80 | struct fsmc_nor_bank_regs nor_bank_regs[FSMC_MAX_NOR_BANKS]; |
| 81 | uint8_t reserved_1[0x40 - 0x20]; | 81 | uint8_t reserved_1[0x40 - 0x20]; |
| 82 | struct fsms_nand_bank_regs bank_regs[FSMC_MAX_NAND_BANKS]; | 82 | struct fsmc_nand_bank_regs bank_regs[FSMC_MAX_NAND_BANKS]; |
| 83 | uint8_t reserved_2[0xfe0 - 0xc0]; | 83 | uint8_t reserved_2[0xfe0 - 0xc0]; |
| 84 | uint32_t peripid0; /* 0xfe0 */ | 84 | uint32_t peripid0; /* 0xfe0 */ |
| 85 | uint32_t peripid1; /* 0xfe4 */ | 85 | uint32_t peripid1; /* 0xfe4 */ |
