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authorBastian Hecht <hechtb@googlemail.com>2012-10-19 06:15:35 -0400
committerArtem Bityutskiy <artem.bityutskiy@linux.intel.com>2012-11-15 08:37:50 -0500
commit83738d87e3a0a4096e1419a65b8228130d183df6 (patch)
treec0a837ba214d479f4f1fa26476aef11d7da58751 /include/linux/mtd
parente8a9d8f31c592eea89f1b0d3fd425e7a96944e88 (diff)
mtd: sh_flctl: Add DMA capabilty
The code probes if DMA channels can get allocated and tears them down at removal/failure if needed. If available it uses them to transfer the data part (not ECC). On failure we fall back to PIO mode. Based on Guennadi Liakhovetski's code from the sh_mmcif driver. Signed-off-by: Bastian Hecht <hechtb@gmail.com> Reviewed-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Diffstat (limited to 'include/linux/mtd')
-rw-r--r--include/linux/mtd/sh_flctl.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/include/linux/mtd/sh_flctl.h b/include/linux/mtd/sh_flctl.h
index 481557688d05..1c28f8879b1c 100644
--- a/include/linux/mtd/sh_flctl.h
+++ b/include/linux/mtd/sh_flctl.h
@@ -20,6 +20,7 @@
20#ifndef __SH_FLCTL_H__ 20#ifndef __SH_FLCTL_H__
21#define __SH_FLCTL_H__ 21#define __SH_FLCTL_H__
22 22
23#include <linux/completion.h>
23#include <linux/mtd/mtd.h> 24#include <linux/mtd/mtd.h>
24#include <linux/mtd/nand.h> 25#include <linux/mtd/nand.h>
25#include <linux/mtd/partitions.h> 26#include <linux/mtd/partitions.h>
@@ -107,6 +108,7 @@
107#define ESTERINTE (0x1 << 24) /* ECC error interrupt enable */ 108#define ESTERINTE (0x1 << 24) /* ECC error interrupt enable */
108#define AC1CLR (0x1 << 19) /* ECC FIFO clear */ 109#define AC1CLR (0x1 << 19) /* ECC FIFO clear */
109#define AC0CLR (0x1 << 18) /* Data FIFO clear */ 110#define AC0CLR (0x1 << 18) /* Data FIFO clear */
111#define DREQ0EN (0x1 << 16) /* FLDTFIFODMA Request Enable */
110#define ECERB (0x1 << 9) /* ECC error */ 112#define ECERB (0x1 << 9) /* ECC error */
111#define STERB (0x1 << 8) /* Status error */ 113#define STERB (0x1 << 8) /* Status error */
112#define STERINTE (0x1 << 4) /* Status error enable */ 114#define STERINTE (0x1 << 4) /* Status error enable */
@@ -138,6 +140,8 @@ enum flctl_ecc_res_t {
138 FL_TIMEOUT 140 FL_TIMEOUT
139}; 141};
140 142
143struct dma_chan;
144
141struct sh_flctl { 145struct sh_flctl {
142 struct mtd_info mtd; 146 struct mtd_info mtd;
143 struct nand_chip chip; 147 struct nand_chip chip;
@@ -161,6 +165,11 @@ struct sh_flctl {
161 unsigned hwecc:1; /* Hardware ECC (0 = disabled, 1 = enabled) */ 165 unsigned hwecc:1; /* Hardware ECC (0 = disabled, 1 = enabled) */
162 unsigned holden:1; /* Hardware has FLHOLDCR and HOLDEN is set */ 166 unsigned holden:1; /* Hardware has FLHOLDCR and HOLDEN is set */
163 unsigned qos_request:1; /* QoS request to prevent deep power shutdown */ 167 unsigned qos_request:1; /* QoS request to prevent deep power shutdown */
168
169 /* DMA related objects */
170 struct dma_chan *chan_fifo0_rx;
171 struct dma_chan *chan_fifo0_tx;
172 struct completion dma_complete;
164}; 173};
165 174
166struct sh_flctl_platform_data { 175struct sh_flctl_platform_data {
@@ -170,6 +179,9 @@ struct sh_flctl_platform_data {
170 179
171 unsigned has_hwecc:1; 180 unsigned has_hwecc:1;
172 unsigned use_holden:1; 181 unsigned use_holden:1;
182
183 unsigned int slave_id_fifo0_tx;
184 unsigned int slave_id_fifo0_rx;
173}; 185};
174 186
175static inline struct sh_flctl *mtd_to_flctl(struct mtd_info *mtdinfo) 187static inline struct sh_flctl *mtd_to_flctl(struct mtd_info *mtdinfo)