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authorHuang Shijie <b32955@freescale.com>2013-09-25 02:58:11 -0400
committerBrian Norris <computersforpeace@gmail.com>2013-10-27 19:27:04 -0400
commit7db906b79f69b6ed936a1ef1d788f02e3ad42462 (patch)
treea5ff4e764cc159db07358a90781b48a976ca5e22 /include/linux/mtd
parent1d0ed69ddd714b6e2a974f42896463366923ded6 (diff)
mtd: nand: rename the cellinfo to bits_per_cell
The @cellinfo fields contains unused information, such as write caching, internal chip numbering, etc. But we only use it to check the SLC or MLC. This patch tries to make it more clear and simple, renames the @cellinfo to @bits_per_cell. In order to avoiding the bisect issue, this patch also does the following changes: (0) add a macro NAND_CI_CELLTYPE_SHIFT to avoid the hardcode. (1) add a helper to parse out the cell type : nand_get_bits_per_cell() (2) parse out the cell type for extended-ID chips and the full-id nand chips. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Diffstat (limited to 'include/linux/mtd')
-rw-r--r--include/linux/mtd/nand.h7
1 files changed, 4 insertions, 3 deletions
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 5c05bab0ad89..9e6c8f9f306e 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -198,6 +198,7 @@ typedef enum {
198/* Cell info constants */ 198/* Cell info constants */
199#define NAND_CI_CHIPNR_MSK 0x03 199#define NAND_CI_CHIPNR_MSK 0x03
200#define NAND_CI_CELLTYPE_MSK 0x0C 200#define NAND_CI_CELLTYPE_MSK 0x0C
201#define NAND_CI_CELLTYPE_SHIFT 2
201 202
202/* Keep gcc happy */ 203/* Keep gcc happy */
203struct nand_chip; 204struct nand_chip;
@@ -477,7 +478,7 @@ struct nand_buffers {
477 * @badblockbits: [INTERN] minimum number of set bits in a good block's 478 * @badblockbits: [INTERN] minimum number of set bits in a good block's
478 * bad block marker position; i.e., BBM == 11110111b is 479 * bad block marker position; i.e., BBM == 11110111b is
479 * not bad when badblockbits == 7 480 * not bad when badblockbits == 7
480 * @cellinfo: [INTERN] MLC/multichip data from chip ident 481 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.
481 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet. 482 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
482 * Minimum amount of bit errors per @ecc_step_ds guaranteed 483 * Minimum amount of bit errors per @ecc_step_ds guaranteed
483 * to be correctable. If unknown, set to zero. 484 * to be correctable. If unknown, set to zero.
@@ -558,7 +559,7 @@ struct nand_chip {
558 int pagebuf; 559 int pagebuf;
559 unsigned int pagebuf_bitflips; 560 unsigned int pagebuf_bitflips;
560 int subpagesize; 561 int subpagesize;
561 uint8_t cellinfo; 562 uint8_t bits_per_cell;
562 uint16_t ecc_strength_ds; 563 uint16_t ecc_strength_ds;
563 uint16_t ecc_step_ds; 564 uint16_t ecc_step_ds;
564 int badblockpos; 565 int badblockpos;
@@ -802,6 +803,6 @@ static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
802 */ 803 */
803static inline bool nand_is_slc(struct nand_chip *chip) 804static inline bool nand_is_slc(struct nand_chip *chip)
804{ 805{
805 return !(chip->cellinfo & NAND_CI_CELLTYPE_MSK); 806 return chip->bits_per_cell == 1;
806} 807}
807#endif /* __LINUX_MTD_NAND_H */ 808#endif /* __LINUX_MTD_NAND_H */