diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2012-03-30 20:31:56 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2012-03-30 20:31:56 -0400 |
commit | 623ff7739e7c00fa3d55dbfd42a492a68298fd7a (patch) | |
tree | 0b7461753a1b13b27ea2958a7d48c6efb47bba54 /include/linux/mtd | |
parent | c39e8ede284f469971589f2e04af78216e1a771d (diff) | |
parent | 7b0e67f604e1829e5292e1ad7743eb18dc42ea7c (diff) |
Merge tag 'for-linus-3.4' of git://git.infradead.org/mtd-2.6
Pull MTD changes from David Woodhouse:
- Artem's cleanup of the MTD API continues apace.
- Fixes and improvements for ST FSMC and SuperH FLCTL NAND, amongst
others.
- More work on DiskOnChip G3, new driver for DiskOnChip G4.
- Clean up debug/warning printks in JFFS2 to use pr_<level>.
Fix up various trivial conflicts, largely due to changes in calling
conventions for things like dmaengine_prep_slave_sg() (new inline
wrapper to hide new parameter, clashing with rewrite of previously last
parameter that used to be an 'append' flag, and is now a bitmap of
'unsigned long flags').
(Also some header file fallout - like so many merges this merge window -
and silly conflicts with sparse fixes)
* tag 'for-linus-3.4' of git://git.infradead.org/mtd-2.6: (120 commits)
mtd: docg3 add protection against concurrency
mtd: docg3 refactor cascade floors structure
mtd: docg3 increase write/erase timeout
mtd: docg3 fix inbound calculations
mtd: nand: gpmi: fix function annotations
mtd: phram: fix section mismatch for phram_setup
mtd: unify initialization of erase_info->fail_addr
mtd: support ONFI multi lun NAND
mtd: sm_ftl: fix typo in major number.
mtd: add device-tree support to spear_smi
mtd: spear_smi: Remove default partition information from driver
mtd: Add device-tree support to fsmc_nand
mtd: fix section mismatch for doc_probe_device
mtd: nand/fsmc: Remove sparse warnings and errors
mtd: nand/fsmc: Add DMA support
mtd: nand/fsmc: Access the NAND device word by word whenever possible
mtd: nand/fsmc: Use dev_err to report error scenario
mtd: nand/fsmc: Use devm routines
mtd: nand/fsmc: Modify fsmc driver to accept nand timing parameters via platform
mtd: fsmc_nand: add pm callbacks to support hibernation
...
Diffstat (limited to 'include/linux/mtd')
-rw-r--r-- | include/linux/mtd/bbm.h | 5 | ||||
-rw-r--r-- | include/linux/mtd/blktrans.h | 1 | ||||
-rw-r--r-- | include/linux/mtd/fsmc.h | 169 | ||||
-rw-r--r-- | include/linux/mtd/mtd.h | 304 | ||||
-rw-r--r-- | include/linux/mtd/nand.h | 7 | ||||
-rw-r--r-- | include/linux/mtd/pmc551.h | 78 | ||||
-rw-r--r-- | include/linux/mtd/sh_flctl.h | 40 | ||||
-rw-r--r-- | include/linux/mtd/spear_smi.h | 65 |
8 files changed, 291 insertions, 378 deletions
diff --git a/include/linux/mtd/bbm.h b/include/linux/mtd/bbm.h index c4eec228eef9..650ef352f045 100644 --- a/include/linux/mtd/bbm.h +++ b/include/linux/mtd/bbm.h | |||
@@ -112,6 +112,11 @@ struct nand_bbt_descr { | |||
112 | #define NAND_BBT_USE_FLASH 0x00020000 | 112 | #define NAND_BBT_USE_FLASH 0x00020000 |
113 | /* Do not store flash based bad block table in OOB area; store it in-band */ | 113 | /* Do not store flash based bad block table in OOB area; store it in-band */ |
114 | #define NAND_BBT_NO_OOB 0x00040000 | 114 | #define NAND_BBT_NO_OOB 0x00040000 |
115 | /* | ||
116 | * Do not write new bad block markers to OOB; useful, e.g., when ECC covers | ||
117 | * entire spare area. Must be used with NAND_BBT_USE_FLASH. | ||
118 | */ | ||
119 | #define NAND_BBT_NO_OOB_BBM 0x00080000 | ||
115 | 120 | ||
116 | /* | 121 | /* |
117 | * Flag set by nand_create_default_bbt_descr(), marking that the nand_bbt_descr | 122 | * Flag set by nand_create_default_bbt_descr(), marking that the nand_bbt_descr |
diff --git a/include/linux/mtd/blktrans.h b/include/linux/mtd/blktrans.h index 1bbd9f289245..ed270bd2e4df 100644 --- a/include/linux/mtd/blktrans.h +++ b/include/linux/mtd/blktrans.h | |||
@@ -47,6 +47,7 @@ struct mtd_blktrans_dev { | |||
47 | struct request_queue *rq; | 47 | struct request_queue *rq; |
48 | spinlock_t queue_lock; | 48 | spinlock_t queue_lock; |
49 | void *priv; | 49 | void *priv; |
50 | fmode_t file_mode; | ||
50 | }; | 51 | }; |
51 | 52 | ||
52 | struct mtd_blktrans_ops { | 53 | struct mtd_blktrans_ops { |
diff --git a/include/linux/mtd/fsmc.h b/include/linux/mtd/fsmc.h index 6987995ad3cf..b20029221fb1 100644 --- a/include/linux/mtd/fsmc.h +++ b/include/linux/mtd/fsmc.h | |||
@@ -26,95 +26,83 @@ | |||
26 | #define FSMC_NAND_BW8 1 | 26 | #define FSMC_NAND_BW8 1 |
27 | #define FSMC_NAND_BW16 2 | 27 | #define FSMC_NAND_BW16 2 |
28 | 28 | ||
29 | /* | ||
30 | * The placement of the Command Latch Enable (CLE) and | ||
31 | * Address Latch Enable (ALE) is twisted around in the | ||
32 | * SPEAR310 implementation. | ||
33 | */ | ||
34 | #if defined(CONFIG_MACH_SPEAR310) | ||
35 | #define PLAT_NAND_CLE (1 << 17) | ||
36 | #define PLAT_NAND_ALE (1 << 16) | ||
37 | #else | ||
38 | #define PLAT_NAND_CLE (1 << 16) | ||
39 | #define PLAT_NAND_ALE (1 << 17) | ||
40 | #endif | ||
41 | |||
42 | #define FSMC_MAX_NOR_BANKS 4 | 29 | #define FSMC_MAX_NOR_BANKS 4 |
43 | #define FSMC_MAX_NAND_BANKS 4 | 30 | #define FSMC_MAX_NAND_BANKS 4 |
44 | 31 | ||
45 | #define FSMC_FLASH_WIDTH8 1 | 32 | #define FSMC_FLASH_WIDTH8 1 |
46 | #define FSMC_FLASH_WIDTH16 2 | 33 | #define FSMC_FLASH_WIDTH16 2 |
47 | 34 | ||
48 | struct fsmc_nor_bank_regs { | 35 | /* fsmc controller registers for NOR flash */ |
49 | uint32_t ctrl; | 36 | #define CTRL 0x0 |
50 | uint32_t ctrl_tim; | 37 | /* ctrl register definitions */ |
51 | }; | 38 | #define BANK_ENABLE (1 << 0) |
52 | 39 | #define MUXED (1 << 1) | |
53 | /* ctrl register definitions */ | 40 | #define NOR_DEV (2 << 2) |
54 | #define BANK_ENABLE (1 << 0) | 41 | #define WIDTH_8 (0 << 4) |
55 | #define MUXED (1 << 1) | 42 | #define WIDTH_16 (1 << 4) |
56 | #define NOR_DEV (2 << 2) | 43 | #define RSTPWRDWN (1 << 6) |
57 | #define WIDTH_8 (0 << 4) | 44 | #define WPROT (1 << 7) |
58 | #define WIDTH_16 (1 << 4) | 45 | #define WRT_ENABLE (1 << 12) |
59 | #define RSTPWRDWN (1 << 6) | 46 | #define WAIT_ENB (1 << 13) |
60 | #define WPROT (1 << 7) | 47 | |
61 | #define WRT_ENABLE (1 << 12) | 48 | #define CTRL_TIM 0x4 |
62 | #define WAIT_ENB (1 << 13) | 49 | /* ctrl_tim register definitions */ |
63 | 50 | ||
64 | /* ctrl_tim register definitions */ | 51 | #define FSMC_NOR_BANK_SZ 0x8 |
65 | |||
66 | struct fsmc_nand_bank_regs { | ||
67 | uint32_t pc; | ||
68 | uint32_t sts; | ||
69 | uint32_t comm; | ||
70 | uint32_t attrib; | ||
71 | uint32_t ioata; | ||
72 | uint32_t ecc1; | ||
73 | uint32_t ecc2; | ||
74 | uint32_t ecc3; | ||
75 | }; | ||
76 | |||
77 | #define FSMC_NOR_REG_SIZE 0x40 | 52 | #define FSMC_NOR_REG_SIZE 0x40 |
78 | 53 | ||
79 | struct fsmc_regs { | 54 | #define FSMC_NOR_REG(base, bank, reg) (base + \ |
80 | struct fsmc_nor_bank_regs nor_bank_regs[FSMC_MAX_NOR_BANKS]; | 55 | FSMC_NOR_BANK_SZ * (bank) + \ |
81 | uint8_t reserved_1[0x40 - 0x20]; | 56 | reg) |
82 | struct fsmc_nand_bank_regs bank_regs[FSMC_MAX_NAND_BANKS]; | 57 | |
83 | uint8_t reserved_2[0xfe0 - 0xc0]; | 58 | /* fsmc controller registers for NAND flash */ |
84 | uint32_t peripid0; /* 0xfe0 */ | 59 | #define PC 0x00 |
85 | uint32_t peripid1; /* 0xfe4 */ | 60 | /* pc register definitions */ |
86 | uint32_t peripid2; /* 0xfe8 */ | 61 | #define FSMC_RESET (1 << 0) |
87 | uint32_t peripid3; /* 0xfec */ | 62 | #define FSMC_WAITON (1 << 1) |
88 | uint32_t pcellid0; /* 0xff0 */ | 63 | #define FSMC_ENABLE (1 << 2) |
89 | uint32_t pcellid1; /* 0xff4 */ | 64 | #define FSMC_DEVTYPE_NAND (1 << 3) |
90 | uint32_t pcellid2; /* 0xff8 */ | 65 | #define FSMC_DEVWID_8 (0 << 4) |
91 | uint32_t pcellid3; /* 0xffc */ | 66 | #define FSMC_DEVWID_16 (1 << 4) |
92 | }; | 67 | #define FSMC_ECCEN (1 << 6) |
68 | #define FSMC_ECCPLEN_512 (0 << 7) | ||
69 | #define FSMC_ECCPLEN_256 (1 << 7) | ||
70 | #define FSMC_TCLR_1 (1) | ||
71 | #define FSMC_TCLR_SHIFT (9) | ||
72 | #define FSMC_TCLR_MASK (0xF) | ||
73 | #define FSMC_TAR_1 (1) | ||
74 | #define FSMC_TAR_SHIFT (13) | ||
75 | #define FSMC_TAR_MASK (0xF) | ||
76 | #define STS 0x04 | ||
77 | /* sts register definitions */ | ||
78 | #define FSMC_CODE_RDY (1 << 15) | ||
79 | #define COMM 0x08 | ||
80 | /* comm register definitions */ | ||
81 | #define FSMC_TSET_0 0 | ||
82 | #define FSMC_TSET_SHIFT 0 | ||
83 | #define FSMC_TSET_MASK 0xFF | ||
84 | #define FSMC_TWAIT_6 6 | ||
85 | #define FSMC_TWAIT_SHIFT 8 | ||
86 | #define FSMC_TWAIT_MASK 0xFF | ||
87 | #define FSMC_THOLD_4 4 | ||
88 | #define FSMC_THOLD_SHIFT 16 | ||
89 | #define FSMC_THOLD_MASK 0xFF | ||
90 | #define FSMC_THIZ_1 1 | ||
91 | #define FSMC_THIZ_SHIFT 24 | ||
92 | #define FSMC_THIZ_MASK 0xFF | ||
93 | #define ATTRIB 0x0C | ||
94 | #define IOATA 0x10 | ||
95 | #define ECC1 0x14 | ||
96 | #define ECC2 0x18 | ||
97 | #define ECC3 0x1C | ||
98 | #define FSMC_NAND_BANK_SZ 0x20 | ||
99 | |||
100 | #define FSMC_NAND_REG(base, bank, reg) (base + FSMC_NOR_REG_SIZE + \ | ||
101 | (FSMC_NAND_BANK_SZ * (bank)) + \ | ||
102 | reg) | ||
93 | 103 | ||
94 | #define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ) | 104 | #define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ) |
95 | 105 | ||
96 | /* pc register definitions */ | ||
97 | #define FSMC_RESET (1 << 0) | ||
98 | #define FSMC_WAITON (1 << 1) | ||
99 | #define FSMC_ENABLE (1 << 2) | ||
100 | #define FSMC_DEVTYPE_NAND (1 << 3) | ||
101 | #define FSMC_DEVWID_8 (0 << 4) | ||
102 | #define FSMC_DEVWID_16 (1 << 4) | ||
103 | #define FSMC_ECCEN (1 << 6) | ||
104 | #define FSMC_ECCPLEN_512 (0 << 7) | ||
105 | #define FSMC_ECCPLEN_256 (1 << 7) | ||
106 | #define FSMC_TCLR_1 (1 << 9) | ||
107 | #define FSMC_TAR_1 (1 << 13) | ||
108 | |||
109 | /* sts register definitions */ | ||
110 | #define FSMC_CODE_RDY (1 << 15) | ||
111 | |||
112 | /* comm register definitions */ | ||
113 | #define FSMC_TSET_0 (0 << 0) | ||
114 | #define FSMC_TWAIT_6 (6 << 8) | ||
115 | #define FSMC_THOLD_4 (4 << 16) | ||
116 | #define FSMC_THIZ_1 (1 << 24) | ||
117 | |||
118 | /* | 106 | /* |
119 | * There are 13 bytes of ecc for every 512 byte block in FSMC version 8 | 107 | * There are 13 bytes of ecc for every 512 byte block in FSMC version 8 |
120 | * and it has to be read consecutively and immediately after the 512 | 108 | * and it has to be read consecutively and immediately after the 512 |
@@ -133,6 +121,20 @@ struct fsmc_eccplace { | |||
133 | struct fsmc_nand_eccplace eccplace[MAX_ECCPLACE_ENTRIES]; | 121 | struct fsmc_nand_eccplace eccplace[MAX_ECCPLACE_ENTRIES]; |
134 | }; | 122 | }; |
135 | 123 | ||
124 | struct fsmc_nand_timings { | ||
125 | uint8_t tclr; | ||
126 | uint8_t tar; | ||
127 | uint8_t thiz; | ||
128 | uint8_t thold; | ||
129 | uint8_t twait; | ||
130 | uint8_t tset; | ||
131 | }; | ||
132 | |||
133 | enum access_mode { | ||
134 | USE_DMA_ACCESS = 1, | ||
135 | USE_WORD_ACCESS, | ||
136 | }; | ||
137 | |||
136 | /** | 138 | /** |
137 | * fsmc_nand_platform_data - platform specific NAND controller config | 139 | * fsmc_nand_platform_data - platform specific NAND controller config |
138 | * @partitions: partition table for the platform, use a default fallback | 140 | * @partitions: partition table for the platform, use a default fallback |
@@ -146,12 +148,23 @@ struct fsmc_eccplace { | |||
146 | * this may be set to NULL | 148 | * this may be set to NULL |
147 | */ | 149 | */ |
148 | struct fsmc_nand_platform_data { | 150 | struct fsmc_nand_platform_data { |
151 | struct fsmc_nand_timings *nand_timings; | ||
149 | struct mtd_partition *partitions; | 152 | struct mtd_partition *partitions; |
150 | unsigned int nr_partitions; | 153 | unsigned int nr_partitions; |
151 | unsigned int options; | 154 | unsigned int options; |
152 | unsigned int width; | 155 | unsigned int width; |
153 | unsigned int bank; | 156 | unsigned int bank; |
157 | |||
158 | /* CLE, ALE offsets */ | ||
159 | unsigned int cle_off; | ||
160 | unsigned int ale_off; | ||
161 | enum access_mode mode; | ||
162 | |||
154 | void (*select_bank)(uint32_t bank, uint32_t busw); | 163 | void (*select_bank)(uint32_t bank, uint32_t busw); |
164 | |||
165 | /* priv structures for dma accesses */ | ||
166 | void *read_dma_priv; | ||
167 | void *write_dma_priv; | ||
155 | }; | 168 | }; |
156 | 169 | ||
157 | extern int __init fsmc_nor_init(struct platform_device *pdev, | 170 | extern int __init fsmc_nor_init(struct platform_device *pdev, |
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index d43dc25af82e..cf5ea8cdcf8e 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h | |||
@@ -164,6 +164,9 @@ struct mtd_info { | |||
164 | /* ECC layout structure pointer - read only! */ | 164 | /* ECC layout structure pointer - read only! */ |
165 | struct nand_ecclayout *ecclayout; | 165 | struct nand_ecclayout *ecclayout; |
166 | 166 | ||
167 | /* max number of correctible bit errors per writesize */ | ||
168 | unsigned int ecc_strength; | ||
169 | |||
167 | /* Data for variable erase regions. If numeraseregions is zero, | 170 | /* Data for variable erase regions. If numeraseregions is zero, |
168 | * it means that the whole device has erasesize as given above. | 171 | * it means that the whole device has erasesize as given above. |
169 | */ | 172 | */ |
@@ -174,52 +177,52 @@ struct mtd_info { | |||
174 | * Do not call via these pointers, use corresponding mtd_*() | 177 | * Do not call via these pointers, use corresponding mtd_*() |
175 | * wrappers instead. | 178 | * wrappers instead. |
176 | */ | 179 | */ |
177 | int (*erase) (struct mtd_info *mtd, struct erase_info *instr); | 180 | int (*_erase) (struct mtd_info *mtd, struct erase_info *instr); |
178 | int (*point) (struct mtd_info *mtd, loff_t from, size_t len, | 181 | int (*_point) (struct mtd_info *mtd, loff_t from, size_t len, |
179 | size_t *retlen, void **virt, resource_size_t *phys); | 182 | size_t *retlen, void **virt, resource_size_t *phys); |
180 | void (*unpoint) (struct mtd_info *mtd, loff_t from, size_t len); | 183 | int (*_unpoint) (struct mtd_info *mtd, loff_t from, size_t len); |
181 | unsigned long (*get_unmapped_area) (struct mtd_info *mtd, | 184 | unsigned long (*_get_unmapped_area) (struct mtd_info *mtd, |
182 | unsigned long len, | 185 | unsigned long len, |
183 | unsigned long offset, | 186 | unsigned long offset, |
184 | unsigned long flags); | 187 | unsigned long flags); |
185 | int (*read) (struct mtd_info *mtd, loff_t from, size_t len, | 188 | int (*_read) (struct mtd_info *mtd, loff_t from, size_t len, |
186 | size_t *retlen, u_char *buf); | 189 | size_t *retlen, u_char *buf); |
187 | int (*write) (struct mtd_info *mtd, loff_t to, size_t len, | 190 | int (*_write) (struct mtd_info *mtd, loff_t to, size_t len, |
188 | size_t *retlen, const u_char *buf); | 191 | size_t *retlen, const u_char *buf); |
189 | int (*panic_write) (struct mtd_info *mtd, loff_t to, size_t len, | 192 | int (*_panic_write) (struct mtd_info *mtd, loff_t to, size_t len, |
190 | size_t *retlen, const u_char *buf); | 193 | size_t *retlen, const u_char *buf); |
191 | int (*read_oob) (struct mtd_info *mtd, loff_t from, | 194 | int (*_read_oob) (struct mtd_info *mtd, loff_t from, |
192 | struct mtd_oob_ops *ops); | ||
193 | int (*write_oob) (struct mtd_info *mtd, loff_t to, | ||
194 | struct mtd_oob_ops *ops); | 195 | struct mtd_oob_ops *ops); |
195 | int (*get_fact_prot_info) (struct mtd_info *mtd, struct otp_info *buf, | 196 | int (*_write_oob) (struct mtd_info *mtd, loff_t to, |
196 | size_t len); | 197 | struct mtd_oob_ops *ops); |
197 | int (*read_fact_prot_reg) (struct mtd_info *mtd, loff_t from, | 198 | int (*_get_fact_prot_info) (struct mtd_info *mtd, struct otp_info *buf, |
198 | size_t len, size_t *retlen, u_char *buf); | 199 | size_t len); |
199 | int (*get_user_prot_info) (struct mtd_info *mtd, struct otp_info *buf, | 200 | int (*_read_fact_prot_reg) (struct mtd_info *mtd, loff_t from, |
200 | size_t len); | 201 | size_t len, size_t *retlen, u_char *buf); |
201 | int (*read_user_prot_reg) (struct mtd_info *mtd, loff_t from, | 202 | int (*_get_user_prot_info) (struct mtd_info *mtd, struct otp_info *buf, |
202 | size_t len, size_t *retlen, u_char *buf); | 203 | size_t len); |
203 | int (*write_user_prot_reg) (struct mtd_info *mtd, loff_t to, size_t len, | 204 | int (*_read_user_prot_reg) (struct mtd_info *mtd, loff_t from, |
204 | size_t *retlen, u_char *buf); | 205 | size_t len, size_t *retlen, u_char *buf); |
205 | int (*lock_user_prot_reg) (struct mtd_info *mtd, loff_t from, | 206 | int (*_write_user_prot_reg) (struct mtd_info *mtd, loff_t to, |
206 | size_t len); | 207 | size_t len, size_t *retlen, u_char *buf); |
207 | int (*writev) (struct mtd_info *mtd, const struct kvec *vecs, | 208 | int (*_lock_user_prot_reg) (struct mtd_info *mtd, loff_t from, |
209 | size_t len); | ||
210 | int (*_writev) (struct mtd_info *mtd, const struct kvec *vecs, | ||
208 | unsigned long count, loff_t to, size_t *retlen); | 211 | unsigned long count, loff_t to, size_t *retlen); |
209 | void (*sync) (struct mtd_info *mtd); | 212 | void (*_sync) (struct mtd_info *mtd); |
210 | int (*lock) (struct mtd_info *mtd, loff_t ofs, uint64_t len); | 213 | int (*_lock) (struct mtd_info *mtd, loff_t ofs, uint64_t len); |
211 | int (*unlock) (struct mtd_info *mtd, loff_t ofs, uint64_t len); | 214 | int (*_unlock) (struct mtd_info *mtd, loff_t ofs, uint64_t len); |
212 | int (*is_locked) (struct mtd_info *mtd, loff_t ofs, uint64_t len); | 215 | int (*_is_locked) (struct mtd_info *mtd, loff_t ofs, uint64_t len); |
213 | int (*block_isbad) (struct mtd_info *mtd, loff_t ofs); | 216 | int (*_block_isbad) (struct mtd_info *mtd, loff_t ofs); |
214 | int (*block_markbad) (struct mtd_info *mtd, loff_t ofs); | 217 | int (*_block_markbad) (struct mtd_info *mtd, loff_t ofs); |
215 | int (*suspend) (struct mtd_info *mtd); | 218 | int (*_suspend) (struct mtd_info *mtd); |
216 | void (*resume) (struct mtd_info *mtd); | 219 | void (*_resume) (struct mtd_info *mtd); |
217 | /* | 220 | /* |
218 | * If the driver is something smart, like UBI, it may need to maintain | 221 | * If the driver is something smart, like UBI, it may need to maintain |
219 | * its own reference counting. The below functions are only for driver. | 222 | * its own reference counting. The below functions are only for driver. |
220 | */ | 223 | */ |
221 | int (*get_device) (struct mtd_info *mtd); | 224 | int (*_get_device) (struct mtd_info *mtd); |
222 | void (*put_device) (struct mtd_info *mtd); | 225 | void (*_put_device) (struct mtd_info *mtd); |
223 | 226 | ||
224 | /* Backing device capabilities for this device | 227 | /* Backing device capabilities for this device |
225 | * - provides mmap capabilities | 228 | * - provides mmap capabilities |
@@ -240,214 +243,75 @@ struct mtd_info { | |||
240 | int usecount; | 243 | int usecount; |
241 | }; | 244 | }; |
242 | 245 | ||
243 | /* | 246 | int mtd_erase(struct mtd_info *mtd, struct erase_info *instr); |
244 | * Erase is an asynchronous operation. Device drivers are supposed | 247 | int mtd_point(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, |
245 | * to call instr->callback() whenever the operation completes, even | 248 | void **virt, resource_size_t *phys); |
246 | * if it completes with a failure. | 249 | int mtd_unpoint(struct mtd_info *mtd, loff_t from, size_t len); |
247 | * Callers are supposed to pass a callback function and wait for it | 250 | unsigned long mtd_get_unmapped_area(struct mtd_info *mtd, unsigned long len, |
248 | * to be called before writing to the block. | 251 | unsigned long offset, unsigned long flags); |
249 | */ | 252 | int mtd_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, |
250 | static inline int mtd_erase(struct mtd_info *mtd, struct erase_info *instr) | 253 | u_char *buf); |
251 | { | 254 | int mtd_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, |
252 | return mtd->erase(mtd, instr); | 255 | const u_char *buf); |
253 | } | 256 | int mtd_panic_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, |
254 | 257 | const u_char *buf); | |
255 | /* | ||
256 | * This stuff for eXecute-In-Place. phys is optional and may be set to NULL. | ||
257 | */ | ||
258 | static inline int mtd_point(struct mtd_info *mtd, loff_t from, size_t len, | ||
259 | size_t *retlen, void **virt, resource_size_t *phys) | ||
260 | { | ||
261 | *retlen = 0; | ||
262 | if (!mtd->point) | ||
263 | return -EOPNOTSUPP; | ||
264 | return mtd->point(mtd, from, len, retlen, virt, phys); | ||
265 | } | ||
266 | |||
267 | /* We probably shouldn't allow XIP if the unpoint isn't a NULL */ | ||
268 | static inline void mtd_unpoint(struct mtd_info *mtd, loff_t from, size_t len) | ||
269 | { | ||
270 | return mtd->unpoint(mtd, from, len); | ||
271 | } | ||
272 | |||
273 | /* | ||
274 | * Allow NOMMU mmap() to directly map the device (if not NULL) | ||
275 | * - return the address to which the offset maps | ||
276 | * - return -ENOSYS to indicate refusal to do the mapping | ||
277 | */ | ||
278 | static inline unsigned long mtd_get_unmapped_area(struct mtd_info *mtd, | ||
279 | unsigned long len, | ||
280 | unsigned long offset, | ||
281 | unsigned long flags) | ||
282 | { | ||
283 | if (!mtd->get_unmapped_area) | ||
284 | return -EOPNOTSUPP; | ||
285 | return mtd->get_unmapped_area(mtd, len, offset, flags); | ||
286 | } | ||
287 | |||
288 | static inline int mtd_read(struct mtd_info *mtd, loff_t from, size_t len, | ||
289 | size_t *retlen, u_char *buf) | ||
290 | { | ||
291 | return mtd->read(mtd, from, len, retlen, buf); | ||
292 | } | ||
293 | |||
294 | static inline int mtd_write(struct mtd_info *mtd, loff_t to, size_t len, | ||
295 | size_t *retlen, const u_char *buf) | ||
296 | { | ||
297 | *retlen = 0; | ||
298 | if (!mtd->write) | ||
299 | return -EROFS; | ||
300 | return mtd->write(mtd, to, len, retlen, buf); | ||
301 | } | ||
302 | |||
303 | /* | ||
304 | * In blackbox flight recorder like scenarios we want to make successful writes | ||
305 | * in interrupt context. panic_write() is only intended to be called when its | ||
306 | * known the kernel is about to panic and we need the write to succeed. Since | ||
307 | * the kernel is not going to be running for much longer, this function can | ||
308 | * break locks and delay to ensure the write succeeds (but not sleep). | ||
309 | */ | ||
310 | static inline int mtd_panic_write(struct mtd_info *mtd, loff_t to, size_t len, | ||
311 | size_t *retlen, const u_char *buf) | ||
312 | { | ||
313 | *retlen = 0; | ||
314 | if (!mtd->panic_write) | ||
315 | return -EOPNOTSUPP; | ||
316 | return mtd->panic_write(mtd, to, len, retlen, buf); | ||
317 | } | ||
318 | 258 | ||
319 | static inline int mtd_read_oob(struct mtd_info *mtd, loff_t from, | 259 | static inline int mtd_read_oob(struct mtd_info *mtd, loff_t from, |
320 | struct mtd_oob_ops *ops) | 260 | struct mtd_oob_ops *ops) |
321 | { | 261 | { |
322 | ops->retlen = ops->oobretlen = 0; | 262 | ops->retlen = ops->oobretlen = 0; |
323 | if (!mtd->read_oob) | 263 | if (!mtd->_read_oob) |
324 | return -EOPNOTSUPP; | 264 | return -EOPNOTSUPP; |
325 | return mtd->read_oob(mtd, from, ops); | 265 | return mtd->_read_oob(mtd, from, ops); |
326 | } | 266 | } |
327 | 267 | ||
328 | static inline int mtd_write_oob(struct mtd_info *mtd, loff_t to, | 268 | static inline int mtd_write_oob(struct mtd_info *mtd, loff_t to, |
329 | struct mtd_oob_ops *ops) | 269 | struct mtd_oob_ops *ops) |
330 | { | 270 | { |
331 | ops->retlen = ops->oobretlen = 0; | 271 | ops->retlen = ops->oobretlen = 0; |
332 | if (!mtd->write_oob) | 272 | if (!mtd->_write_oob) |
333 | return -EOPNOTSUPP; | ||
334 | return mtd->write_oob(mtd, to, ops); | ||
335 | } | ||
336 | |||
337 | /* | ||
338 | * Method to access the protection register area, present in some flash | ||
339 | * devices. The user data is one time programmable but the factory data is read | ||
340 | * only. | ||
341 | */ | ||
342 | static inline int mtd_get_fact_prot_info(struct mtd_info *mtd, | ||
343 | struct otp_info *buf, size_t len) | ||
344 | { | ||
345 | if (!mtd->get_fact_prot_info) | ||
346 | return -EOPNOTSUPP; | 273 | return -EOPNOTSUPP; |
347 | return mtd->get_fact_prot_info(mtd, buf, len); | 274 | if (!(mtd->flags & MTD_WRITEABLE)) |
348 | } | 275 | return -EROFS; |
349 | 276 | return mtd->_write_oob(mtd, to, ops); | |
350 | static inline int mtd_read_fact_prot_reg(struct mtd_info *mtd, loff_t from, | ||
351 | size_t len, size_t *retlen, | ||
352 | u_char *buf) | ||
353 | { | ||
354 | *retlen = 0; | ||
355 | if (!mtd->read_fact_prot_reg) | ||
356 | return -EOPNOTSUPP; | ||
357 | return mtd->read_fact_prot_reg(mtd, from, len, retlen, buf); | ||
358 | } | ||
359 | |||
360 | static inline int mtd_get_user_prot_info(struct mtd_info *mtd, | ||
361 | struct otp_info *buf, | ||
362 | size_t len) | ||
363 | { | ||
364 | if (!mtd->get_user_prot_info) | ||
365 | return -EOPNOTSUPP; | ||
366 | return mtd->get_user_prot_info(mtd, buf, len); | ||
367 | } | ||
368 | |||
369 | static inline int mtd_read_user_prot_reg(struct mtd_info *mtd, loff_t from, | ||
370 | size_t len, size_t *retlen, | ||
371 | u_char *buf) | ||
372 | { | ||
373 | *retlen = 0; | ||
374 | if (!mtd->read_user_prot_reg) | ||
375 | return -EOPNOTSUPP; | ||
376 | return mtd->read_user_prot_reg(mtd, from, len, retlen, buf); | ||
377 | } | ||
378 | |||
379 | static inline int mtd_write_user_prot_reg(struct mtd_info *mtd, loff_t to, | ||
380 | size_t len, size_t *retlen, | ||
381 | u_char *buf) | ||
382 | { | ||
383 | *retlen = 0; | ||
384 | if (!mtd->write_user_prot_reg) | ||
385 | return -EOPNOTSUPP; | ||
386 | return mtd->write_user_prot_reg(mtd, to, len, retlen, buf); | ||
387 | } | 277 | } |
388 | 278 | ||
389 | static inline int mtd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, | 279 | int mtd_get_fact_prot_info(struct mtd_info *mtd, struct otp_info *buf, |
390 | size_t len) | 280 | size_t len); |
391 | { | 281 | int mtd_read_fact_prot_reg(struct mtd_info *mtd, loff_t from, size_t len, |
392 | if (!mtd->lock_user_prot_reg) | 282 | size_t *retlen, u_char *buf); |
393 | return -EOPNOTSUPP; | 283 | int mtd_get_user_prot_info(struct mtd_info *mtd, struct otp_info *buf, |
394 | return mtd->lock_user_prot_reg(mtd, from, len); | 284 | size_t len); |
395 | } | 285 | int mtd_read_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len, |
286 | size_t *retlen, u_char *buf); | ||
287 | int mtd_write_user_prot_reg(struct mtd_info *mtd, loff_t to, size_t len, | ||
288 | size_t *retlen, u_char *buf); | ||
289 | int mtd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len); | ||
396 | 290 | ||
397 | int mtd_writev(struct mtd_info *mtd, const struct kvec *vecs, | 291 | int mtd_writev(struct mtd_info *mtd, const struct kvec *vecs, |
398 | unsigned long count, loff_t to, size_t *retlen); | 292 | unsigned long count, loff_t to, size_t *retlen); |
399 | 293 | ||
400 | static inline void mtd_sync(struct mtd_info *mtd) | 294 | static inline void mtd_sync(struct mtd_info *mtd) |
401 | { | 295 | { |
402 | if (mtd->sync) | 296 | if (mtd->_sync) |
403 | mtd->sync(mtd); | 297 | mtd->_sync(mtd); |
404 | } | ||
405 | |||
406 | /* Chip-supported device locking */ | ||
407 | static inline int mtd_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | ||
408 | { | ||
409 | if (!mtd->lock) | ||
410 | return -EOPNOTSUPP; | ||
411 | return mtd->lock(mtd, ofs, len); | ||
412 | } | 298 | } |
413 | 299 | ||
414 | static inline int mtd_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | 300 | int mtd_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len); |
415 | { | 301 | int mtd_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len); |
416 | if (!mtd->unlock) | 302 | int mtd_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len); |
417 | return -EOPNOTSUPP; | 303 | int mtd_block_isbad(struct mtd_info *mtd, loff_t ofs); |
418 | return mtd->unlock(mtd, ofs, len); | 304 | int mtd_block_markbad(struct mtd_info *mtd, loff_t ofs); |
419 | } | ||
420 | |||
421 | static inline int mtd_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) | ||
422 | { | ||
423 | if (!mtd->is_locked) | ||
424 | return -EOPNOTSUPP; | ||
425 | return mtd->is_locked(mtd, ofs, len); | ||
426 | } | ||
427 | 305 | ||
428 | static inline int mtd_suspend(struct mtd_info *mtd) | 306 | static inline int mtd_suspend(struct mtd_info *mtd) |
429 | { | 307 | { |
430 | return mtd->suspend ? mtd->suspend(mtd) : 0; | 308 | return mtd->_suspend ? mtd->_suspend(mtd) : 0; |
431 | } | 309 | } |
432 | 310 | ||
433 | static inline void mtd_resume(struct mtd_info *mtd) | 311 | static inline void mtd_resume(struct mtd_info *mtd) |
434 | { | 312 | { |
435 | if (mtd->resume) | 313 | if (mtd->_resume) |
436 | mtd->resume(mtd); | 314 | mtd->_resume(mtd); |
437 | } | ||
438 | |||
439 | static inline int mtd_block_isbad(struct mtd_info *mtd, loff_t ofs) | ||
440 | { | ||
441 | if (!mtd->block_isbad) | ||
442 | return 0; | ||
443 | return mtd->block_isbad(mtd, ofs); | ||
444 | } | ||
445 | |||
446 | static inline int mtd_block_markbad(struct mtd_info *mtd, loff_t ofs) | ||
447 | { | ||
448 | if (!mtd->block_markbad) | ||
449 | return -EOPNOTSUPP; | ||
450 | return mtd->block_markbad(mtd, ofs); | ||
451 | } | 315 | } |
452 | 316 | ||
453 | static inline uint32_t mtd_div_by_eb(uint64_t sz, struct mtd_info *mtd) | 317 | static inline uint32_t mtd_div_by_eb(uint64_t sz, struct mtd_info *mtd) |
@@ -482,12 +346,12 @@ static inline uint32_t mtd_mod_by_ws(uint64_t sz, struct mtd_info *mtd) | |||
482 | 346 | ||
483 | static inline int mtd_has_oob(const struct mtd_info *mtd) | 347 | static inline int mtd_has_oob(const struct mtd_info *mtd) |
484 | { | 348 | { |
485 | return mtd->read_oob && mtd->write_oob; | 349 | return mtd->_read_oob && mtd->_write_oob; |
486 | } | 350 | } |
487 | 351 | ||
488 | static inline int mtd_can_have_bb(const struct mtd_info *mtd) | 352 | static inline int mtd_can_have_bb(const struct mtd_info *mtd) |
489 | { | 353 | { |
490 | return !!mtd->block_isbad; | 354 | return !!mtd->_block_isbad; |
491 | } | 355 | } |
492 | 356 | ||
493 | /* Kernel-side ioctl definitions */ | 357 | /* Kernel-side ioctl definitions */ |
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 63b5a8b6dfbd..1482340d3d9f 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h | |||
@@ -324,6 +324,7 @@ struct nand_hw_control { | |||
324 | * @steps: number of ECC steps per page | 324 | * @steps: number of ECC steps per page |
325 | * @size: data bytes per ECC step | 325 | * @size: data bytes per ECC step |
326 | * @bytes: ECC bytes per step | 326 | * @bytes: ECC bytes per step |
327 | * @strength: max number of correctible bits per ECC step | ||
327 | * @total: total number of ECC bytes per page | 328 | * @total: total number of ECC bytes per page |
328 | * @prepad: padding information for syndrome based ECC generators | 329 | * @prepad: padding information for syndrome based ECC generators |
329 | * @postpad: padding information for syndrome based ECC generators | 330 | * @postpad: padding information for syndrome based ECC generators |
@@ -351,6 +352,7 @@ struct nand_ecc_ctrl { | |||
351 | int size; | 352 | int size; |
352 | int bytes; | 353 | int bytes; |
353 | int total; | 354 | int total; |
355 | int strength; | ||
354 | int prepad; | 356 | int prepad; |
355 | int postpad; | 357 | int postpad; |
356 | struct nand_ecclayout *layout; | 358 | struct nand_ecclayout *layout; |
@@ -448,8 +450,9 @@ struct nand_buffers { | |||
448 | * will be copied to the appropriate nand_bbt_descr's. | 450 | * will be copied to the appropriate nand_bbt_descr's. |
449 | * @badblockpos: [INTERN] position of the bad block marker in the oob | 451 | * @badblockpos: [INTERN] position of the bad block marker in the oob |
450 | * area. | 452 | * area. |
451 | * @badblockbits: [INTERN] number of bits to left-shift the bad block | 453 | * @badblockbits: [INTERN] minimum number of set bits in a good block's |
452 | * number | 454 | * bad block marker position; i.e., BBM == 11110111b is |
455 | * not bad when badblockbits == 7 | ||
453 | * @cellinfo: [INTERN] MLC/multichip data from chip ident | 456 | * @cellinfo: [INTERN] MLC/multichip data from chip ident |
454 | * @numchips: [INTERN] number of physical chips | 457 | * @numchips: [INTERN] number of physical chips |
455 | * @chipsize: [INTERN] the size of one chip for multichip arrays | 458 | * @chipsize: [INTERN] the size of one chip for multichip arrays |
diff --git a/include/linux/mtd/pmc551.h b/include/linux/mtd/pmc551.h deleted file mode 100644 index 27ad40aed19f..000000000000 --- a/include/linux/mtd/pmc551.h +++ /dev/null | |||
@@ -1,78 +0,0 @@ | |||
1 | /* | ||
2 | * PMC551 PCI Mezzanine Ram Device | ||
3 | * | ||
4 | * Author: | ||
5 | * Mark Ferrell | ||
6 | * Copyright 1999,2000 Nortel Networks | ||
7 | * | ||
8 | * License: | ||
9 | * As part of this driver was derrived from the slram.c driver it falls | ||
10 | * under the same license, which is GNU General Public License v2 | ||
11 | */ | ||
12 | |||
13 | #ifndef __MTD_PMC551_H__ | ||
14 | #define __MTD_PMC551_H__ | ||
15 | |||
16 | #include <linux/mtd/mtd.h> | ||
17 | |||
18 | #define PMC551_VERSION \ | ||
19 | "Ramix PMC551 PCI Mezzanine Ram Driver. (C) 1999,2000 Nortel Networks.\n" | ||
20 | |||
21 | /* | ||
22 | * Our personal and private information | ||
23 | */ | ||
24 | struct mypriv { | ||
25 | struct pci_dev *dev; | ||
26 | u_char *start; | ||
27 | u32 base_map0; | ||
28 | u32 curr_map0; | ||
29 | u32 asize; | ||
30 | struct mtd_info *nextpmc551; | ||
31 | }; | ||
32 | |||
33 | /* | ||
34 | * Function Prototypes | ||
35 | */ | ||
36 | static int pmc551_erase(struct mtd_info *, struct erase_info *); | ||
37 | static void pmc551_unpoint(struct mtd_info *, loff_t, size_t); | ||
38 | static int pmc551_point(struct mtd_info *mtd, loff_t from, size_t len, | ||
39 | size_t *retlen, void **virt, resource_size_t *phys); | ||
40 | static int pmc551_read(struct mtd_info *, loff_t, size_t, size_t *, u_char *); | ||
41 | static int pmc551_write(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); | ||
42 | |||
43 | |||
44 | /* | ||
45 | * Define the PCI ID's if the kernel doesn't define them for us | ||
46 | */ | ||
47 | #ifndef PCI_VENDOR_ID_V3_SEMI | ||
48 | #define PCI_VENDOR_ID_V3_SEMI 0x11b0 | ||
49 | #endif | ||
50 | |||
51 | #ifndef PCI_DEVICE_ID_V3_SEMI_V370PDC | ||
52 | #define PCI_DEVICE_ID_V3_SEMI_V370PDC 0x0200 | ||
53 | #endif | ||
54 | |||
55 | |||
56 | #define PMC551_PCI_MEM_MAP0 0x50 | ||
57 | #define PMC551_PCI_MEM_MAP1 0x54 | ||
58 | #define PMC551_PCI_MEM_MAP_MAP_ADDR_MASK 0x3ff00000 | ||
59 | #define PMC551_PCI_MEM_MAP_APERTURE_MASK 0x000000f0 | ||
60 | #define PMC551_PCI_MEM_MAP_REG_EN 0x00000002 | ||
61 | #define PMC551_PCI_MEM_MAP_ENABLE 0x00000001 | ||
62 | |||
63 | #define PMC551_SDRAM_MA 0x60 | ||
64 | #define PMC551_SDRAM_CMD 0x62 | ||
65 | #define PMC551_DRAM_CFG 0x64 | ||
66 | #define PMC551_SYS_CTRL_REG 0x78 | ||
67 | |||
68 | #define PMC551_DRAM_BLK0 0x68 | ||
69 | #define PMC551_DRAM_BLK1 0x6c | ||
70 | #define PMC551_DRAM_BLK2 0x70 | ||
71 | #define PMC551_DRAM_BLK3 0x74 | ||
72 | #define PMC551_DRAM_BLK_GET_SIZE(x) (524288<<((x>>4)&0x0f)) | ||
73 | #define PMC551_DRAM_BLK_SET_COL_MUX(x,v) (((x) & ~0x00007000) | (((v) & 0x7) << 12)) | ||
74 | #define PMC551_DRAM_BLK_SET_ROW_MUX(x,v) (((x) & ~0x00000f00) | (((v) & 0xf) << 8)) | ||
75 | |||
76 | |||
77 | #endif /* __MTD_PMC551_H__ */ | ||
78 | |||
diff --git a/include/linux/mtd/sh_flctl.h b/include/linux/mtd/sh_flctl.h index 9cf4c4c79555..a38e1fa8af01 100644 --- a/include/linux/mtd/sh_flctl.h +++ b/include/linux/mtd/sh_flctl.h | |||
@@ -23,6 +23,7 @@ | |||
23 | #include <linux/mtd/mtd.h> | 23 | #include <linux/mtd/mtd.h> |
24 | #include <linux/mtd/nand.h> | 24 | #include <linux/mtd/nand.h> |
25 | #include <linux/mtd/partitions.h> | 25 | #include <linux/mtd/partitions.h> |
26 | #include <linux/pm_qos.h> | ||
26 | 27 | ||
27 | /* FLCTL registers */ | 28 | /* FLCTL registers */ |
28 | #define FLCMNCR(f) (f->reg + 0x0) | 29 | #define FLCMNCR(f) (f->reg + 0x0) |
@@ -38,6 +39,7 @@ | |||
38 | #define FLDTFIFO(f) (f->reg + 0x24) | 39 | #define FLDTFIFO(f) (f->reg + 0x24) |
39 | #define FLECFIFO(f) (f->reg + 0x28) | 40 | #define FLECFIFO(f) (f->reg + 0x28) |
40 | #define FLTRCR(f) (f->reg + 0x2C) | 41 | #define FLTRCR(f) (f->reg + 0x2C) |
42 | #define FLHOLDCR(f) (f->reg + 0x38) | ||
41 | #define FL4ECCRESULT0(f) (f->reg + 0x80) | 43 | #define FL4ECCRESULT0(f) (f->reg + 0x80) |
42 | #define FL4ECCRESULT1(f) (f->reg + 0x84) | 44 | #define FL4ECCRESULT1(f) (f->reg + 0x84) |
43 | #define FL4ECCRESULT2(f) (f->reg + 0x88) | 45 | #define FL4ECCRESULT2(f) (f->reg + 0x88) |
@@ -67,6 +69,30 @@ | |||
67 | #define CE0_ENABLE (0x1 << 3) /* Chip Enable 0 */ | 69 | #define CE0_ENABLE (0x1 << 3) /* Chip Enable 0 */ |
68 | #define TYPESEL_SET (0x1 << 0) | 70 | #define TYPESEL_SET (0x1 << 0) |
69 | 71 | ||
72 | /* | ||
73 | * Clock settings using the PULSEx registers from FLCMNCR | ||
74 | * | ||
75 | * Some hardware uses bits called PULSEx instead of FCKSEL_E and QTSEL_E | ||
76 | * to control the clock divider used between the High-Speed Peripheral Clock | ||
77 | * and the FLCTL internal clock. If so, use CLK_8_BIT_xxx for connecting 8 bit | ||
78 | * and CLK_16_BIT_xxx for connecting 16 bit bus bandwith NAND chips. For the 16 | ||
79 | * bit version the divider is seperate for the pulse width of high and low | ||
80 | * signals. | ||
81 | */ | ||
82 | #define PULSE3 (0x1 << 27) | ||
83 | #define PULSE2 (0x1 << 17) | ||
84 | #define PULSE1 (0x1 << 15) | ||
85 | #define PULSE0 (0x1 << 9) | ||
86 | #define CLK_8B_0_5 PULSE1 | ||
87 | #define CLK_8B_1 0x0 | ||
88 | #define CLK_8B_1_5 (PULSE1 | PULSE2) | ||
89 | #define CLK_8B_2 PULSE0 | ||
90 | #define CLK_8B_3 (PULSE0 | PULSE1 | PULSE2) | ||
91 | #define CLK_8B_4 (PULSE0 | PULSE2) | ||
92 | #define CLK_16B_6L_2H PULSE0 | ||
93 | #define CLK_16B_9L_3H (PULSE0 | PULSE1 | PULSE2) | ||
94 | #define CLK_16B_12L_4H (PULSE0 | PULSE2) | ||
95 | |||
70 | /* FLCMDCR control bits */ | 96 | /* FLCMDCR control bits */ |
71 | #define ADRCNT2_E (0x1 << 31) /* 5byte address enable */ | 97 | #define ADRCNT2_E (0x1 << 31) /* 5byte address enable */ |
72 | #define ADRMD_E (0x1 << 26) /* Sector address access */ | 98 | #define ADRMD_E (0x1 << 26) /* Sector address access */ |
@@ -85,6 +111,15 @@ | |||
85 | #define TRSTRT (0x1 << 0) /* translation start */ | 111 | #define TRSTRT (0x1 << 0) /* translation start */ |
86 | #define TREND (0x1 << 1) /* translation end */ | 112 | #define TREND (0x1 << 1) /* translation end */ |
87 | 113 | ||
114 | /* | ||
115 | * FLHOLDCR control bits | ||
116 | * | ||
117 | * HOLDEN: Bus Occupancy Enable (inverted) | ||
118 | * Enable this bit when the external bus might be used in between transfers. | ||
119 | * If not set and the bus gets used by other modules, a deadlock occurs. | ||
120 | */ | ||
121 | #define HOLDEN (0x1 << 0) | ||
122 | |||
88 | /* FL4ECCCR control bits */ | 123 | /* FL4ECCCR control bits */ |
89 | #define _4ECCFA (0x1 << 2) /* 4 symbols correct fault */ | 124 | #define _4ECCFA (0x1 << 2) /* 4 symbols correct fault */ |
90 | #define _4ECCEND (0x1 << 1) /* 4 symbols end */ | 125 | #define _4ECCEND (0x1 << 1) /* 4 symbols end */ |
@@ -97,6 +132,7 @@ struct sh_flctl { | |||
97 | struct mtd_info mtd; | 132 | struct mtd_info mtd; |
98 | struct nand_chip chip; | 133 | struct nand_chip chip; |
99 | struct platform_device *pdev; | 134 | struct platform_device *pdev; |
135 | struct dev_pm_qos_request pm_qos; | ||
100 | void __iomem *reg; | 136 | void __iomem *reg; |
101 | 137 | ||
102 | uint8_t done_buff[2048 + 64]; /* max size 2048 + 64 */ | 138 | uint8_t done_buff[2048 + 64]; /* max size 2048 + 64 */ |
@@ -108,11 +144,14 @@ struct sh_flctl { | |||
108 | int erase1_page_addr; /* page_addr in ERASE1 cmd */ | 144 | int erase1_page_addr; /* page_addr in ERASE1 cmd */ |
109 | uint32_t erase_ADRCNT; /* bits of FLCMDCR in ERASE1 cmd */ | 145 | uint32_t erase_ADRCNT; /* bits of FLCMDCR in ERASE1 cmd */ |
110 | uint32_t rw_ADRCNT; /* bits of FLCMDCR in READ WRITE cmd */ | 146 | uint32_t rw_ADRCNT; /* bits of FLCMDCR in READ WRITE cmd */ |
147 | uint32_t flcmncr_base; /* base value of FLCMNCR */ | ||
111 | 148 | ||
112 | int hwecc_cant_correct[4]; | 149 | int hwecc_cant_correct[4]; |
113 | 150 | ||
114 | unsigned page_size:1; /* NAND page size (0 = 512, 1 = 2048) */ | 151 | unsigned page_size:1; /* NAND page size (0 = 512, 1 = 2048) */ |
115 | unsigned hwecc:1; /* Hardware ECC (0 = disabled, 1 = enabled) */ | 152 | unsigned hwecc:1; /* Hardware ECC (0 = disabled, 1 = enabled) */ |
153 | unsigned holden:1; /* Hardware has FLHOLDCR and HOLDEN is set */ | ||
154 | unsigned qos_request:1; /* QoS request to prevent deep power shutdown */ | ||
116 | }; | 155 | }; |
117 | 156 | ||
118 | struct sh_flctl_platform_data { | 157 | struct sh_flctl_platform_data { |
@@ -121,6 +160,7 @@ struct sh_flctl_platform_data { | |||
121 | unsigned long flcmncr_val; | 160 | unsigned long flcmncr_val; |
122 | 161 | ||
123 | unsigned has_hwecc:1; | 162 | unsigned has_hwecc:1; |
163 | unsigned use_holden:1; | ||
124 | }; | 164 | }; |
125 | 165 | ||
126 | static inline struct sh_flctl *mtd_to_flctl(struct mtd_info *mtdinfo) | 166 | static inline struct sh_flctl *mtd_to_flctl(struct mtd_info *mtdinfo) |
diff --git a/include/linux/mtd/spear_smi.h b/include/linux/mtd/spear_smi.h new file mode 100644 index 000000000000..8ae1726044c3 --- /dev/null +++ b/include/linux/mtd/spear_smi.h | |||
@@ -0,0 +1,65 @@ | |||
1 | /* | ||
2 | * Copyright © 2010 ST Microelectronics | ||
3 | * Shiraz Hashim <shiraz.hashim@st.com> | ||
4 | * | ||
5 | * This file is licensed under the terms of the GNU General Public | ||
6 | * License version 2. This program is licensed "as is" without any | ||
7 | * warranty of any kind, whether express or implied. | ||
8 | */ | ||
9 | |||
10 | #ifndef __MTD_SPEAR_SMI_H | ||
11 | #define __MTD_SPEAR_SMI_H | ||
12 | |||
13 | #include <linux/types.h> | ||
14 | #include <linux/mtd/mtd.h> | ||
15 | #include <linux/mtd/partitions.h> | ||
16 | #include <linux/platform_device.h> | ||
17 | #include <linux/of.h> | ||
18 | |||
19 | /* max possible slots for serial-nor flash chip in the SMI controller */ | ||
20 | #define MAX_NUM_FLASH_CHIP 4 | ||
21 | |||
22 | /* macro to define partitions for flash devices */ | ||
23 | #define DEFINE_PARTS(n, of, s) \ | ||
24 | { \ | ||
25 | .name = n, \ | ||
26 | .offset = of, \ | ||
27 | .size = s, \ | ||
28 | } | ||
29 | |||
30 | /** | ||
31 | * struct spear_smi_flash_info - platform structure for passing flash | ||
32 | * information | ||
33 | * | ||
34 | * name: name of the serial nor flash for identification | ||
35 | * mem_base: the memory base on which the flash is mapped | ||
36 | * size: size of the flash in bytes | ||
37 | * partitions: parition details | ||
38 | * nr_partitions: number of partitions | ||
39 | * fast_mode: whether flash supports fast mode | ||
40 | */ | ||
41 | |||
42 | struct spear_smi_flash_info { | ||
43 | char *name; | ||
44 | unsigned long mem_base; | ||
45 | unsigned long size; | ||
46 | struct mtd_partition *partitions; | ||
47 | int nr_partitions; | ||
48 | u8 fast_mode; | ||
49 | }; | ||
50 | |||
51 | /** | ||
52 | * struct spear_smi_plat_data - platform structure for configuring smi | ||
53 | * | ||
54 | * clk_rate: clk rate at which SMI must operate | ||
55 | * num_flashes: number of flashes present on board | ||
56 | * board_flash_info: specific details of each flash present on board | ||
57 | */ | ||
58 | struct spear_smi_plat_data { | ||
59 | unsigned long clk_rate; | ||
60 | int num_flashes; | ||
61 | struct spear_smi_flash_info *board_flash_info; | ||
62 | struct device_node *np[MAX_NUM_FLASH_CHIP]; | ||
63 | }; | ||
64 | |||
65 | #endif /* __MTD_SPEAR_SMI_H */ | ||