diff options
author | Paul Mundt <lethal@linux-sh.org> | 2010-11-30 00:42:55 -0500 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2010-11-30 00:42:55 -0500 |
commit | d8e7943d821d8ee7f48ff38f6f7c509297c88402 (patch) | |
tree | 7c3990942d495fd6bdfcdf6e69fe37bda8e4ce33 /include/linux/mmc/sh_mmcif.h | |
parent | df73af86b6e737f357aae85e0b5e621516117780 (diff) | |
parent | 22efa0fee32d9e7f6f6fbc396a872b5708d86048 (diff) |
Merge branch 'common/mmcif' into rmobile/mmcif
Diffstat (limited to 'include/linux/mmc/sh_mmcif.h')
-rw-r--r-- | include/linux/mmc/sh_mmcif.h | 26 |
1 files changed, 12 insertions, 14 deletions
diff --git a/include/linux/mmc/sh_mmcif.h b/include/linux/mmc/sh_mmcif.h index f216a8879b58..44fc5348fd5d 100644 --- a/include/linux/mmc/sh_mmcif.h +++ b/include/linux/mmc/sh_mmcif.h | |||
@@ -77,6 +77,9 @@ struct sh_mmcif_plat_data { | |||
77 | #define CLK_ENABLE (1 << 24) /* 1: output mmc clock */ | 77 | #define CLK_ENABLE (1 << 24) /* 1: output mmc clock */ |
78 | #define CLK_CLEAR ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16)) | 78 | #define CLK_CLEAR ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16)) |
79 | #define CLK_SUP_PCLK ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16)) | 79 | #define CLK_SUP_PCLK ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16)) |
80 | #define CLKDIV_4 (1<<16) /* mmc clock frequency. | ||
81 | * n: bus clock/(2^(n+1)) */ | ||
82 | #define CLKDIV_256 (7<<16) /* mmc clock frequency. (see above) */ | ||
80 | #define SRSPTO_256 ((1 << 13) | (0 << 12)) /* resp timeout */ | 83 | #define SRSPTO_256 ((1 << 13) | (0 << 12)) /* resp timeout */ |
81 | #define SRBSYTO_29 ((1 << 11) | (1 << 10) | \ | 84 | #define SRBSYTO_29 ((1 << 11) | (1 << 10) | \ |
82 | (1 << 9) | (1 << 8)) /* resp busy timeout */ | 85 | (1 << 9) | (1 << 8)) /* resp busy timeout */ |
@@ -87,7 +90,7 @@ struct sh_mmcif_plat_data { | |||
87 | 90 | ||
88 | /* CE_VERSION */ | 91 | /* CE_VERSION */ |
89 | #define SOFT_RST_ON (1 << 31) | 92 | #define SOFT_RST_ON (1 << 31) |
90 | #define SOFT_RST_OFF ~SOFT_RST_ON | 93 | #define SOFT_RST_OFF 0 |
91 | 94 | ||
92 | static inline u32 sh_mmcif_readl(void __iomem *addr, int reg) | 95 | static inline u32 sh_mmcif_readl(void __iomem *addr, int reg) |
93 | { | 96 | { |
@@ -175,12 +178,9 @@ static inline int sh_mmcif_boot_do_read(void __iomem *base, | |||
175 | 178 | ||
176 | static inline void sh_mmcif_boot_init(void __iomem *base) | 179 | static inline void sh_mmcif_boot_init(void __iomem *base) |
177 | { | 180 | { |
178 | unsigned long tmp; | ||
179 | |||
180 | /* reset */ | 181 | /* reset */ |
181 | tmp = sh_mmcif_readl(base, MMCIF_CE_VERSION); | 182 | sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_ON); |
182 | sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp | SOFT_RST_ON); | 183 | sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_OFF); |
183 | sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp & SOFT_RST_OFF); | ||
184 | 184 | ||
185 | /* byte swap */ | 185 | /* byte swap */ |
186 | sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); | 186 | sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); |
@@ -188,14 +188,10 @@ static inline void sh_mmcif_boot_init(void __iomem *base) | |||
188 | /* Set block size in MMCIF hardware */ | 188 | /* Set block size in MMCIF hardware */ |
189 | sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS); | 189 | sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS); |
190 | 190 | ||
191 | /* Enable the clock, set it to Bus clock/256 (about 325Khz). | 191 | /* Enable the clock, set it to Bus clock/256 (about 325Khz). */ |
192 | * It is unclear where 0x70000 comes from or if it is even needed. | ||
193 | * It is there for byte-compatibility with code that is known to | ||
194 | * work. | ||
195 | */ | ||
196 | sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, | 192 | sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, |
197 | CLK_ENABLE | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | | 193 | CLK_ENABLE | CLKDIV_256 | SRSPTO_256 | |
198 | SCCSTO_29 | 0x70000); | 194 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29); |
199 | 195 | ||
200 | /* CMD0 */ | 196 | /* CMD0 */ |
201 | sh_mmcif_boot_cmd(base, 0x00000040, 0); | 197 | sh_mmcif_boot_cmd(base, 0x00000040, 0); |
@@ -220,7 +216,9 @@ static inline void sh_mmcif_boot_slurp(void __iomem *base, | |||
220 | unsigned long tmp; | 216 | unsigned long tmp; |
221 | 217 | ||
222 | /* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */ | 218 | /* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */ |
223 | sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, 0x01012fff); | 219 | sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, |
220 | CLK_ENABLE | CLKDIV_4 | SRSPTO_256 | | ||
221 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29); | ||
224 | 222 | ||
225 | /* CMD9 - Get CSD */ | 223 | /* CMD9 - Get CSD */ |
226 | sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000); | 224 | sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000); |