diff options
| author | Saeed Mahameed <saeedm@mellanox.com> | 2014-10-27 05:37:37 -0400 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2014-10-28 17:18:00 -0400 |
| commit | adbc7ac5c15eb5e9d70393428345e72a1a897d6a (patch) | |
| tree | ffd61c6e2196a0b5a59534198528a7204269a792 /include/linux/mlx4 | |
| parent | 7202da8b7f7131d25411d81aa557e28cd941c5b6 (diff) | |
net/mlx4_core: Introduce ACCESS_REG CMD and eth_prot_ctrl dev cap
Adding ACCESS REG mlx4 command and use it to implement Query method for
PTYS (Port Type and Speed Register).
Query and store eth_prot_ctrl dev cap.
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Signed-off-by: Amir Vadai <amirv@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/linux/mlx4')
| -rw-r--r-- | include/linux/mlx4/cmd.h | 2 | ||||
| -rw-r--r-- | include/linux/mlx4/device.h | 40 |
2 files changed, 41 insertions, 1 deletions
diff --git a/include/linux/mlx4/cmd.h b/include/linux/mlx4/cmd.h index 379c02648ab3..ff5f5deb3dcf 100644 --- a/include/linux/mlx4/cmd.h +++ b/include/linux/mlx4/cmd.h | |||
| @@ -67,6 +67,8 @@ enum { | |||
| 67 | MLX4_CMD_MAP_ICM_AUX = 0xffc, | 67 | MLX4_CMD_MAP_ICM_AUX = 0xffc, |
| 68 | MLX4_CMD_UNMAP_ICM_AUX = 0xffb, | 68 | MLX4_CMD_UNMAP_ICM_AUX = 0xffb, |
| 69 | MLX4_CMD_SET_ICM_SIZE = 0xffd, | 69 | MLX4_CMD_SET_ICM_SIZE = 0xffd, |
| 70 | MLX4_CMD_ACCESS_REG = 0x3b, | ||
| 71 | |||
| 70 | /*master notify fw on finish for slave's flr*/ | 72 | /*master notify fw on finish for slave's flr*/ |
| 71 | MLX4_CMD_INFORM_FLR_DONE = 0x5b, | 73 | MLX4_CMD_INFORM_FLR_DONE = 0x5b, |
| 72 | MLX4_CMD_GET_OP_REQ = 0x59, | 74 | MLX4_CMD_GET_OP_REQ = 0x59, |
diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h index 73910daec317..181cd9fc90f2 100644 --- a/include/linux/mlx4/device.h +++ b/include/linux/mlx4/device.h | |||
| @@ -186,7 +186,8 @@ enum { | |||
| 186 | MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10, | 186 | MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10, |
| 187 | MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11, | 187 | MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11, |
| 188 | MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12, | 188 | MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12, |
| 189 | MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13 | 189 | MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13, |
| 190 | MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14 | ||
| 190 | }; | 191 | }; |
| 191 | 192 | ||
| 192 | enum { | 193 | enum { |
| @@ -1319,4 +1320,41 @@ static inline bool mlx4_low_memory_profile(void) | |||
| 1319 | return is_kdump_kernel(); | 1320 | return is_kdump_kernel(); |
| 1320 | } | 1321 | } |
| 1321 | 1322 | ||
| 1323 | /* ACCESS REG commands */ | ||
| 1324 | enum mlx4_access_reg_method { | ||
| 1325 | MLX4_ACCESS_REG_QUERY = 0x1, | ||
| 1326 | MLX4_ACCESS_REG_WRITE = 0x2, | ||
| 1327 | }; | ||
| 1328 | |||
| 1329 | /* ACCESS PTYS Reg command */ | ||
| 1330 | enum mlx4_ptys_proto { | ||
| 1331 | MLX4_PTYS_IB = 1<<0, | ||
| 1332 | MLX4_PTYS_EN = 1<<2, | ||
| 1333 | }; | ||
| 1334 | |||
| 1335 | struct mlx4_ptys_reg { | ||
| 1336 | u8 resrvd1; | ||
| 1337 | u8 local_port; | ||
| 1338 | u8 resrvd2; | ||
| 1339 | u8 proto_mask; | ||
| 1340 | __be32 resrvd3[2]; | ||
| 1341 | __be32 eth_proto_cap; | ||
| 1342 | __be16 ib_width_cap; | ||
| 1343 | __be16 ib_speed_cap; | ||
| 1344 | __be32 resrvd4; | ||
| 1345 | __be32 eth_proto_admin; | ||
| 1346 | __be16 ib_width_admin; | ||
| 1347 | __be16 ib_speed_admin; | ||
| 1348 | __be32 resrvd5; | ||
| 1349 | __be32 eth_proto_oper; | ||
| 1350 | __be16 ib_width_oper; | ||
| 1351 | __be16 ib_speed_oper; | ||
| 1352 | __be32 resrvd6; | ||
| 1353 | __be32 eth_proto_lp_adv; | ||
| 1354 | } __packed; | ||
| 1355 | |||
| 1356 | int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev, | ||
| 1357 | enum mlx4_access_reg_method method, | ||
| 1358 | struct mlx4_ptys_reg *ptys_reg); | ||
| 1359 | |||
| 1322 | #endif /* MLX4_DEVICE_H */ | 1360 | #endif /* MLX4_DEVICE_H */ |
