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authorMatan Barak <matanb@mellanox.com>2014-11-13 07:45:32 -0500
committerDavid S. Miller <davem@davemloft.net>2014-11-13 15:16:21 -0500
commit7ae0e400cd9396c41fe596d35dcc34feaa89a04f (patch)
tree0cc4b53c1d8ad12d2b1624dcedc5a2e0c8b6e950 /include/linux/mlx4
parente8c4265bea8437f5583d0c2f272058200ebc10ff (diff)
net/mlx4_core: Flexible (asymmetric) allocation of EQs and MSI-X vectors for PF/VFs
Previously, the driver queried the firmware in order to get the number of supported EQs. Under SRIOV, since this was done before the driver notified the firmware how many VFs it actually needs, the firmware had to take into account a worst case scenario and always allocated four EQs per VF, where one was used for events while the others were used for completions. Now, when the firmware supports the asymmetric allocation scheme, denoted by exposing num_sys_eqs > 0 (--> MLX4_DEV_CAP_FLAG2_SYS_EQS), we use the QUERY_FUNC command to query the firmware before enabling SRIOV. Thus we can get more EQs and MSI-X vectors per function. Moreover, when running in the new firmware/driver mode, the limitation that the number of EQs should be a power of two is lifted. Signed-off-by: Jack Morgenstein <jackm@dev.mellanox.co.il> Signed-off-by: Matan Barak <matanb@mellanox.com> Signed-off-by: Or Gerlitz <ogerlitz@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/linux/mlx4')
-rw-r--r--include/linux/mlx4/device.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h
index 3d9bff00f24a..1c560eb870ad 100644
--- a/include/linux/mlx4/device.h
+++ b/include/linux/mlx4/device.h
@@ -189,7 +189,8 @@ enum {
189 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13, 189 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13,
190 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14, 190 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14,
191 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15, 191 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15,
192 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16 192 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16,
193 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17
193}; 194};
194 195
195enum { 196enum {
@@ -443,6 +444,7 @@ struct mlx4_caps {
443 int num_cqs; 444 int num_cqs;
444 int max_cqes; 445 int max_cqes;
445 int reserved_cqs; 446 int reserved_cqs;
447 int num_sys_eqs;
446 int num_eqs; 448 int num_eqs;
447 int reserved_eqs; 449 int reserved_eqs;
448 int num_comp_vectors; 450 int num_comp_vectors;