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authorLinus Torvalds <torvalds@linux-foundation.org>2014-10-15 00:58:16 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-10-15 00:58:16 -0400
commitfcc3a5d277571bc6048e7b4ef8cd391b935de629 (patch)
tree143954c115011c657f747a0e1470973b94ab3690 /include/linux/mfd
parent50fa86172bec2769979b5eb0cd1a244391ae4bb0 (diff)
parentd86c21fd31114e3ef9fae64be335c76aa22859dc (diff)
Merge tag 'mfd-for-linus-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
Pull MFD updates from Lee Jones: "Changes to existing drivers: - DT clean-ups in da9055-core, max14577, rn5t618, arizona, hi6421, stmpe, twl4030 - Export symbols for use in modules in max14577 - Plenty of static code analysis/Coccinelle fixes throughout the SS - Regmap clean-ups in arizona, wm5102, wm5110, da9052, tps65217, rk808 - Remove unused/duplicate code in da9052, 88pm860x, ti_ssp, lpc_sch, arizona - Bug fixes in ti_am335x_tscadc, da9052, ti_am335x_tscadc, rtsx_pcr - IRQ fixups in arizona, stmpe, max14577 - Regulator related changes in axp20x - Pass DMA coherency information from parent => child in MFD core - Rename DT document files for consistency - Add ACPI support to the MFD core - Add Andreas Werner to MAINTAINERS for MEN F21BMC New drivers/supported devices: - New driver for MEN 14F021P00 Board Management Controller - New driver for Ricoh RN5T618 PMIC - New driver for Rockchip RK808 - New driver for HiSilicon Hi6421 PMIC - New driver for Qualcomm SPMI PMICs - Add support for Intel Braswell in lpc_ich - Add support for Intel 9 Series PCH in lpc_ich - Add support for Intel Quark ILB in lpc_sch" [ Delayed to after the poweer/reset pull due to Kconfig problems with recursive Kconfig select/depends-on chains. - Linus ] * tag 'mfd-for-linus-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (79 commits) mfd: cros_ec: wait for completion of commands that return IN_PROGRESS i2c: i2c-cros-ec-tunnel: Set retries to 3 mfd: cros_ec: move locking into cros_ec_cmd_xfer mfd: cros_ec: stop calling ->cmd_xfer() directly mfd: cros_ec: Delay for 50ms when we see EC_CMD_REBOOT_EC MAINTAINERS: Adds Andreas Werner to maintainers list for MEN F21BMC mfd: arizona: Correct mask to allow setting micbias external cap mfd: Add ACPI support Revert "mfd: wm5102: Manually apply register patch" mfd: ti_am335x_tscadc: Update logic in CTRL register for 5-wire TS mfd: dt-bindings: atmel-gpbr: Rename doc file to conform to naming convention mfd: dt-bindings: qcom-pm8xxx: Rename doc file to conform to naming convention mfd: Inherit coherent_dma_mask from parent device mfd: Document DT bindings for Qualcomm SPMI PMICs mfd: Add support for Qualcomm SPMI PMICs mfd: dt-bindings: pm8xxx: Add new compatible string mfd: axp209x: Drop the parent supplies field mfd: twl4030-power: Use 'ti,system-power-controller' as alternative way to support system power off mfd: dt-bindings: twl4030-power: Use the standard property to mark power control mfd: syscon: Add Atmel GPBR DT bindings documention ...
Diffstat (limited to 'include/linux/mfd')
-rw-r--r--include/linux/mfd/arizona/registers.h29
-rw-r--r--include/linux/mfd/core.h3
-rw-r--r--include/linux/mfd/cros_ec.h24
-rw-r--r--include/linux/mfd/da9052/da9052.h2
-rw-r--r--include/linux/mfd/davinci_voicecodec.h2
-rw-r--r--include/linux/mfd/hi6421-pmic.h41
-rw-r--r--include/linux/mfd/max77693-private.h61
-rw-r--r--include/linux/mfd/max77693.h40
-rw-r--r--include/linux/mfd/rk808.h196
-rw-r--r--include/linux/mfd/rn5t618.h228
-rw-r--r--include/linux/mfd/ti_am335x_tscadc.h1
-rw-r--r--include/linux/mfd/ti_ssp.h93
-rw-r--r--include/linux/mfd/tps65217.h2
13 files changed, 614 insertions, 108 deletions
diff --git a/include/linux/mfd/arizona/registers.h b/include/linux/mfd/arizona/registers.h
index dbd23c36de21..c0b075f6bc35 100644
--- a/include/linux/mfd/arizona/registers.h
+++ b/include/linux/mfd/arizona/registers.h
@@ -27,6 +27,7 @@
27#define ARIZONA_WRITE_SEQUENCER_CTRL_0 0x16 27#define ARIZONA_WRITE_SEQUENCER_CTRL_0 0x16
28#define ARIZONA_WRITE_SEQUENCER_CTRL_1 0x17 28#define ARIZONA_WRITE_SEQUENCER_CTRL_1 0x17
29#define ARIZONA_WRITE_SEQUENCER_CTRL_2 0x18 29#define ARIZONA_WRITE_SEQUENCER_CTRL_2 0x18
30#define ARIZONA_WRITE_SEQUENCER_CTRL_3 0x19
30#define ARIZONA_WRITE_SEQUENCER_PROM 0x1A 31#define ARIZONA_WRITE_SEQUENCER_PROM 0x1A
31#define ARIZONA_TONE_GENERATOR_1 0x20 32#define ARIZONA_TONE_GENERATOR_1 0x20
32#define ARIZONA_TONE_GENERATOR_2 0x21 33#define ARIZONA_TONE_GENERATOR_2 0x21
@@ -70,7 +71,9 @@
70#define ARIZONA_SAMPLE_RATE_3_STATUS 0x10C 71#define ARIZONA_SAMPLE_RATE_3_STATUS 0x10C
71#define ARIZONA_ASYNC_CLOCK_1 0x112 72#define ARIZONA_ASYNC_CLOCK_1 0x112
72#define ARIZONA_ASYNC_SAMPLE_RATE_1 0x113 73#define ARIZONA_ASYNC_SAMPLE_RATE_1 0x113
74#define ARIZONA_ASYNC_SAMPLE_RATE_2 0x114
73#define ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS 0x11B 75#define ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS 0x11B
76#define ARIZONA_ASYNC_SAMPLE_RATE_2_STATUS 0x11C
74#define ARIZONA_OUTPUT_SYSTEM_CLOCK 0x149 77#define ARIZONA_OUTPUT_SYSTEM_CLOCK 0x149
75#define ARIZONA_OUTPUT_ASYNC_CLOCK 0x14A 78#define ARIZONA_OUTPUT_ASYNC_CLOCK 0x14A
76#define ARIZONA_RATE_ESTIMATOR_1 0x152 79#define ARIZONA_RATE_ESTIMATOR_1 0x152
@@ -1664,16 +1667,30 @@
1664/* 1667/*
1665 * R275 (0x113) - Async sample rate 1 1668 * R275 (0x113) - Async sample rate 1
1666 */ 1669 */
1667#define ARIZONA_ASYNC_SAMPLE_RATE_MASK 0x001F /* ASYNC_SAMPLE_RATE - [4:0] */ 1670#define ARIZONA_ASYNC_SAMPLE_RATE_1_MASK 0x001F /* ASYNC_SAMPLE_RATE_1 - [4:0] */
1668#define ARIZONA_ASYNC_SAMPLE_RATE_SHIFT 0 /* ASYNC_SAMPLE_RATE - [4:0] */ 1671#define ARIZONA_ASYNC_SAMPLE_RATE_1_SHIFT 0 /* ASYNC_SAMPLE_RATE_1 - [4:0] */
1669#define ARIZONA_ASYNC_SAMPLE_RATE_WIDTH 5 /* ASYNC_SAMPLE_RATE - [4:0] */ 1672#define ARIZONA_ASYNC_SAMPLE_RATE_1_WIDTH 5 /* ASYNC_SAMPLE_RATE_1 - [4:0] */
1673
1674/*
1675 * R276 (0x114) - Async sample rate 2
1676 */
1677#define ARIZONA_ASYNC_SAMPLE_RATE_2_MASK 0x001F /* ASYNC_SAMPLE_RATE_2 - [4:0] */
1678#define ARIZONA_ASYNC_SAMPLE_RATE_2_SHIFT 0 /* ASYNC_SAMPLE_RATE_2 - [4:0] */
1679#define ARIZONA_ASYNC_SAMPLE_RATE_2_WIDTH 5 /* ASYNC_SAMPLE_RATE_2 - [4:0] */
1670 1680
1671/* 1681/*
1672 * R283 (0x11B) - Async sample rate 1 status 1682 * R283 (0x11B) - Async sample rate 1 status
1673 */ 1683 */
1674#define ARIZONA_ASYNC_SAMPLE_RATE_STS_MASK 0x001F /* ASYNC_SAMPLE_RATE_STS - [4:0] */ 1684#define ARIZONA_ASYNC_SAMPLE_RATE_1_STS_MASK 0x001F /* ASYNC_SAMPLE_RATE_1_STS - [4:0] */
1675#define ARIZONA_ASYNC_SAMPLE_RATE_STS_SHIFT 0 /* ASYNC_SAMPLE_RATE_STS - [4:0] */ 1685#define ARIZONA_ASYNC_SAMPLE_RATE_1_STS_SHIFT 0 /* ASYNC_SAMPLE_RATE_1_STS - [4:0] */
1676#define ARIZONA_ASYNC_SAMPLE_RATE_STS_WIDTH 5 /* ASYNC_SAMPLE_RATE_STS - [4:0] */ 1686#define ARIZONA_ASYNC_SAMPLE_RATE_1_STS_WIDTH 5 /* ASYNC_SAMPLE_RATE_1_STS - [4:0] */
1687
1688/*
1689 * R284 (0x11C) - Async sample rate 2 status
1690 */
1691#define ARIZONA_ASYNC_SAMPLE_RATE_2_STS_MASK 0x001F /* ASYNC_SAMPLE_RATE_2_STS - [4:0] */
1692#define ARIZONA_ASYNC_SAMPLE_RATE_2_STS_SHIFT 0 /* ASYNC_SAMPLE_RATE_2_STS - [4:0] */
1693#define ARIZONA_ASYNC_SAMPLE_RATE_2_STS_WIDTH 5 /* ASYNC_SAMPLE_RATE_2_STS - [4:0] */
1677 1694
1678/* 1695/*
1679 * R329 (0x149) - Output system clock 1696 * R329 (0x149) - Output system clock
diff --git a/include/linux/mfd/core.h b/include/linux/mfd/core.h
index f543de91ce19..73e1709d4c09 100644
--- a/include/linux/mfd/core.h
+++ b/include/linux/mfd/core.h
@@ -44,6 +44,9 @@ struct mfd_cell {
44 */ 44 */
45 const char *of_compatible; 45 const char *of_compatible;
46 46
47 /* Matches ACPI PNP id, either _HID or _CID */
48 const char *acpi_pnpid;
49
47 /* 50 /*
48 * These resources can be specified relative to the parent device. 51 * These resources can be specified relative to the parent device.
49 * For accessing hardware you should use resources from the platform dev 52 * For accessing hardware you should use resources from the platform dev
diff --git a/include/linux/mfd/cros_ec.h b/include/linux/mfd/cros_ec.h
index fcbe9d129a9d..0e166b92f5b4 100644
--- a/include/linux/mfd/cros_ec.h
+++ b/include/linux/mfd/cros_ec.h
@@ -62,10 +62,6 @@ struct cros_ec_command {
62 * @dev: Device pointer 62 * @dev: Device pointer
63 * @was_wake_device: true if this device was set to wake the system from 63 * @was_wake_device: true if this device was set to wake the system from
64 * sleep at the last suspend 64 * sleep at the last suspend
65 * @cmd_xfer: send command to EC and get response
66 * Returns the number of bytes received if the communication succeeded, but
67 * that doesn't mean the EC was happy with the command. The caller
68 * should check msg.result for the EC's result code.
69 * 65 *
70 * @priv: Private data 66 * @priv: Private data
71 * @irq: Interrupt to use 67 * @irq: Interrupt to use
@@ -82,6 +78,10 @@ struct cros_ec_command {
82 * @dout_size: size of dout buffer to allocate (zero to use static dout) 78 * @dout_size: size of dout buffer to allocate (zero to use static dout)
83 * @parent: pointer to parent device (e.g. i2c or spi device) 79 * @parent: pointer to parent device (e.g. i2c or spi device)
84 * @wake_enabled: true if this device can wake the system from sleep 80 * @wake_enabled: true if this device can wake the system from sleep
81 * @cmd_xfer: send command to EC and get response
82 * Returns the number of bytes received if the communication succeeded, but
83 * that doesn't mean the EC was happy with the command. The caller
84 * should check msg.result for the EC's result code.
85 * @lock: one transaction at a time 85 * @lock: one transaction at a time
86 */ 86 */
87struct cros_ec_device { 87struct cros_ec_device {
@@ -92,8 +92,6 @@ struct cros_ec_device {
92 struct device *dev; 92 struct device *dev;
93 bool was_wake_device; 93 bool was_wake_device;
94 struct class *cros_class; 94 struct class *cros_class;
95 int (*cmd_xfer)(struct cros_ec_device *ec,
96 struct cros_ec_command *msg);
97 95
98 /* These are used to implement the platform-specific interface */ 96 /* These are used to implement the platform-specific interface */
99 void *priv; 97 void *priv;
@@ -104,6 +102,8 @@ struct cros_ec_device {
104 int dout_size; 102 int dout_size;
105 struct device *parent; 103 struct device *parent;
106 bool wake_enabled; 104 bool wake_enabled;
105 int (*cmd_xfer)(struct cros_ec_device *ec,
106 struct cros_ec_command *msg);
107 struct mutex lock; 107 struct mutex lock;
108}; 108};
109 109
@@ -153,6 +153,18 @@ int cros_ec_check_result(struct cros_ec_device *ec_dev,
153 struct cros_ec_command *msg); 153 struct cros_ec_command *msg);
154 154
155/** 155/**
156 * cros_ec_cmd_xfer - Send a command to the ChromeOS EC
157 *
158 * Call this to send a command to the ChromeOS EC. This should be used
159 * instead of calling the EC's cmd_xfer() callback directly.
160 *
161 * @ec_dev: EC device
162 * @msg: Message to write
163 */
164int cros_ec_cmd_xfer(struct cros_ec_device *ec_dev,
165 struct cros_ec_command *msg);
166
167/**
156 * cros_ec_remove - Remove a ChromeOS EC 168 * cros_ec_remove - Remove a ChromeOS EC
157 * 169 *
158 * Call this to deregister a ChromeOS EC, then clean up any private data. 170 * Call this to deregister a ChromeOS EC, then clean up any private data.
diff --git a/include/linux/mfd/da9052/da9052.h b/include/linux/mfd/da9052/da9052.h
index bba65f51a0b5..c18a4c19d6fc 100644
--- a/include/linux/mfd/da9052/da9052.h
+++ b/include/linux/mfd/da9052/da9052.h
@@ -211,7 +211,7 @@ static inline int da9052_reg_update(struct da9052 *da9052, unsigned char reg,
211int da9052_device_init(struct da9052 *da9052, u8 chip_id); 211int da9052_device_init(struct da9052 *da9052, u8 chip_id);
212void da9052_device_exit(struct da9052 *da9052); 212void da9052_device_exit(struct da9052 *da9052);
213 213
214extern struct regmap_config da9052_regmap_config; 214extern const struct regmap_config da9052_regmap_config;
215 215
216int da9052_irq_init(struct da9052 *da9052); 216int da9052_irq_init(struct da9052 *da9052);
217int da9052_irq_exit(struct da9052 *da9052); 217int da9052_irq_exit(struct da9052 *da9052);
diff --git a/include/linux/mfd/davinci_voicecodec.h b/include/linux/mfd/davinci_voicecodec.h
index 5166935ce66d..cb01496bfa49 100644
--- a/include/linux/mfd/davinci_voicecodec.h
+++ b/include/linux/mfd/davinci_voicecodec.h
@@ -21,7 +21,7 @@
21 */ 21 */
22 22
23#ifndef __LINUX_MFD_DAVINCI_VOICECODEC_H_ 23#ifndef __LINUX_MFD_DAVINCI_VOICECODEC_H_
24#define __LINUX_MFD_DAVINIC_VOICECODEC_H_ 24#define __LINUX_MFD_DAVINCI_VOICECODEC_H_
25 25
26#include <linux/kernel.h> 26#include <linux/kernel.h>
27#include <linux/platform_device.h> 27#include <linux/platform_device.h>
diff --git a/include/linux/mfd/hi6421-pmic.h b/include/linux/mfd/hi6421-pmic.h
new file mode 100644
index 000000000000..587273e35acf
--- /dev/null
+++ b/include/linux/mfd/hi6421-pmic.h
@@ -0,0 +1,41 @@
1/*
2 * Header file for device driver Hi6421 PMIC
3 *
4 * Copyright (c) <2011-2014> HiSilicon Technologies Co., Ltd.
5 * http://www.hisilicon.com
6 * Copyright (c) <2013-2014> Linaro Ltd.
7 * http://www.linaro.org
8 *
9 * Author: Guodong Xu <guodong.xu@linaro.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#ifndef __HI6421_PMIC_H
17#define __HI6421_PMIC_H
18
19/* Hi6421 registers are mapped to memory bus in 4 bytes stride */
20#define HI6421_REG_TO_BUS_ADDR(x) (x << 2)
21
22/* Hi6421 maximum register number */
23#define HI6421_REG_MAX 0xFF
24
25/* Hi6421 OCP (over current protection) and DEB (debounce) control register */
26#define HI6421_OCP_DEB_CTRL_REG HI6421_REG_TO_BUS_ADDR(0x51)
27#define HI6421_OCP_DEB_SEL_MASK 0x0C
28#define HI6421_OCP_DEB_SEL_8MS 0x00
29#define HI6421_OCP_DEB_SEL_16MS 0x04
30#define HI6421_OCP_DEB_SEL_32MS 0x08
31#define HI6421_OCP_DEB_SEL_64MS 0x0C
32#define HI6421_OCP_EN_DEBOUNCE_MASK 0x02
33#define HI6421_OCP_EN_DEBOUNCE_ENABLE 0x02
34#define HI6421_OCP_AUTO_STOP_MASK 0x01
35#define HI6421_OCP_AUTO_STOP_ENABLE 0x01
36
37struct hi6421_pmic {
38 struct regmap *regmap;
39};
40
41#endif /* __HI6421_PMIC_H */
diff --git a/include/linux/mfd/max77693-private.h b/include/linux/mfd/max77693-private.h
index d0e578fd7053..fc17d56581b2 100644
--- a/include/linux/mfd/max77693-private.h
+++ b/include/linux/mfd/max77693-private.h
@@ -46,7 +46,7 @@ enum max77693_pmic_reg {
46 MAX77693_LED_REG_VOUT_FLASH2 = 0x0C, 46 MAX77693_LED_REG_VOUT_FLASH2 = 0x0C,
47 MAX77693_LED_REG_FLASH_INT = 0x0E, 47 MAX77693_LED_REG_FLASH_INT = 0x0E,
48 MAX77693_LED_REG_FLASH_INT_MASK = 0x0F, 48 MAX77693_LED_REG_FLASH_INT_MASK = 0x0F,
49 MAX77693_LED_REG_FLASH_INT_STATUS = 0x10, 49 MAX77693_LED_REG_FLASH_STATUS = 0x10,
50 50
51 MAX77693_PMIC_REG_PMIC_ID1 = 0x20, 51 MAX77693_PMIC_REG_PMIC_ID1 = 0x20,
52 MAX77693_PMIC_REG_PMIC_ID2 = 0x21, 52 MAX77693_PMIC_REG_PMIC_ID2 = 0x21,
@@ -85,6 +85,65 @@ enum max77693_pmic_reg {
85 MAX77693_PMIC_REG_END, 85 MAX77693_PMIC_REG_END,
86}; 86};
87 87
88/* MAX77693 ITORCH register */
89#define TORCH_IOUT1_SHIFT 0
90#define TORCH_IOUT2_SHIFT 4
91#define TORCH_IOUT_MIN 15625
92#define TORCH_IOUT_MAX 250000
93#define TORCH_IOUT_STEP 15625
94
95/* MAX77693 IFLASH1 and IFLASH2 registers */
96#define FLASH_IOUT_MIN 15625
97#define FLASH_IOUT_MAX_1LED 1000000
98#define FLASH_IOUT_MAX_2LEDS 625000
99#define FLASH_IOUT_STEP 15625
100
101/* MAX77693 TORCH_TIMER register */
102#define TORCH_TMR_NO_TIMER 0x40
103#define TORCH_TIMEOUT_MIN 262000
104#define TORCH_TIMEOUT_MAX 15728000
105
106/* MAX77693 FLASH_TIMER register */
107#define FLASH_TMR_LEVEL 0x80
108#define FLASH_TIMEOUT_MIN 62500
109#define FLASH_TIMEOUT_MAX 1000000
110#define FLASH_TIMEOUT_STEP 62500
111
112/* MAX77693 FLASH_EN register */
113#define FLASH_EN_OFF 0x0
114#define FLASH_EN_FLASH 0x1
115#define FLASH_EN_TORCH 0x2
116#define FLASH_EN_ON 0x3
117#define FLASH_EN_SHIFT(x) (6 - ((x) - 1) * 2)
118#define TORCH_EN_SHIFT(x) (2 - ((x) - 1) * 2)
119
120/* MAX77693 MAX_FLASH1 register */
121#define MAX_FLASH1_MAX_FL_EN 0x80
122#define MAX_FLASH1_VSYS_MIN 2400
123#define MAX_FLASH1_VSYS_MAX 3400
124#define MAX_FLASH1_VSYS_STEP 33
125
126/* MAX77693 VOUT_CNTL register */
127#define FLASH_BOOST_FIXED 0x04
128#define FLASH_BOOST_LEDNUM_2 0x80
129
130/* MAX77693 VOUT_FLASH1 register */
131#define FLASH_VOUT_MIN 3300
132#define FLASH_VOUT_MAX 5500
133#define FLASH_VOUT_STEP 25
134#define FLASH_VOUT_RMIN 0x0c
135
136/* MAX77693 FLASH_STATUS register */
137#define FLASH_STATUS_FLASH_ON BIT(3)
138#define FLASH_STATUS_TORCH_ON BIT(2)
139
140/* MAX77693 FLASH_INT register */
141#define FLASH_INT_FLED2_OPEN BIT(0)
142#define FLASH_INT_FLED2_SHORT BIT(1)
143#define FLASH_INT_FLED1_OPEN BIT(2)
144#define FLASH_INT_FLED1_SHORT BIT(3)
145#define FLASH_INT_OVER_CURRENT BIT(4)
146
88/* MAX77693 CHG_CNFG_00 register */ 147/* MAX77693 CHG_CNFG_00 register */
89#define CHG_CNFG_00_CHG_MASK 0x1 148#define CHG_CNFG_00_CHG_MASK 0x1
90#define CHG_CNFG_00_BUCK_MASK 0x4 149#define CHG_CNFG_00_BUCK_MASK 0x4
diff --git a/include/linux/mfd/max77693.h b/include/linux/mfd/max77693.h
index 3f3dc45f93ee..f0b6585cd874 100644
--- a/include/linux/mfd/max77693.h
+++ b/include/linux/mfd/max77693.h
@@ -63,6 +63,45 @@ struct max77693_muic_platform_data {
63 int path_uart; 63 int path_uart;
64}; 64};
65 65
66/* MAX77693 led flash */
67
68/* triggers */
69enum max77693_led_trigger {
70 MAX77693_LED_TRIG_OFF,
71 MAX77693_LED_TRIG_FLASH,
72 MAX77693_LED_TRIG_TORCH,
73 MAX77693_LED_TRIG_EXT,
74 MAX77693_LED_TRIG_SOFT,
75};
76
77/* trigger types */
78enum max77693_led_trigger_type {
79 MAX77693_LED_TRIG_TYPE_EDGE,
80 MAX77693_LED_TRIG_TYPE_LEVEL,
81};
82
83/* boost modes */
84enum max77693_led_boost_mode {
85 MAX77693_LED_BOOST_NONE,
86 MAX77693_LED_BOOST_ADAPTIVE,
87 MAX77693_LED_BOOST_FIXED,
88};
89
90struct max77693_led_platform_data {
91 u32 fleds[2];
92 u32 iout_torch[2];
93 u32 iout_flash[2];
94 u32 trigger[2];
95 u32 trigger_type[2];
96 u32 num_leds;
97 u32 boost_mode;
98 u32 flash_timeout;
99 u32 boost_vout;
100 u32 low_vsys;
101};
102
103/* MAX77693 */
104
66struct max77693_platform_data { 105struct max77693_platform_data {
67 /* regulator data */ 106 /* regulator data */
68 struct max77693_regulator_data *regulators; 107 struct max77693_regulator_data *regulators;
@@ -70,5 +109,6 @@ struct max77693_platform_data {
70 109
71 /* muic data */ 110 /* muic data */
72 struct max77693_muic_platform_data *muic_data; 111 struct max77693_muic_platform_data *muic_data;
112 struct max77693_led_platform_data *led_data;
73}; 113};
74#endif /* __LINUX_MFD_MAX77693_H */ 114#endif /* __LINUX_MFD_MAX77693_H */
diff --git a/include/linux/mfd/rk808.h b/include/linux/mfd/rk808.h
new file mode 100644
index 000000000000..fb09312d854b
--- /dev/null
+++ b/include/linux/mfd/rk808.h
@@ -0,0 +1,196 @@
1/*
2 * rk808.h for Rockchip RK808
3 *
4 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
5 *
6 * Author: Chris Zhong <zyw@rock-chips.com>
7 * Author: Zhang Qing <zhangqing@rock-chips.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 */
18
19#ifndef __LINUX_REGULATOR_rk808_H
20#define __LINUX_REGULATOR_rk808_H
21
22#include <linux/regulator/machine.h>
23#include <linux/regmap.h>
24
25/*
26 * rk808 Global Register Map.
27 */
28
29#define RK808_DCDC1 0 /* (0+RK808_START) */
30#define RK808_LDO1 4 /* (4+RK808_START) */
31#define RK808_NUM_REGULATORS 14
32
33enum rk808_reg {
34 RK808_ID_DCDC1,
35 RK808_ID_DCDC2,
36 RK808_ID_DCDC3,
37 RK808_ID_DCDC4,
38 RK808_ID_LDO1,
39 RK808_ID_LDO2,
40 RK808_ID_LDO3,
41 RK808_ID_LDO4,
42 RK808_ID_LDO5,
43 RK808_ID_LDO6,
44 RK808_ID_LDO7,
45 RK808_ID_LDO8,
46 RK808_ID_SWITCH1,
47 RK808_ID_SWITCH2,
48};
49
50#define RK808_SECONDS_REG 0x00
51#define RK808_MINUTES_REG 0x01
52#define RK808_HOURS_REG 0x02
53#define RK808_DAYS_REG 0x03
54#define RK808_MONTHS_REG 0x04
55#define RK808_YEARS_REG 0x05
56#define RK808_WEEKS_REG 0x06
57#define RK808_ALARM_SECONDS_REG 0x08
58#define RK808_ALARM_MINUTES_REG 0x09
59#define RK808_ALARM_HOURS_REG 0x0a
60#define RK808_ALARM_DAYS_REG 0x0b
61#define RK808_ALARM_MONTHS_REG 0x0c
62#define RK808_ALARM_YEARS_REG 0x0d
63#define RK808_RTC_CTRL_REG 0x10
64#define RK808_RTC_STATUS_REG 0x11
65#define RK808_RTC_INT_REG 0x12
66#define RK808_RTC_COMP_LSB_REG 0x13
67#define RK808_RTC_COMP_MSB_REG 0x14
68#define RK808_CLK32OUT_REG 0x20
69#define RK808_VB_MON_REG 0x21
70#define RK808_THERMAL_REG 0x22
71#define RK808_DCDC_EN_REG 0x23
72#define RK808_LDO_EN_REG 0x24
73#define RK808_SLEEP_SET_OFF_REG1 0x25
74#define RK808_SLEEP_SET_OFF_REG2 0x26
75#define RK808_DCDC_UV_STS_REG 0x27
76#define RK808_DCDC_UV_ACT_REG 0x28
77#define RK808_LDO_UV_STS_REG 0x29
78#define RK808_LDO_UV_ACT_REG 0x2a
79#define RK808_DCDC_PG_REG 0x2b
80#define RK808_LDO_PG_REG 0x2c
81#define RK808_VOUT_MON_TDB_REG 0x2d
82#define RK808_BUCK1_CONFIG_REG 0x2e
83#define RK808_BUCK1_ON_VSEL_REG 0x2f
84#define RK808_BUCK1_SLP_VSEL_REG 0x30
85#define RK808_BUCK1_DVS_VSEL_REG 0x31
86#define RK808_BUCK2_CONFIG_REG 0x32
87#define RK808_BUCK2_ON_VSEL_REG 0x33
88#define RK808_BUCK2_SLP_VSEL_REG 0x34
89#define RK808_BUCK2_DVS_VSEL_REG 0x35
90#define RK808_BUCK3_CONFIG_REG 0x36
91#define RK808_BUCK4_CONFIG_REG 0x37
92#define RK808_BUCK4_ON_VSEL_REG 0x38
93#define RK808_BUCK4_SLP_VSEL_REG 0x39
94#define RK808_BOOST_CONFIG_REG 0x3a
95#define RK808_LDO1_ON_VSEL_REG 0x3b
96#define RK808_LDO1_SLP_VSEL_REG 0x3c
97#define RK808_LDO2_ON_VSEL_REG 0x3d
98#define RK808_LDO2_SLP_VSEL_REG 0x3e
99#define RK808_LDO3_ON_VSEL_REG 0x3f
100#define RK808_LDO3_SLP_VSEL_REG 0x40
101#define RK808_LDO4_ON_VSEL_REG 0x41
102#define RK808_LDO4_SLP_VSEL_REG 0x42
103#define RK808_LDO5_ON_VSEL_REG 0x43
104#define RK808_LDO5_SLP_VSEL_REG 0x44
105#define RK808_LDO6_ON_VSEL_REG 0x45
106#define RK808_LDO6_SLP_VSEL_REG 0x46
107#define RK808_LDO7_ON_VSEL_REG 0x47
108#define RK808_LDO7_SLP_VSEL_REG 0x48
109#define RK808_LDO8_ON_VSEL_REG 0x49
110#define RK808_LDO8_SLP_VSEL_REG 0x4a
111#define RK808_DEVCTRL_REG 0x4b
112#define RK808_INT_STS_REG1 0x4c
113#define RK808_INT_STS_MSK_REG1 0x4d
114#define RK808_INT_STS_REG2 0x4e
115#define RK808_INT_STS_MSK_REG2 0x4f
116#define RK808_IO_POL_REG 0x50
117
118/* IRQ Definitions */
119#define RK808_IRQ_VOUT_LO 0
120#define RK808_IRQ_VB_LO 1
121#define RK808_IRQ_PWRON 2
122#define RK808_IRQ_PWRON_LP 3
123#define RK808_IRQ_HOTDIE 4
124#define RK808_IRQ_RTC_ALARM 5
125#define RK808_IRQ_RTC_PERIOD 6
126#define RK808_IRQ_PLUG_IN_INT 7
127#define RK808_IRQ_PLUG_OUT_INT 8
128#define RK808_NUM_IRQ 9
129
130#define RK808_IRQ_VOUT_LO_MSK BIT(0)
131#define RK808_IRQ_VB_LO_MSK BIT(1)
132#define RK808_IRQ_PWRON_MSK BIT(2)
133#define RK808_IRQ_PWRON_LP_MSK BIT(3)
134#define RK808_IRQ_HOTDIE_MSK BIT(4)
135#define RK808_IRQ_RTC_ALARM_MSK BIT(5)
136#define RK808_IRQ_RTC_PERIOD_MSK BIT(6)
137#define RK808_IRQ_PLUG_IN_INT_MSK BIT(0)
138#define RK808_IRQ_PLUG_OUT_INT_MSK BIT(1)
139
140#define RK808_VBAT_LOW_2V8 0x00
141#define RK808_VBAT_LOW_2V9 0x01
142#define RK808_VBAT_LOW_3V0 0x02
143#define RK808_VBAT_LOW_3V1 0x03
144#define RK808_VBAT_LOW_3V2 0x04
145#define RK808_VBAT_LOW_3V3 0x05
146#define RK808_VBAT_LOW_3V4 0x06
147#define RK808_VBAT_LOW_3V5 0x07
148#define VBAT_LOW_VOL_MASK (0x07 << 0)
149#define EN_VABT_LOW_SHUT_DOWN (0x00 << 4)
150#define EN_VBAT_LOW_IRQ (0x1 << 4)
151#define VBAT_LOW_ACT_MASK (0x1 << 4)
152
153#define BUCK_ILMIN_MASK (7 << 0)
154#define BOOST_ILMIN_MASK (7 << 0)
155#define BUCK1_RATE_MASK (3 << 3)
156#define BUCK2_RATE_MASK (3 << 3)
157#define MASK_ALL 0xff
158
159#define SWITCH2_EN BIT(6)
160#define SWITCH1_EN BIT(5)
161#define DEV_OFF_RST BIT(3)
162
163#define VB_LO_ACT BIT(4)
164#define VB_LO_SEL_3500MV (7 << 0)
165
166#define VOUT_LO_INT BIT(0)
167#define CLK32KOUT2_EN BIT(0)
168
169enum {
170 BUCK_ILMIN_50MA,
171 BUCK_ILMIN_100MA,
172 BUCK_ILMIN_150MA,
173 BUCK_ILMIN_200MA,
174 BUCK_ILMIN_250MA,
175 BUCK_ILMIN_300MA,
176 BUCK_ILMIN_350MA,
177 BUCK_ILMIN_400MA,
178};
179
180enum {
181 BOOST_ILMIN_75MA,
182 BOOST_ILMIN_100MA,
183 BOOST_ILMIN_125MA,
184 BOOST_ILMIN_150MA,
185 BOOST_ILMIN_175MA,
186 BOOST_ILMIN_200MA,
187 BOOST_ILMIN_225MA,
188 BOOST_ILMIN_250MA,
189};
190
191struct rk808 {
192 struct i2c_client *i2c;
193 struct regmap_irq_chip_data *irq_data;
194 struct regmap *regmap;
195};
196#endif /* __LINUX_REGULATOR_rk808_H */
diff --git a/include/linux/mfd/rn5t618.h b/include/linux/mfd/rn5t618.h
new file mode 100644
index 000000000000..c72d5344f3b3
--- /dev/null
+++ b/include/linux/mfd/rn5t618.h
@@ -0,0 +1,228 @@
1/*
2 * MFD core driver for Ricoh RN5T618 PMIC
3 *
4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * You should have received a copy of the GNU General Public License
11 * along with this program. If not, see <http://www.gnu.org/licenses/>.
12 */
13
14#ifndef __LINUX_MFD_RN5T618_H
15#define __LINUX_MFD_RN5T618_H
16
17#include <linux/regmap.h>
18
19#define RN5T618_LSIVER 0x00
20#define RN5T618_OTPVER 0x01
21#define RN5T618_IODAC 0x02
22#define RN5T618_VINDAC 0x03
23#define RN5T618_CPUCNT 0x06
24#define RN5T618_PSWR 0x07
25#define RN5T618_PONHIS 0x09
26#define RN5T618_POFFHIS 0x0a
27#define RN5T618_WATCHDOG 0x0b
28#define RN5T618_WATCHDOGCNT 0x0c
29#define RN5T618_PWRFUNC 0x0d
30#define RN5T618_SLPCNT 0x0e
31#define RN5T618_REPCNT 0x0f
32#define RN5T618_PWRONTIMSET 0x10
33#define RN5T618_NOETIMSETCNT 0x11
34#define RN5T618_PWRIREN 0x12
35#define RN5T618_PWRIRQ 0x13
36#define RN5T618_PWRMON 0x14
37#define RN5T618_PWRIRSEL 0x15
38#define RN5T618_DC1_SLOT 0x16
39#define RN5T618_DC2_SLOT 0x17
40#define RN5T618_DC3_SLOT 0x18
41#define RN5T618_LDO1_SLOT 0x1b
42#define RN5T618_LDO2_SLOT 0x1c
43#define RN5T618_LDO3_SLOT 0x1d
44#define RN5T618_LDO4_SLOT 0x1e
45#define RN5T618_LDO5_SLOT 0x1f
46#define RN5T618_PSO0_SLOT 0x25
47#define RN5T618_PSO1_SLOT 0x26
48#define RN5T618_PSO2_SLOT 0x27
49#define RN5T618_PSO3_SLOT 0x28
50#define RN5T618_LDORTC1_SLOT 0x2a
51#define RN5T618_DC1CTL 0x2c
52#define RN5T618_DC1CTL2 0x2d
53#define RN5T618_DC2CTL 0x2e
54#define RN5T618_DC2CTL2 0x2f
55#define RN5T618_DC3CTL 0x30
56#define RN5T618_DC3CTL2 0x31
57#define RN5T618_DC1DAC 0x36
58#define RN5T618_DC2DAC 0x37
59#define RN5T618_DC3DAC 0x38
60#define RN5T618_DC1DAC_SLP 0x3b
61#define RN5T618_DC2DAC_SLP 0x3c
62#define RN5T618_DC3DAC_SLP 0x3d
63#define RN5T618_DCIREN 0x40
64#define RN5T618_DCIRQ 0x41
65#define RN5T618_DCIRMON 0x42
66#define RN5T618_LDOEN1 0x44
67#define RN5T618_LDOEN2 0x45
68#define RN5T618_LDODIS 0x46
69#define RN5T618_LDO1DAC 0x4c
70#define RN5T618_LDO2DAC 0x4d
71#define RN5T618_LDO3DAC 0x4e
72#define RN5T618_LDO4DAC 0x4f
73#define RN5T618_LDO5DAC 0x50
74#define RN5T618_LDORTCDAC 0x56
75#define RN5T618_LDORTC2DAC 0x57
76#define RN5T618_LDO1DAC_SLP 0x58
77#define RN5T618_LDO2DAC_SLP 0x59
78#define RN5T618_LDO3DAC_SLP 0x5a
79#define RN5T618_LDO4DAC_SLP 0x5b
80#define RN5T618_LDO5DAC_SLP 0x5c
81#define RN5T618_ADCCNT1 0x64
82#define RN5T618_ADCCNT2 0x65
83#define RN5T618_ADCCNT3 0x66
84#define RN5T618_ILIMDATAH 0x68
85#define RN5T618_ILIMDATAL 0x69
86#define RN5T618_VBATDATAH 0x6a
87#define RN5T618_VBATDATAL 0x6b
88#define RN5T618_VADPDATAH 0x6c
89#define RN5T618_VADPDATAL 0x6d
90#define RN5T618_VUSBDATAH 0x6e
91#define RN5T618_VUSBDATAL 0x6f
92#define RN5T618_VSYSDATAH 0x70
93#define RN5T618_VSYSDATAL 0x71
94#define RN5T618_VTHMDATAH 0x72
95#define RN5T618_VTHMDATAL 0x73
96#define RN5T618_AIN1DATAH 0x74
97#define RN5T618_AIN1DATAL 0x75
98#define RN5T618_AIN0DATAH 0x76
99#define RN5T618_AIN0DATAL 0x77
100#define RN5T618_ILIMTHL 0x78
101#define RN5T618_ILIMTHH 0x79
102#define RN5T618_VBATTHL 0x7a
103#define RN5T618_VBATTHH 0x7b
104#define RN5T618_VADPTHL 0x7c
105#define RN5T618_VADPTHH 0x7d
106#define RN5T618_VUSBTHL 0x7e
107#define RN5T618_VUSBTHH 0x7f
108#define RN5T618_VSYSTHL 0x80
109#define RN5T618_VSYSTHH 0x81
110#define RN5T618_VTHMTHL 0x82
111#define RN5T618_VTHMTHH 0x83
112#define RN5T618_AIN1THL 0x84
113#define RN5T618_AIN1THH 0x85
114#define RN5T618_AIN0THL 0x86
115#define RN5T618_AIN0THH 0x87
116#define RN5T618_EN_ADCIR1 0x88
117#define RN5T618_EN_ADCIR2 0x89
118#define RN5T618_EN_ADCIR3 0x8a
119#define RN5T618_IR_ADC1 0x8c
120#define RN5T618_IR_ADC2 0x8d
121#define RN5T618_IR_ADC3 0x8e
122#define RN5T618_IOSEL 0x90
123#define RN5T618_IOOUT 0x91
124#define RN5T618_GPEDGE1 0x92
125#define RN5T618_GPEDGE2 0x93
126#define RN5T618_EN_GPIR 0x94
127#define RN5T618_IR_GPR 0x95
128#define RN5T618_IR_GPF 0x96
129#define RN5T618_MON_IOIN 0x97
130#define RN5T618_GPLED_FUNC 0x98
131#define RN5T618_INTPOL 0x9c
132#define RN5T618_INTEN 0x9d
133#define RN5T618_INTMON 0x9e
134#define RN5T618_PREVINDAC 0xb0
135#define RN5T618_BATDAC 0xb1
136#define RN5T618_CHGCTL1 0xb3
137#define RN5T618_CHGCTL2 0xb4
138#define RN5T618_VSYSSET 0xb5
139#define RN5T618_REGISET1 0xb6
140#define RN5T618_REGISET2 0xb7
141#define RN5T618_CHGISET 0xb8
142#define RN5T618_TIMSET 0xb9
143#define RN5T618_BATSET1 0xba
144#define RN5T618_BATSET2 0xbb
145#define RN5T618_DIESET 0xbc
146#define RN5T618_CHGSTATE 0xbd
147#define RN5T618_CHGCTRL_IRFMASK 0xbe
148#define RN5T618_CHGSTAT_IRFMASK1 0xbf
149#define RN5T618_CHGSTAT_IRFMASK2 0xc0
150#define RN5T618_CHGERR_IRFMASK 0xc1
151#define RN5T618_CHGCTRL_IRR 0xc2
152#define RN5T618_CHGSTAT_IRR1 0xc3
153#define RN5T618_CHGSTAT_IRR2 0xc4
154#define RN5T618_CHGERR_IRR 0xc5
155#define RN5T618_CHGCTRL_MONI 0xc6
156#define RN5T618_CHGSTAT_MONI1 0xc7
157#define RN5T618_CHGSTAT_MONI2 0xc8
158#define RN5T618_CHGERR_MONI 0xc9
159#define RN5T618_CHGCTRL_DETMOD1 0xca
160#define RN5T618_CHGCTRL_DETMOD2 0xcb
161#define RN5T618_CHGSTAT_DETMOD1 0xcc
162#define RN5T618_CHGSTAT_DETMOD2 0xcd
163#define RN5T618_CHGSTAT_DETMOD3 0xce
164#define RN5T618_CHGERR_DETMOD1 0xcf
165#define RN5T618_CHGERR_DETMOD2 0xd0
166#define RN5T618_CHGOSCCTL 0xd4
167#define RN5T618_CHGOSCSCORESET1 0xd5
168#define RN5T618_CHGOSCSCORESET2 0xd6
169#define RN5T618_CHGOSCSCORESET3 0xd7
170#define RN5T618_CHGOSCFREQSET1 0xd8
171#define RN5T618_CHGOSCFREQSET2 0xd9
172#define RN5T618_CONTROL 0xe0
173#define RN5T618_SOC 0xe1
174#define RN5T618_RE_CAP_H 0xe2
175#define RN5T618_RE_CAP_L 0xe3
176#define RN5T618_FA_CAP_H 0xe4
177#define RN5T618_FA_CAP_L 0xe5
178#define RN5T618_AGE 0xe6
179#define RN5T618_TT_EMPTY_H 0xe7
180#define RN5T618_TT_EMPTY_L 0xe8
181#define RN5T618_TT_FULL_H 0xe9
182#define RN5T618_TT_FULL_L 0xea
183#define RN5T618_VOLTAGE_1 0xeb
184#define RN5T618_VOLTAGE_0 0xec
185#define RN5T618_TEMP_1 0xed
186#define RN5T618_TEMP_0 0xee
187#define RN5T618_CC_CTRL 0xef
188#define RN5T618_CC_COUNT2 0xf0
189#define RN5T618_CC_COUNT1 0xf1
190#define RN5T618_CC_COUNT0 0xf2
191#define RN5T618_CC_SUMREG3 0xf3
192#define RN5T618_CC_SUMREG2 0xf4
193#define RN5T618_CC_SUMREG1 0xf5
194#define RN5T618_CC_SUMREG0 0xf6
195#define RN5T618_CC_OFFREG1 0xf7
196#define RN5T618_CC_OFFREG0 0xf8
197#define RN5T618_CC_GAINREG1 0xf9
198#define RN5T618_CC_GAINREG0 0xfa
199#define RN5T618_CC_AVEREG1 0xfb
200#define RN5T618_CC_AVEREG0 0xfc
201#define RN5T618_MAX_REG 0xfc
202
203#define RN5T618_REPCNT_REPWRON BIT(0)
204#define RN5T618_SLPCNT_SWPWROFF BIT(0)
205#define RN5T618_WATCHDOG_WDOGEN BIT(2)
206#define RN5T618_WATCHDOG_WDOGTIM_M (BIT(0) | BIT(1))
207#define RN5T618_WATCHDOG_WDOGTIM_S 0
208#define RN5T618_PWRIRQ_IR_WDOG BIT(6)
209
210enum {
211 RN5T618_DCDC1,
212 RN5T618_DCDC2,
213 RN5T618_DCDC3,
214 RN5T618_LDO1,
215 RN5T618_LDO2,
216 RN5T618_LDO3,
217 RN5T618_LDO4,
218 RN5T618_LDO5,
219 RN5T618_LDORTC1,
220 RN5T618_LDORTC2,
221 RN5T618_REG_NUM,
222};
223
224struct rn5t618 {
225 struct regmap *regmap;
226};
227
228#endif /* __LINUX_MFD_RN5T618_H */
diff --git a/include/linux/mfd/ti_am335x_tscadc.h b/include/linux/mfd/ti_am335x_tscadc.h
index fb96c84dada5..e2e70053470e 100644
--- a/include/linux/mfd/ti_am335x_tscadc.h
+++ b/include/linux/mfd/ti_am335x_tscadc.h
@@ -155,6 +155,7 @@ struct ti_tscadc_dev {
155 void __iomem *tscadc_base; 155 void __iomem *tscadc_base;
156 int irq; 156 int irq;
157 int used_cells; /* 1-2 */ 157 int used_cells; /* 1-2 */
158 int tsc_wires;
158 int tsc_cell; /* -1 if not used */ 159 int tsc_cell; /* -1 if not used */
159 int adc_cell; /* -1 if not used */ 160 int adc_cell; /* -1 if not used */
160 struct mfd_cell cells[TSCADC_CELLS]; 161 struct mfd_cell cells[TSCADC_CELLS];
diff --git a/include/linux/mfd/ti_ssp.h b/include/linux/mfd/ti_ssp.h
deleted file mode 100644
index dbb4b43bd20e..000000000000
--- a/include/linux/mfd/ti_ssp.h
+++ /dev/null
@@ -1,93 +0,0 @@
1/*
2 * Sequencer Serial Port (SSP) driver for Texas Instruments' SoCs
3 *
4 * Copyright (C) 2010 Texas Instruments Inc
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __TI_SSP_H__
22#define __TI_SSP_H__
23
24struct ti_ssp_dev_data {
25 const char *dev_name;
26 void *pdata;
27 size_t pdata_size;
28};
29
30struct ti_ssp_data {
31 unsigned long out_clock;
32 struct ti_ssp_dev_data dev_data[2];
33};
34
35struct ti_ssp_spi_data {
36 unsigned long iosel;
37 int num_cs;
38 void (*select)(int cs);
39};
40
41/*
42 * Sequencer port IO pin configuration bits. These do not correlate 1-1 with
43 * the hardware. The iosel field in the port data combines iosel1 and iosel2,
44 * and is therefore not a direct map to register space. It is best to use the
45 * macros below to construct iosel values.
46 *
47 * least significant 16 bits --> iosel1
48 * most significant 16 bits --> iosel2
49 */
50
51#define SSP_IN 0x0000
52#define SSP_DATA 0x0001
53#define SSP_CLOCK 0x0002
54#define SSP_CHIPSEL 0x0003
55#define SSP_OUT 0x0004
56#define SSP_PIN_SEL(pin, v) ((v) << ((pin) * 3))
57#define SSP_PIN_MASK(pin) SSP_PIN_SEL(pin, 0x7)
58#define SSP_INPUT_SEL(pin) ((pin) << 16)
59
60/* Sequencer port config bits */
61#define SSP_EARLY_DIN BIT(8)
62#define SSP_DELAY_DOUT BIT(9)
63
64/* Sequence map definitions */
65#define SSP_CLK_HIGH BIT(0)
66#define SSP_CLK_LOW 0
67#define SSP_DATA_HIGH BIT(1)
68#define SSP_DATA_LOW 0
69#define SSP_CS_HIGH BIT(2)
70#define SSP_CS_LOW 0
71#define SSP_OUT_MODE BIT(3)
72#define SSP_IN_MODE 0
73#define SSP_DATA_REG BIT(4)
74#define SSP_ADDR_REG 0
75
76#define SSP_OPCODE_DIRECT ((0x0) << 5)
77#define SSP_OPCODE_TOGGLE ((0x1) << 5)
78#define SSP_OPCODE_SHIFT ((0x2) << 5)
79#define SSP_OPCODE_BRANCH0 ((0x4) << 5)
80#define SSP_OPCODE_BRANCH1 ((0x5) << 5)
81#define SSP_OPCODE_BRANCH ((0x6) << 5)
82#define SSP_OPCODE_STOP ((0x7) << 5)
83#define SSP_BRANCH(addr) ((addr) << 8)
84#define SSP_COUNT(cycles) ((cycles) << 8)
85
86int ti_ssp_raw_read(struct device *dev);
87int ti_ssp_raw_write(struct device *dev, u32 val);
88int ti_ssp_load(struct device *dev, int offs, u32* prog, int len);
89int ti_ssp_run(struct device *dev, u32 pc, u32 input, u32 *output);
90int ti_ssp_set_mode(struct device *dev, int mode);
91int ti_ssp_set_iosel(struct device *dev, u32 iosel);
92
93#endif /* __TI_SSP_H__ */
diff --git a/include/linux/mfd/tps65217.h b/include/linux/mfd/tps65217.h
index 95d6938737fd..ac7fba44d7e4 100644
--- a/include/linux/mfd/tps65217.h
+++ b/include/linux/mfd/tps65217.h
@@ -60,6 +60,8 @@
60#define TPS65217_REG_SEQ5 0X1D 60#define TPS65217_REG_SEQ5 0X1D
61#define TPS65217_REG_SEQ6 0X1E 61#define TPS65217_REG_SEQ6 0X1E
62 62
63#define TPS65217_REG_MAX TPS65217_REG_SEQ6
64
63/* Register field definitions */ 65/* Register field definitions */
64#define TPS65217_CHIPID_CHIP_MASK 0xF0 66#define TPS65217_CHIPID_CHIP_MASK 0xF0
65#define TPS65217_CHIPID_REV_MASK 0x0F 67#define TPS65217_CHIPID_REV_MASK 0x0F
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-06 19:00:21 -0400