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authorEric Paris <eparis@redhat.com>2013-11-22 18:57:08 -0500
committerEric Paris <eparis@redhat.com>2013-11-22 18:57:54 -0500
commitfc582aef7dcc27a7120cf232c1e76c569c7b6eab (patch)
tree7d275dd4ceab6067b91e9a25a5f6338b425fbccd /include/linux/mfd
parent9175c9d2aed528800175ef81c90569d00d23f9be (diff)
parent5e01dc7b26d9f24f39abace5da98ccbd6a5ceb52 (diff)
Merge tag 'v3.12'
Linux 3.12 Conflicts: fs/exec.c
Diffstat (limited to 'include/linux/mfd')
-rw-r--r--include/linux/mfd/arizona/gpio.h96
-rw-r--r--include/linux/mfd/da9063/core.h93
-rw-r--r--include/linux/mfd/da9063/pdata.h111
-rw-r--r--include/linux/mfd/da9063/registers.h1028
-rw-r--r--include/linux/mfd/davinci_voicecodec.h3
-rw-r--r--include/linux/mfd/mcp.h2
-rw-r--r--include/linux/mfd/palmas.h102
-rw-r--r--include/linux/mfd/rtsx_common.h3
-rw-r--r--include/linux/mfd/rtsx_pci.h66
-rw-r--r--include/linux/mfd/samsung/s2mps11.h17
-rw-r--r--include/linux/mfd/ti_am335x_tscadc.h1
-rw-r--r--include/linux/mfd/tmio.h1
-rw-r--r--include/linux/mfd/tps65217.h19
-rw-r--r--include/linux/mfd/twl6040.h2
-rw-r--r--include/linux/mfd/ucb1x00.h1
15 files changed, 1491 insertions, 54 deletions
diff --git a/include/linux/mfd/arizona/gpio.h b/include/linux/mfd/arizona/gpio.h
new file mode 100644
index 000000000000..d2146bb74f89
--- /dev/null
+++ b/include/linux/mfd/arizona/gpio.h
@@ -0,0 +1,96 @@
1/*
2 * GPIO configuration for Arizona devices
3 *
4 * Copyright 2013 Wolfson Microelectronics. PLC.
5 *
6 * Author: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef _ARIZONA_GPIO_H
14#define _ARIZONA_GPIO_H
15
16#define ARIZONA_GP_FN_TXLRCLK 0x00
17#define ARIZONA_GP_FN_GPIO 0x01
18#define ARIZONA_GP_FN_IRQ1 0x02
19#define ARIZONA_GP_FN_IRQ2 0x03
20#define ARIZONA_GP_FN_OPCLK 0x04
21#define ARIZONA_GP_FN_FLL1_OUT 0x05
22#define ARIZONA_GP_FN_FLL2_OUT 0x06
23#define ARIZONA_GP_FN_PWM1 0x08
24#define ARIZONA_GP_FN_PWM2 0x09
25#define ARIZONA_GP_FN_SYSCLK_UNDERCLOCKED 0x0A
26#define ARIZONA_GP_FN_ASYNCCLK_UNDERCLOCKED 0x0B
27#define ARIZONA_GP_FN_FLL1_LOCK 0x0C
28#define ARIZONA_GP_FN_FLL2_LOCK 0x0D
29#define ARIZONA_GP_FN_FLL1_CLOCK_OK 0x0F
30#define ARIZONA_GP_FN_FLL2_CLOCK_OK 0x10
31#define ARIZONA_GP_FN_HEADPHONE_DET 0x12
32#define ARIZONA_GP_FN_MIC_DET 0x13
33#define ARIZONA_GP_FN_WSEQ_STATUS 0x15
34#define ARIZONA_GP_FN_CIF_ADDRESS_ERROR 0x16
35#define ARIZONA_GP_FN_ASRC1_LOCK 0x1A
36#define ARIZONA_GP_FN_ASRC2_LOCK 0x1B
37#define ARIZONA_GP_FN_ASRC_CONFIG_ERROR 0x1C
38#define ARIZONA_GP_FN_DRC1_SIGNAL_DETECT 0x1D
39#define ARIZONA_GP_FN_DRC1_ANTICLIP 0x1E
40#define ARIZONA_GP_FN_DRC1_DECAY 0x1F
41#define ARIZONA_GP_FN_DRC1_NOISE 0x20
42#define ARIZONA_GP_FN_DRC1_QUICK_RELEASE 0x21
43#define ARIZONA_GP_FN_DRC2_SIGNAL_DETECT 0x22
44#define ARIZONA_GP_FN_DRC2_ANTICLIP 0x23
45#define ARIZONA_GP_FN_DRC2_DECAY 0x24
46#define ARIZONA_GP_FN_DRC2_NOISE 0x25
47#define ARIZONA_GP_FN_DRC2_QUICK_RELEASE 0x26
48#define ARIZONA_GP_FN_MIXER_DROPPED_SAMPLE 0x27
49#define ARIZONA_GP_FN_AIF1_CONFIG_ERROR 0x28
50#define ARIZONA_GP_FN_AIF2_CONFIG_ERROR 0x29
51#define ARIZONA_GP_FN_AIF3_CONFIG_ERROR 0x2A
52#define ARIZONA_GP_FN_SPK_TEMP_SHUTDOWN 0x2B
53#define ARIZONA_GP_FN_SPK_TEMP_WARNING 0x2C
54#define ARIZONA_GP_FN_UNDERCLOCKED 0x2D
55#define ARIZONA_GP_FN_OVERCLOCKED 0x2E
56#define ARIZONA_GP_FN_DSP_IRQ1 0x35
57#define ARIZONA_GP_FN_DSP_IRQ2 0x36
58#define ARIZONA_GP_FN_ASYNC_OPCLK 0x3D
59#define ARIZONA_GP_FN_BOOT_DONE 0x44
60#define ARIZONA_GP_FN_DSP1_RAM_READY 0x45
61#define ARIZONA_GP_FN_SYSCLK_ENA_STATUS 0x4B
62#define ARIZONA_GP_FN_ASYNCCLK_ENA_STATUS 0x4C
63
64#define ARIZONA_GPN_DIR 0x8000 /* GPN_DIR */
65#define ARIZONA_GPN_DIR_MASK 0x8000 /* GPN_DIR */
66#define ARIZONA_GPN_DIR_SHIFT 15 /* GPN_DIR */
67#define ARIZONA_GPN_DIR_WIDTH 1 /* GPN_DIR */
68#define ARIZONA_GPN_PU 0x4000 /* GPN_PU */
69#define ARIZONA_GPN_PU_MASK 0x4000 /* GPN_PU */
70#define ARIZONA_GPN_PU_SHIFT 14 /* GPN_PU */
71#define ARIZONA_GPN_PU_WIDTH 1 /* GPN_PU */
72#define ARIZONA_GPN_PD 0x2000 /* GPN_PD */
73#define ARIZONA_GPN_PD_MASK 0x2000 /* GPN_PD */
74#define ARIZONA_GPN_PD_SHIFT 13 /* GPN_PD */
75#define ARIZONA_GPN_PD_WIDTH 1 /* GPN_PD */
76#define ARIZONA_GPN_LVL 0x0800 /* GPN_LVL */
77#define ARIZONA_GPN_LVL_MASK 0x0800 /* GPN_LVL */
78#define ARIZONA_GPN_LVL_SHIFT 11 /* GPN_LVL */
79#define ARIZONA_GPN_LVL_WIDTH 1 /* GPN_LVL */
80#define ARIZONA_GPN_POL 0x0400 /* GPN_POL */
81#define ARIZONA_GPN_POL_MASK 0x0400 /* GPN_POL */
82#define ARIZONA_GPN_POL_SHIFT 10 /* GPN_POL */
83#define ARIZONA_GPN_POL_WIDTH 1 /* GPN_POL */
84#define ARIZONA_GPN_OP_CFG 0x0200 /* GPN_OP_CFG */
85#define ARIZONA_GPN_OP_CFG_MASK 0x0200 /* GPN_OP_CFG */
86#define ARIZONA_GPN_OP_CFG_SHIFT 9 /* GPN_OP_CFG */
87#define ARIZONA_GPN_OP_CFG_WIDTH 1 /* GPN_OP_CFG */
88#define ARIZONA_GPN_DB 0x0100 /* GPN_DB */
89#define ARIZONA_GPN_DB_MASK 0x0100 /* GPN_DB */
90#define ARIZONA_GPN_DB_SHIFT 8 /* GPN_DB */
91#define ARIZONA_GPN_DB_WIDTH 1 /* GPN_DB */
92#define ARIZONA_GPN_FN_MASK 0x007F /* GPN_DB */
93#define ARIZONA_GPN_FN_SHIFT 0 /* GPN_DB */
94#define ARIZONA_GPN_FN_WIDTH 7 /* GPN_DB */
95
96#endif
diff --git a/include/linux/mfd/da9063/core.h b/include/linux/mfd/da9063/core.h
new file mode 100644
index 000000000000..2d2a0af675fd
--- /dev/null
+++ b/include/linux/mfd/da9063/core.h
@@ -0,0 +1,93 @@
1/*
2 * Definitions for DA9063 MFD driver
3 *
4 * Copyright 2012 Dialog Semiconductor Ltd.
5 *
6 * Author: Michal Hajduk <michal.hajduk@diasemi.com>
7 * Krystian Garbaciak <krystian.garbaciak@diasemi.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#ifndef __MFD_DA9063_CORE_H__
17#define __MFD_DA9063_CORE_H__
18
19#include <linux/interrupt.h>
20#include <linux/mfd/da9063/registers.h>
21
22/* DA9063 modules */
23#define DA9063_DRVNAME_CORE "da9063-core"
24#define DA9063_DRVNAME_REGULATORS "da9063-regulators"
25#define DA9063_DRVNAME_LEDS "da9063-leds"
26#define DA9063_DRVNAME_WATCHDOG "da9063-watchdog"
27#define DA9063_DRVNAME_HWMON "da9063-hwmon"
28#define DA9063_DRVNAME_ONKEY "da9063-onkey"
29#define DA9063_DRVNAME_RTC "da9063-rtc"
30#define DA9063_DRVNAME_VIBRATION "da9063-vibration"
31
32enum da9063_models {
33 PMIC_DA9063 = 0x61,
34};
35
36/* Interrupts */
37enum da9063_irqs {
38 DA9063_IRQ_ONKEY = 0,
39 DA9063_IRQ_ALARM,
40 DA9063_IRQ_TICK,
41 DA9063_IRQ_ADC_RDY,
42 DA9063_IRQ_SEQ_RDY,
43 DA9063_IRQ_WAKE,
44 DA9063_IRQ_TEMP,
45 DA9063_IRQ_COMP_1V2,
46 DA9063_IRQ_LDO_LIM,
47 DA9063_IRQ_REG_UVOV,
48 DA9063_IRQ_VDD_MON,
49 DA9063_IRQ_WARN,
50 DA9063_IRQ_GPI0,
51 DA9063_IRQ_GPI1,
52 DA9063_IRQ_GPI2,
53 DA9063_IRQ_GPI3,
54 DA9063_IRQ_GPI4,
55 DA9063_IRQ_GPI5,
56 DA9063_IRQ_GPI6,
57 DA9063_IRQ_GPI7,
58 DA9063_IRQ_GPI8,
59 DA9063_IRQ_GPI9,
60 DA9063_IRQ_GPI10,
61 DA9063_IRQ_GPI11,
62 DA9063_IRQ_GPI12,
63 DA9063_IRQ_GPI13,
64 DA9063_IRQ_GPI14,
65 DA9063_IRQ_GPI15,
66};
67
68#define DA9063_IRQ_BASE_OFFSET 0
69#define DA9063_NUM_IRQ (DA9063_IRQ_GPI15 + 1 - DA9063_IRQ_BASE_OFFSET)
70
71struct da9063 {
72 /* Device */
73 struct device *dev;
74 unsigned short model;
75 unsigned short revision;
76 unsigned int flags;
77
78 /* Control interface */
79 struct regmap *regmap;
80
81 /* Interrupts */
82 int chip_irq;
83 unsigned int irq_base;
84 struct regmap_irq_chip_data *regmap_irq;
85};
86
87int da9063_device_init(struct da9063 *da9063, unsigned int irq);
88int da9063_irq_init(struct da9063 *da9063);
89
90void da9063_device_exit(struct da9063 *da9063);
91void da9063_irq_exit(struct da9063 *da9063);
92
93#endif /* __MFD_DA9063_CORE_H__ */
diff --git a/include/linux/mfd/da9063/pdata.h b/include/linux/mfd/da9063/pdata.h
new file mode 100644
index 000000000000..95c8742215a7
--- /dev/null
+++ b/include/linux/mfd/da9063/pdata.h
@@ -0,0 +1,111 @@
1/*
2 * Platform configuration options for DA9063
3 *
4 * Copyright 2012 Dialog Semiconductor Ltd.
5 *
6 * Author: Michal Hajduk <michal.hajduk@diasemi.com>
7 * Author: Krystian Garbaciak <krystian.garbaciak@diasemi.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#ifndef __MFD_DA9063_PDATA_H__
17#define __MFD_DA9063_PDATA_H__
18
19#include <linux/regulator/machine.h>
20
21/*
22 * Regulator configuration
23 */
24/* DA9063 regulator IDs */
25enum {
26 /* BUCKs */
27 DA9063_ID_BCORE1,
28 DA9063_ID_BCORE2,
29 DA9063_ID_BPRO,
30 DA9063_ID_BMEM,
31 DA9063_ID_BIO,
32 DA9063_ID_BPERI,
33
34 /* BCORE1 and BCORE2 in merged mode */
35 DA9063_ID_BCORES_MERGED,
36 /* BMEM and BIO in merged mode */
37 DA9063_ID_BMEM_BIO_MERGED,
38 /* When two BUCKs are merged, they cannot be reused separately */
39
40 /* LDOs */
41 DA9063_ID_LDO1,
42 DA9063_ID_LDO2,
43 DA9063_ID_LDO3,
44 DA9063_ID_LDO4,
45 DA9063_ID_LDO5,
46 DA9063_ID_LDO6,
47 DA9063_ID_LDO7,
48 DA9063_ID_LDO8,
49 DA9063_ID_LDO9,
50 DA9063_ID_LDO10,
51 DA9063_ID_LDO11,
52};
53
54/* Regulators platform data */
55struct da9063_regulator_data {
56 int id;
57 struct regulator_init_data *initdata;
58};
59
60struct da9063_regulators_pdata {
61 unsigned n_regulators;
62 struct da9063_regulator_data *regulator_data;
63};
64
65
66/*
67 * RGB LED configuration
68 */
69/* LED IDs for flags in struct led_info. */
70enum {
71 DA9063_GPIO11_LED,
72 DA9063_GPIO14_LED,
73 DA9063_GPIO15_LED,
74
75 DA9063_LED_NUM
76};
77#define DA9063_LED_ID_MASK 0x3
78
79/* LED polarity for flags in struct led_info. */
80#define DA9063_LED_HIGH_LEVEL_ACTIVE 0x0
81#define DA9063_LED_LOW_LEVEL_ACTIVE 0x4
82
83
84/*
85 * General PMIC configuration
86 */
87/* HWMON ADC channels configuration */
88#define DA9063_FLG_FORCE_IN0_MANUAL_MODE 0x0010
89#define DA9063_FLG_FORCE_IN0_AUTO_MODE 0x0020
90#define DA9063_FLG_FORCE_IN1_MANUAL_MODE 0x0040
91#define DA9063_FLG_FORCE_IN1_AUTO_MODE 0x0080
92#define DA9063_FLG_FORCE_IN2_MANUAL_MODE 0x0100
93#define DA9063_FLG_FORCE_IN2_AUTO_MODE 0x0200
94#define DA9063_FLG_FORCE_IN3_MANUAL_MODE 0x0400
95#define DA9063_FLG_FORCE_IN3_AUTO_MODE 0x0800
96
97/* Disable register caching. */
98#define DA9063_FLG_NO_CACHE 0x0008
99
100struct da9063;
101
102/* DA9063 platform data */
103struct da9063_pdata {
104 int (*init)(struct da9063 *da9063);
105 int irq_base;
106 unsigned flags;
107 struct da9063_regulators_pdata *regulators_pdata;
108 struct led_platform_data *leds_pdata;
109};
110
111#endif /* __MFD_DA9063_PDATA_H__ */
diff --git a/include/linux/mfd/da9063/registers.h b/include/linux/mfd/da9063/registers.h
new file mode 100644
index 000000000000..5834813fb5f3
--- /dev/null
+++ b/include/linux/mfd/da9063/registers.h
@@ -0,0 +1,1028 @@
1/*
2 * Registers definition for DA9063 modules
3 *
4 * Copyright 2012 Dialog Semiconductor Ltd.
5 *
6 * Author: Michal Hajduk <michal.hajduk@diasemi.com>
7 * Krystian Garbaciak <krystian.garbaciak@diasemi.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#ifndef _DA9063_REG_H
17#define _DA9063_REG_H
18
19#define DA9063_I2C_PAGE_SEL_SHIFT 1
20
21#define DA9063_EVENT_REG_NUM 4
22#define DA9210_EVENT_REG_NUM 2
23#define DA9063_EXT_EVENT_REG_NUM (DA9063_EVENT_REG_NUM + \
24 DA9210_EVENT_REG_NUM)
25
26/* Page selection I2C or SPI always in the begining of any page. */
27/* Page 0 : I2C access 0x000 - 0x0FF SPI access 0x000 - 0x07F */
28/* Page 1 : SPI access 0x080 - 0x0FF */
29/* Page 2 : I2C access 0x100 - 0x1FF SPI access 0x100 - 0x17F */
30/* Page 3 : SPI access 0x180 - 0x1FF */
31#define DA9063_REG_PAGE_CON 0x00
32
33/* System Control and Event Registers */
34#define DA9063_REG_STATUS_A 0x01
35#define DA9063_REG_STATUS_B 0x02
36#define DA9063_REG_STATUS_C 0x03
37#define DA9063_REG_STATUS_D 0x04
38#define DA9063_REG_FAULT_LOG 0x05
39#define DA9063_REG_EVENT_A 0x06
40#define DA9063_REG_EVENT_B 0x07
41#define DA9063_REG_EVENT_C 0x08
42#define DA9063_REG_EVENT_D 0x09
43#define DA9063_REG_IRQ_MASK_A 0x0A
44#define DA9063_REG_IRQ_MASK_B 0x0B
45#define DA9063_REG_IRQ_MASK_C 0x0C
46#define DA9063_REG_IRQ_MASK_D 0x0D
47#define DA9063_REG_CONTROL_A 0x0E
48#define DA9063_REG_CONTROL_B 0x0F
49#define DA9063_REG_CONTROL_C 0x10
50#define DA9063_REG_CONTROL_D 0x11
51#define DA9063_REG_CONTROL_E 0x12
52#define DA9063_REG_CONTROL_F 0x13
53#define DA9063_REG_PD_DIS 0x14
54
55/* GPIO Control Registers */
56#define DA9063_REG_GPIO_0_1 0x15
57#define DA9063_REG_GPIO_2_3 0x16
58#define DA9063_REG_GPIO_4_5 0x17
59#define DA9063_REG_GPIO_6_7 0x18
60#define DA9063_REG_GPIO_8_9 0x19
61#define DA9063_REG_GPIO_10_11 0x1A
62#define DA9063_REG_GPIO_12_13 0x1B
63#define DA9063_REG_GPIO_14_15 0x1C
64#define DA9063_REG_GPIO_MODE_0_7 0x1D
65#define DA9063_REG_GPIO_MODE_8_15 0x1E
66#define DA9063_REG_GPIO_SWITCH_CONT 0x1F
67
68/* Regulator Control Registers */
69#define DA9063_REG_BCORE2_CONT 0x20
70#define DA9063_REG_BCORE1_CONT 0x21
71#define DA9063_REG_BPRO_CONT 0x22
72#define DA9063_REG_BMEM_CONT 0x23
73#define DA9063_REG_BIO_CONT 0x24
74#define DA9063_REG_BPERI_CONT 0x25
75#define DA9063_REG_LDO1_CONT 0x26
76#define DA9063_REG_LDO2_CONT 0x27
77#define DA9063_REG_LDO3_CONT 0x28
78#define DA9063_REG_LDO4_CONT 0x29
79#define DA9063_REG_LDO5_CONT 0x2A
80#define DA9063_REG_LDO6_CONT 0x2B
81#define DA9063_REG_LDO7_CONT 0x2C
82#define DA9063_REG_LDO8_CONT 0x2D
83#define DA9063_REG_LDO9_CONT 0x2E
84#define DA9063_REG_LDO10_CONT 0x2F
85#define DA9063_REG_LDO11_CONT 0x30
86#define DA9063_REG_VIB 0x31
87#define DA9063_REG_DVC_1 0x32
88#define DA9063_REG_DVC_2 0x33
89
90/* GP-ADC Control Registers */
91#define DA9063_REG_ADC_MAN 0x34
92#define DA9063_REG_ADC_CONT 0x35
93#define DA9063_REG_VSYS_MON 0x36
94#define DA9063_REG_ADC_RES_L 0x37
95#define DA9063_REG_ADC_RES_H 0x38
96#define DA9063_REG_VSYS_RES 0x39
97#define DA9063_REG_ADCIN1_RES 0x3A
98#define DA9063_REG_ADCIN2_RES 0x3B
99#define DA9063_REG_ADCIN3_RES 0x3C
100#define DA9063_REG_MON1_RES 0x3D
101#define DA9063_REG_MON2_RES 0x3E
102#define DA9063_REG_MON3_RES 0x3F
103
104/* RTC Calendar and Alarm Registers */
105#define DA9063_REG_COUNT_S 0x40
106#define DA9063_REG_COUNT_MI 0x41
107#define DA9063_REG_COUNT_H 0x42
108#define DA9063_REG_COUNT_D 0x43
109#define DA9063_REG_COUNT_MO 0x44
110#define DA9063_REG_COUNT_Y 0x45
111#define DA9063_REG_ALARM_MI 0x46
112#define DA9063_REG_ALARM_H 0x47
113#define DA9063_REG_ALARM_D 0x48
114#define DA9063_REG_ALARM_MO 0x49
115#define DA9063_REG_ALARM_Y 0x4A
116#define DA9063_REG_SECOND_A 0x4B
117#define DA9063_REG_SECOND_B 0x4C
118#define DA9063_REG_SECOND_C 0x4D
119#define DA9063_REG_SECOND_D 0x4E
120
121/* Sequencer Control Registers */
122#define DA9063_REG_SEQ 0x81
123#define DA9063_REG_SEQ_TIMER 0x82
124#define DA9063_REG_ID_2_1 0x83
125#define DA9063_REG_ID_4_3 0x84
126#define DA9063_REG_ID_6_5 0x85
127#define DA9063_REG_ID_8_7 0x86
128#define DA9063_REG_ID_10_9 0x87
129#define DA9063_REG_ID_12_11 0x88
130#define DA9063_REG_ID_14_13 0x89
131#define DA9063_REG_ID_16_15 0x8A
132#define DA9063_REG_ID_18_17 0x8B
133#define DA9063_REG_ID_20_19 0x8C
134#define DA9063_REG_ID_22_21 0x8D
135#define DA9063_REG_ID_24_23 0x8E
136#define DA9063_REG_ID_26_25 0x8F
137#define DA9063_REG_ID_28_27 0x90
138#define DA9063_REG_ID_30_29 0x91
139#define DA9063_REG_ID_32_31 0x92
140#define DA9063_REG_SEQ_A 0x95
141#define DA9063_REG_SEQ_B 0x96
142#define DA9063_REG_WAIT 0x97
143#define DA9063_REG_EN_32K 0x98
144#define DA9063_REG_RESET 0x99
145
146/* Regulator Setting Registers */
147#define DA9063_REG_BUCK_ILIM_A 0x9A
148#define DA9063_REG_BUCK_ILIM_B 0x9B
149#define DA9063_REG_BUCK_ILIM_C 0x9C
150#define DA9063_REG_BCORE2_CFG 0x9D
151#define DA9063_REG_BCORE1_CFG 0x9E
152#define DA9063_REG_BPRO_CFG 0x9F
153#define DA9063_REG_BIO_CFG 0xA0
154#define DA9063_REG_BMEM_CFG 0xA1
155#define DA9063_REG_BPERI_CFG 0xA2
156#define DA9063_REG_VBCORE2_A 0xA3
157#define DA9063_REG_VBCORE1_A 0xA4
158#define DA9063_REG_VBPRO_A 0xA5
159#define DA9063_REG_VBMEM_A 0xA6
160#define DA9063_REG_VBIO_A 0xA7
161#define DA9063_REG_VBPERI_A 0xA8
162#define DA9063_REG_VLDO1_A 0xA9
163#define DA9063_REG_VLDO2_A 0xAA
164#define DA9063_REG_VLDO3_A 0xAB
165#define DA9063_REG_VLDO4_A 0xAC
166#define DA9063_REG_VLDO5_A 0xAD
167#define DA9063_REG_VLDO6_A 0xAE
168#define DA9063_REG_VLDO7_A 0xAF
169#define DA9063_REG_VLDO8_A 0xB0
170#define DA9063_REG_VLDO9_A 0xB1
171#define DA9063_REG_VLDO10_A 0xB2
172#define DA9063_REG_VLDO11_A 0xB3
173#define DA9063_REG_VBCORE2_B 0xB4
174#define DA9063_REG_VBCORE1_B 0xB5
175#define DA9063_REG_VBPRO_B 0xB6
176#define DA9063_REG_VBMEM_B 0xB7
177#define DA9063_REG_VBIO_B 0xB8
178#define DA9063_REG_VBPERI_B 0xB9
179#define DA9063_REG_VLDO1_B 0xBA
180#define DA9063_REG_VLDO2_B 0xBB
181#define DA9063_REG_VLDO3_B 0xBC
182#define DA9063_REG_VLDO4_B 0xBD
183#define DA9063_REG_VLDO5_B 0xBE
184#define DA9063_REG_VLDO6_B 0xBF
185#define DA9063_REG_VLDO7_B 0xC0
186#define DA9063_REG_VLDO8_B 0xC1
187#define DA9063_REG_VLDO9_B 0xC2
188#define DA9063_REG_VLDO10_B 0xC3
189#define DA9063_REG_VLDO11_B 0xC4
190
191/* Backup Battery Charger Control Register */
192#define DA9063_REG_BBAT_CONT 0xC5
193
194/* GPIO PWM (LED) */
195#define DA9063_REG_GPO11_LED 0xC6
196#define DA9063_REG_GPO14_LED 0xC7
197#define DA9063_REG_GPO15_LED 0xC8
198
199/* GP-ADC Threshold Registers */
200#define DA9063_REG_ADC_CFG 0xC9
201#define DA9063_REG_AUTO1_HIGH 0xCA
202#define DA9063_REG_AUTO1_LOW 0xCB
203#define DA9063_REG_AUTO2_HIGH 0xCC
204#define DA9063_REG_AUTO2_LOW 0xCD
205#define DA9063_REG_AUTO3_HIGH 0xCE
206#define DA9063_REG_AUTO3_LOW 0xCF
207
208/* DA9063 Configuration registers */
209/* OTP */
210#define DA9063_REG_OPT_COUNT 0x101
211#define DA9063_REG_OPT_ADDR 0x102
212#define DA9063_REG_OPT_DATA 0x103
213
214/* Customer Trim and Configuration */
215#define DA9063_REG_T_OFFSET 0x104
216#define DA9063_REG_INTERFACE 0x105
217#define DA9063_REG_CONFIG_A 0x106
218#define DA9063_REG_CONFIG_B 0x107
219#define DA9063_REG_CONFIG_C 0x108
220#define DA9063_REG_CONFIG_D 0x109
221#define DA9063_REG_CONFIG_E 0x10A
222#define DA9063_REG_CONFIG_F 0x10B
223#define DA9063_REG_CONFIG_G 0x10C
224#define DA9063_REG_CONFIG_H 0x10D
225#define DA9063_REG_CONFIG_I 0x10E
226#define DA9063_REG_CONFIG_J 0x10F
227#define DA9063_REG_CONFIG_K 0x110
228#define DA9063_REG_CONFIG_L 0x111
229#define DA9063_REG_MON_REG_1 0x112
230#define DA9063_REG_MON_REG_2 0x113
231#define DA9063_REG_MON_REG_3 0x114
232#define DA9063_REG_MON_REG_4 0x115
233#define DA9063_REG_MON_REG_5 0x116
234#define DA9063_REG_MON_REG_6 0x117
235#define DA9063_REG_TRIM_CLDR 0x118
236
237/* General Purpose Registers */
238#define DA9063_REG_GP_ID_0 0x119
239#define DA9063_REG_GP_ID_1 0x11A
240#define DA9063_REG_GP_ID_2 0x11B
241#define DA9063_REG_GP_ID_3 0x11C
242#define DA9063_REG_GP_ID_4 0x11D
243#define DA9063_REG_GP_ID_5 0x11E
244#define DA9063_REG_GP_ID_6 0x11F
245#define DA9063_REG_GP_ID_7 0x120
246#define DA9063_REG_GP_ID_8 0x121
247#define DA9063_REG_GP_ID_9 0x122
248#define DA9063_REG_GP_ID_10 0x123
249#define DA9063_REG_GP_ID_11 0x124
250#define DA9063_REG_GP_ID_12 0x125
251#define DA9063_REG_GP_ID_13 0x126
252#define DA9063_REG_GP_ID_14 0x127
253#define DA9063_REG_GP_ID_15 0x128
254#define DA9063_REG_GP_ID_16 0x129
255#define DA9063_REG_GP_ID_17 0x12A
256#define DA9063_REG_GP_ID_18 0x12B
257#define DA9063_REG_GP_ID_19 0x12C
258
259/* Chip ID and variant */
260#define DA9063_REG_CHIP_ID 0x181
261#define DA9063_REG_CHIP_VARIANT 0x182
262
263/*
264 * PMIC registers bits
265 */
266/* DA9063_REG_PAGE_CON (addr=0x00) */
267#define DA9063_PEG_PAGE_SHIFT 0
268#define DA9063_REG_PAGE_MASK 0x07
269#define DA9063_REG_PAGE0 0x00
270#define DA9063_REG_PAGE2 0x02
271#define DA9063_PAGE_WRITE_MODE 0x00
272#define DA9063_REPEAT_WRITE_MODE 0x40
273#define DA9063_PAGE_REVERT 0x80
274
275/* DA9063_REG_STATUS_A (addr=0x01) */
276#define DA9063_NONKEY 0x01
277#define DA9063_WAKE 0x02
278#define DA9063_DVC_BUSY 0x04
279#define DA9063_COMP_1V2 0x08
280
281/* DA9063_REG_STATUS_B (addr=0x02) */
282#define DA9063_GPI0 0x01
283#define DA9063_GPI1 0x02
284#define DA9063_GPI2 0x04
285#define DA9063_GPI3 0x08
286#define DA9063_GPI4 0x10
287#define DA9063_GPI5 0x20
288#define DA9063_GPI6 0x40
289#define DA9063_GPI7 0x80
290
291/* DA9063_REG_STATUS_C (addr=0x03) */
292#define DA9063_GPI8 0x01
293#define DA9063_GPI9 0x02
294#define DA9063_GPI10 0x04
295#define DA9063_GPI11 0x08
296#define DA9063_GPI12 0x10
297#define DA9063_GPI13 0x20
298#define DA9063_GPI14 0x40
299#define DA9063_GPI15 0x80
300
301/* DA9063_REG_STATUS_D (addr=0x04) */
302#define DA9063_LDO3_LIM 0x08
303#define DA9063_LDO4_LIM 0x10
304#define DA9063_LDO7_LIM 0x20
305#define DA9063_LDO8_LIM 0x40
306#define DA9063_LDO11_LIM 0x80
307
308/* DA9063_REG_FAULT_LOG (addr=0x05) */
309#define DA9063_TWD_ERROR 0x01
310#define DA9063_POR 0x02
311#define DA9063_VDD_FAULT 0x04
312#define DA9063_VDD_START 0x08
313#define DA9063_TEMP_CRIT 0x10
314#define DA9063_KEY_RESET 0x20
315#define DA9063_NSHUTDOWN 0x40
316#define DA9063_WAIT_SHUT 0x80
317
318/* DA9063_REG_EVENT_A (addr=0x06) */
319#define DA9063_E_NONKEY 0x01
320#define DA9063_E_ALARM 0x02
321#define DA9063_E_TICK 0x04
322#define DA9063_E_ADC_RDY 0x08
323#define DA9063_E_SEQ_RDY 0x10
324#define DA9063_EVENTS_B 0x20
325#define DA9063_EVENTS_C 0x40
326#define DA9063_EVENTS_D 0x80
327
328/* DA9063_REG_EVENT_B (addr=0x07) */
329#define DA9063_E_WAKE 0x01
330#define DA9063_E_TEMP 0x02
331#define DA9063_E_COMP_1V2 0x04
332#define DA9063_E_LDO_LIM 0x08
333#define DA9063_E_REG_UVOV 0x10
334#define DA9063_E_DVC_RDY 0x20
335#define DA9063_E_VDD_MON 0x40
336#define DA9063_E_VDD_WARN 0x80
337
338/* DA9063_REG_EVENT_C (addr=0x08) */
339#define DA9063_E_GPI0 0x01
340#define DA9063_E_GPI1 0x02
341#define DA9063_E_GPI2 0x04
342#define DA9063_E_GPI3 0x08
343#define DA9063_E_GPI4 0x10
344#define DA9063_E_GPI5 0x20
345#define DA9063_E_GPI6 0x40
346#define DA9063_E_GPI7 0x80
347
348/* DA9063_REG_EVENT_D (addr=0x09) */
349#define DA9063_E_GPI8 0x01
350#define DA9063_E_GPI9 0x02
351#define DA9063_E_GPI10 0x04
352#define DA9063_E_GPI11 0x08
353#define DA9063_E_GPI12 0x10
354#define DA9063_E_GPI13 0x20
355#define DA9063_E_GPI14 0x40
356#define DA9063_E_GPI15 0x80
357
358/* DA9063_REG_IRQ_MASK_A (addr=0x0A) */
359#define DA9063_M_ONKEY 0x01
360#define DA9063_M_ALARM 0x02
361#define DA9063_M_TICK 0x04
362#define DA9063_M_ADC_RDY 0x08
363#define DA9063_M_SEQ_RDY 0x10
364
365/* DA9063_REG_IRQ_MASK_B (addr=0x0B) */
366#define DA9063_M_WAKE 0x01
367#define DA9063_M_TEMP 0x02
368#define DA9063_M_COMP_1V2 0x04
369#define DA9063_M_LDO_LIM 0x08
370#define DA9063_M_UVOV 0x10
371#define DA9063_M_DVC_RDY 0x20
372#define DA9063_M_VDD_MON 0x40
373#define DA9063_M_VDD_WARN 0x80
374
375/* DA9063_REG_IRQ_MASK_C (addr=0x0C) */
376#define DA9063_M_GPI0 0x01
377#define DA9063_M_GPI1 0x02
378#define DA9063_M_GPI2 0x04
379#define DA9063_M_GPI3 0x08
380#define DA9063_M_GPI4 0x10
381#define DA9063_M_GPI5 0x20
382#define DA9063_M_GPI6 0x40
383#define DA9063_M_GPI7 0x80
384
385/* DA9063_REG_IRQ_MASK_D (addr=0x0D) */
386#define DA9063_M_GPI8 0x01
387#define DA9063_M_GPI9 0x02
388#define DA9063_M_GPI10 0x04
389#define DA9063_M_GPI11 0x08
390#define DA9063_M_GPI12 0x10
391#define DA9063_M_GPI13 0x20
392#define DA9063_M_GPI14 0x40
393#define DA9063_M_GPI15 0x80
394
395/* DA9063_REG_CONTROL_A (addr=0x0E) */
396#define DA9063_SYSTEM_EN 0x01
397#define DA9063_POWER_EN 0x02
398#define DA9063_POWER1_EN 0x04
399#define DA9063_STANDBY 0x08
400#define DA9063_M_SYSTEM_EN 0x10
401#define DA9063_M_POWER_EN 0x20
402#define DA9063_M_POWER1_EN 0x40
403#define DA9063_CP_EN 0x80
404
405/* DA9063_REG_CONTROL_B (addr=0x0F) */
406#define DA9063_CHG_SEL 0x01
407#define DA9063_WATCHDOG_PD 0x02
408#define DA9063_NRES_MODE 0x08
409#define DA9063_NONKEY_LOCK 0x10
410
411/* DA9063_REG_CONTROL_C (addr=0x10) */
412#define DA9063_DEBOUNCING_MASK 0x07
413#define DA9063_DEBOUNCING_OFF 0x0
414#define DA9063_DEBOUNCING_0MS1 0x1
415#define DA9063_DEBOUNCING_1MS 0x2
416#define DA9063_DEBOUNCING_10MS24 0x3
417#define DA9063_DEBOUNCING_51MS2 0x4
418#define DA9063_DEBOUNCING_256MS 0x5
419#define DA9063_DEBOUNCING_512MS 0x6
420#define DA9063_DEBOUNCING_1024MS 0x7
421
422#define DA9063_AUTO_BOOT 0x08
423#define DA9063_OTPREAD_EN 0x10
424#define DA9063_SLEW_RATE_MASK 0x60
425#define DA9063_SLEW_RATE_4US 0x00
426#define DA9063_SLEW_RATE_3US 0x20
427#define DA9063_SLEW_RATE_1US 0x40
428#define DA9063_SLEW_RATE_0US5 0x60
429#define DA9063_DEF_SUPPLY 0x80
430
431/* DA9063_REG_CONTROL_D (addr=0x11) */
432#define DA9063_TWDSCALE_MASK 0x07
433#define DA9063_BLINK_FRQ_MASK 0x38
434#define DA9063_BLINK_FRQ_OFF 0x00
435#define DA9063_BLINK_FRQ_1S0 0x08
436#define DA9063_BLINK_FRQ_2S0 0x10
437#define DA9063_BLINK_FRQ_4S0 0x18
438#define DA9063_BLINK_FRQ_0S18 0x20
439#define DA9063_BLINK_FRQ_2S0_VDD 0x28
440#define DA9063_BLINK_FRQ_4S0_VDD 0x30
441#define DA9063_BLINK_FRQ_0S18_VDD 0x38
442
443#define DA9063_BLINK_DUR_MASK 0xC0
444#define DA9063_BLINK_DUR_10MS 0x00
445#define DA9063_BLINK_DUR_20MS 0x40
446#define DA9063_BLINK_DUR_40MS 0x80
447#define DA9063_BLINK_DUR_20MSDBL 0xC0
448
449/* DA9063_REG_CONTROL_E (addr=0x12) */
450#define DA9063_RTC_MODE_PD 0x01
451#define DA9063_RTC_MODE_SD 0x02
452#define DA9063_RTC_EN 0x04
453#define DA9063_ECO_MODE 0x08
454#define DA9063_PM_FB1_PIN 0x10
455#define DA9063_PM_FB2_PIN 0x20
456#define DA9063_PM_FB3_PIN 0x40
457#define DA9063_V_LOCK 0x80
458
459/* DA9063_REG_CONTROL_F (addr=0x13) */
460#define DA9063_WATCHDOG 0x01
461#define DA9063_SHUTDOWN 0x02
462#define DA9063_WAKE_UP 0x04
463
464/* DA9063_REG_PD_DIS (addr=0x14) */
465#define DA9063_GPI_DIS 0x01
466#define DA9063_GPADC_PAUSE 0x02
467#define DA9063_PMIF_DIS 0x04
468#define DA9063_HS2WIRE_DIS 0x08
469#define DA9063_BBAT_DIS 0x20
470#define DA9063_OUT_32K_PAUSE 0x40
471#define DA9063_PMCONT_DIS 0x80
472
473/* DA9063_REG_GPIO_0_1 (addr=0x15) */
474#define DA9063_GPIO0_PIN_MASK 0x03
475#define DA9063_GPIO0_PIN_ADCIN1 0x00
476#define DA9063_GPIO0_PIN_GPI 0x01
477#define DA9063_GPIO0_PIN_GPO_OD 0x02
478#define DA9063_GPIO0_PIN_GPO 0x03
479#define DA9063_GPIO0_TYPE 0x04
480#define DA9063_GPIO0_TYPE_GPI_ACT_LOW 0x00
481#define DA9063_GPIO0_TYPE_GPO_VDD_IO1 0x00
482#define DA9063_GPIO0_TYPE_GPI_ACT_HIGH 0x04
483#define DA9063_GPIO0_TYPE_GPO_VDD_IO2 0x04
484#define DA9063_GPIO0_NO_WAKEUP 0x08
485#define DA9063_GPIO1_PIN_MASK 0x30
486#define DA9063_GPIO1_PIN_ADCIN2_COMP 0x00
487#define DA9063_GPIO1_PIN_GPI 0x10
488#define DA9063_GPIO1_PIN_GPO_OD 0x20
489#define DA9063_GPIO1_PIN_GPO 0x30
490#define DA9063_GPIO1_TYPE 0x40
491#define DA9063_GPIO1_TYPE_GPI_ACT_LOW 0x00
492#define DA9063_GPIO1_TYPE_GPO_VDD_IO1 0x00
493#define DA9063_GPIO1_TYPE_GPI_ACT_HIGH 0x04
494#define DA9063_GPIO1_TYPE_GPO_VDD_IO2 0x04
495#define DA9063_GPIO1_NO_WAKEUP 0x80
496
497/* DA9063_REG_GPIO_2_3 (addr=0x16) */
498#define DA9063_GPIO2_PIN_MASK 0x03
499#define DA9063_GPIO2_PIN_ADCIN3 0x00
500#define DA9063_GPIO2_PIN_GPI 0x01
501#define DA9063_GPIO2_PIN_GPO_PSS 0x02
502#define DA9063_GPIO2_PIN_GPO 0x03
503#define DA9063_GPIO2_TYPE 0x04
504#define DA9063_GPIO2_TYPE_GPI_ACT_LOW 0x00
505#define DA9063_GPIO2_TYPE_GPO_VDD_IO1 0x00
506#define DA9063_GPIO2_TYPE_GPI_ACT_HIGH 0x04
507#define DA9063_GPIO2_TYPE_GPO_VDD_IO2 0x04
508#define DA9063_GPIO2_NO_WAKEUP 0x08
509#define DA9063_GPIO3_PIN_MASK 0x30
510#define DA9063_GPIO3_PIN_CORE_SW_G 0x00
511#define DA9063_GPIO3_PIN_GPI 0x10
512#define DA9063_GPIO3_PIN_GPO_OD 0x20
513#define DA9063_GPIO3_PIN_GPO 0x30
514#define DA9063_GPIO3_TYPE 0x40
515#define DA9063_GPIO3_TYPE_GPI_ACT_LOW 0x00
516#define DA9063_GPIO3_TYPE_GPO_VDD_IO1 0x00
517#define DA9063_GPIO3_TYPE_GPI_ACT_HIGH 0x04
518#define DA9063_GPIO3_TYPE_GPO_VDD_IO2 0x04
519#define DA9063_GPIO3_NO_WAKEUP 0x80
520
521/* DA9063_REG_GPIO_4_5 (addr=0x17) */
522#define DA9063_GPIO4_PIN_MASK 0x03
523#define DA9063_GPIO4_PIN_CORE_SW_S 0x00
524#define DA9063_GPIO4_PIN_GPI 0x01
525#define DA9063_GPIO4_PIN_GPO_OD 0x02
526#define DA9063_GPIO4_PIN_GPO 0x03
527#define DA9063_GPIO4_TYPE 0x04
528#define DA9063_GPIO4_TYPE_GPI_ACT_LOW 0x00
529#define DA9063_GPIO4_TYPE_GPO_VDD_IO1 0x00
530#define DA9063_GPIO4_TYPE_GPI_ACT_HIGH 0x04
531#define DA9063_GPIO4_TYPE_GPO_VDD_IO2 0x04
532#define DA9063_GPIO4_NO_WAKEUP 0x08
533#define DA9063_GPIO5_PIN_MASK 0x30
534#define DA9063_GPIO5_PIN_PERI_SW_G 0x00
535#define DA9063_GPIO5_PIN_GPI 0x10
536#define DA9063_GPIO5_PIN_GPO_OD 0x20
537#define DA9063_GPIO5_PIN_GPO 0x30
538#define DA9063_GPIO5_TYPE 0x40
539#define DA9063_GPIO5_TYPE_GPI_ACT_LOW 0x00
540#define DA9063_GPIO5_TYPE_GPO_VDD_IO1 0x00
541#define DA9063_GPIO5_TYPE_GPI_ACT_HIGH 0x04
542#define DA9063_GPIO5_TYPE_GPO_VDD_IO2 0x04
543#define DA9063_GPIO5_NO_WAKEUP 0x80
544
545/* DA9063_REG_GPIO_6_7 (addr=0x18) */
546#define DA9063_GPIO6_PIN_MASK 0x03
547#define DA9063_GPIO6_PIN_PERI_SW_S 0x00
548#define DA9063_GPIO6_PIN_GPI 0x01
549#define DA9063_GPIO6_PIN_GPO_OD 0x02
550#define DA9063_GPIO6_PIN_GPO 0x03
551#define DA9063_GPIO6_TYPE 0x04
552#define DA9063_GPIO6_TYPE_GPI_ACT_LOW 0x00
553#define DA9063_GPIO6_TYPE_GPO_VDD_IO1 0x00
554#define DA9063_GPIO6_TYPE_GPI_ACT_HIGH 0x04
555#define DA9063_GPIO6_TYPE_GPO_VDD_IO2 0x04
556#define DA9063_GPIO6_NO_WAKEUP 0x08
557#define DA9063_GPIO7_PIN_MASK 0x30
558#define DA9063_GPIO7_PIN_GPI 0x10
559#define DA9063_GPIO7_PIN_GPO_PSS 0x20
560#define DA9063_GPIO7_PIN_GPO 0x30
561#define DA9063_GPIO7_TYPE 0x40
562#define DA9063_GPIO7_TYPE_GPI_ACT_LOW 0x00
563#define DA9063_GPIO7_TYPE_GPO_VDD_IO1 0x00
564#define DA9063_GPIO7_TYPE_GPI_ACT_HIGH 0x04
565#define DA9063_GPIO7_TYPE_GPO_VDD_IO2 0x04
566#define DA9063_GPIO7_NO_WAKEUP 0x80
567
568/* DA9063_REG_GPIO_8_9 (addr=0x19) */
569#define DA9063_GPIO8_PIN_MASK 0x03
570#define DA9063_GPIO8_PIN_GPI_SYS_EN 0x00
571#define DA9063_GPIO8_PIN_GPI 0x01
572#define DA9063_GPIO8_PIN_GPO_PSS 0x02
573#define DA9063_GPIO8_PIN_GPO 0x03
574#define DA9063_GPIO8_TYPE 0x04
575#define DA9063_GPIO8_TYPE_GPI_ACT_LOW 0x00
576#define DA9063_GPIO8_TYPE_GPO_VDD_IO1 0x00
577#define DA9063_GPIO8_TYPE_GPI_ACT_HIGH 0x04
578#define DA9063_GPIO8_TYPE_GPO_VDD_IO2 0x04
579#define DA9063_GPIO8_NO_WAKEUP 0x08
580#define DA9063_GPIO9_PIN_MASK 0x30
581#define DA9063_GPIO9_PIN_GPI_PWR_EN 0x00
582#define DA9063_GPIO9_PIN_GPI 0x10
583#define DA9063_GPIO9_PIN_GPO_PSS 0x20
584#define DA9063_GPIO9_PIN_GPO 0x30
585#define DA9063_GPIO9_TYPE 0x40
586#define DA9063_GPIO9_TYPE_GPI_ACT_LOW 0x00
587#define DA9063_GPIO9_TYPE_GPO_VDD_IO1 0x00
588#define DA9063_GPIO9_TYPE_GPI_ACT_HIGH 0x04
589#define DA9063_GPIO9_TYPE_GPO_VDD_IO2 0x04
590#define DA9063_GPIO9_NO_WAKEUP 0x80
591
592/* DA9063_REG_GPIO_10_11 (addr=0x1A) */
593#define DA9063_GPIO10_PIN_MASK 0x03
594#define DA9063_GPIO10_PIN_GPI_PWR1_EN 0x00
595#define DA9063_GPIO10_PIN_GPI 0x01
596#define DA9063_GPIO10_PIN_GPO_OD 0x02
597#define DA9063_GPIO10_PIN_GPO 0x03
598#define DA9063_GPIO10_TYPE 0x04
599#define DA9063_GPIO10_TYPE_GPI_ACT_LOW 0x00
600#define DA9063_GPIO10_TYPE_GPO_VDD_IO1 0x00
601#define DA9063_GPIO10_TYPE_GPI_ACT_HIGH 0x04
602#define DA9063_GPIO10_TYPE_GPO_VDD_IO2 0x04
603#define DA9063_GPIO10_NO_WAKEUP 0x08
604#define DA9063_GPIO11_PIN_MASK 0x30
605#define DA9063_GPIO11_PIN_GPO_OD 0x00
606#define DA9063_GPIO11_PIN_GPI 0x10
607#define DA9063_GPIO11_PIN_GPO_PSS 0x20
608#define DA9063_GPIO11_PIN_GPO 0x30
609#define DA9063_GPIO11_TYPE 0x40
610#define DA9063_GPIO11_TYPE_GPI_ACT_LOW 0x00
611#define DA9063_GPIO11_TYPE_GPO_VDD_IO1 0x00
612#define DA9063_GPIO11_TYPE_GPI_ACT_HIGH 0x04
613#define DA9063_GPIO11_TYPE_GPO_VDD_IO2 0x04
614#define DA9063_GPIO11_NO_WAKEUP 0x80
615
616/* DA9063_REG_GPIO_12_13 (addr=0x1B) */
617#define DA9063_GPIO12_PIN_MASK 0x03
618#define DA9063_GPIO12_PIN_NVDDFLT_OUT 0x00
619#define DA9063_GPIO12_PIN_GPI 0x01
620#define DA9063_GPIO12_PIN_VSYSMON_OUT 0x02
621#define DA9063_GPIO12_PIN_GPO 0x03
622#define DA9063_GPIO12_TYPE 0x04
623#define DA9063_GPIO12_TYPE_GPI_ACT_LOW 0x00
624#define DA9063_GPIO12_TYPE_GPO_VDD_IO1 0x00
625#define DA9063_GPIO12_TYPE_GPI_ACT_HIGH 0x04
626#define DA9063_GPIO12_TYPE_GPO_VDD_IO2 0x04
627#define DA9063_GPIO12_NO_WAKEUP 0x08
628#define DA9063_GPIO13_PIN_MASK 0x30
629#define DA9063_GPIO13_PIN_GPFB1_OUT 0x00
630#define DA9063_GPIO13_PIN_GPI 0x10
631#define DA9063_GPIO13_PIN_GPFB1_OUTOD 0x20
632#define DA9063_GPIO13_PIN_GPO 0x30
633#define DA9063_GPIO13_TYPE 0x40
634#define DA9063_GPIO13_TYPE_GPFB1_OUT 0x00
635#define DA9063_GPIO13_TYPE_GPI 0x00
636#define DA9063_GPIO13_TYPE_GPFB1_OUTOD 0x04
637#define DA9063_GPIO13_TYPE_GPO 0x04
638#define DA9063_GPIO13_NO_WAKEUP 0x80
639
640/* DA9063_REG_GPIO_14_15 (addr=0x1C) */
641#define DA9063_GPIO14_PIN_MASK 0x03
642#define DA9063_GPIO14_PIN_GPO_OD 0x00
643#define DA9063_GPIO14_PIN_GPI 0x01
644#define DA9063_GPIO14_PIN_HS2DATA 0x02
645#define DA9063_GPIO14_PIN_GPO 0x03
646#define DA9063_GPIO14_TYPE 0x04
647#define DA9063_GPIO14_TYPE_GPI_ACT_LOW 0x00
648#define DA9063_GPIO14_TYPE_GPO_VDD_IO1 0x00
649#define DA9063_GPIO14_TYPE_GPI_ACT_HIGH 0x04
650#define DA9063_GPIO14_TYPE_GPO_VDD_IO2 0x04
651#define DA9063_GPIO14_NO_WAKEUP 0x08
652#define DA9063_GPIO15_PIN_MASK 0x30
653#define DA9063_GPIO15_PIN_GPO_OD 0x00
654#define DA9063_GPIO15_PIN_GPI 0x10
655#define DA9063_GPIO15_PIN_GPO 0x30
656#define DA9063_GPIO15_TYPE 0x40
657#define DA9063_GPIO15_TYPE_GPFB1_OUT 0x00
658#define DA9063_GPIO15_TYPE_GPI 0x00
659#define DA9063_GPIO15_TYPE_GPFB1_OUTOD 0x04
660#define DA9063_GPIO15_TYPE_GPO 0x04
661#define DA9063_GPIO15_NO_WAKEUP 0x80
662
663/* DA9063_REG_GPIO_MODE_0_7 (addr=0x1D) */
664#define DA9063_GPIO0_MODE 0x01
665#define DA9063_GPIO1_MODE 0x02
666#define DA9063_GPIO2_MODE 0x04
667#define DA9063_GPIO3_MODE 0x08
668#define DA9063_GPIO4_MODE 0x10
669#define DA9063_GPIO5_MODE 0x20
670#define DA9063_GPIO6_MODE 0x40
671#define DA9063_GPIO7_MODE 0x80
672
673/* DA9063_REG_GPIO_MODE_8_15 (addr=0x1E) */
674#define DA9063_GPIO8_MODE 0x01
675#define DA9063_GPIO9_MODE 0x02
676#define DA9063_GPIO10_MODE 0x04
677#define DA9063_GPIO11_MODE 0x08
678#define DA9063_GPIO11_MODE_LED_ACT_HIGH 0x00
679#define DA9063_GPIO11_MODE_LED_ACT_LOW 0x08
680#define DA9063_GPIO12_MODE 0x10
681#define DA9063_GPIO13_MODE 0x20
682#define DA9063_GPIO14_MODE 0x40
683#define DA9063_GPIO14_MODE_LED_ACT_HIGH 0x00
684#define DA9063_GPIO14_MODE_LED_ACT_LOW 0x40
685#define DA9063_GPIO15_MODE 0x80
686#define DA9063_GPIO15_MODE_LED_ACT_HIGH 0x00
687#define DA9063_GPIO15_MODE_LED_ACT_LOW 0x80
688
689/* DA9063_REG_SWITCH_CONT (addr=0x1F) */
690#define DA9063_CORE_SW_GPI_MASK 0x03
691#define DA9063_CORE_SW_GPI_OFF 0x00
692#define DA9063_CORE_SW_GPI_GPIO1 0x01
693#define DA9063_CORE_SW_GPI_GPIO2 0x02
694#define DA9063_CORE_SW_GPI_GPIO13 0x03
695#define DA9063_PERI_SW_GPI_MASK 0x0C
696#define DA9063_PERI_SW_GPI_OFF 0x00
697#define DA9063_PERI_SW_GPI_GPIO1 0x04
698#define DA9063_PERI_SW_GPI_GPIO2 0x08
699#define DA9063_PERI_SW_GPI_GPIO13 0x0C
700#define DA9063_SWITCH_SR_MASK 0x30
701#define DA9063_SWITCH_SR_1MV 0x00
702#define DA9063_SWITCH_SR_5MV 0x10
703#define DA9063_SWITCH_SR_10MV 0x20
704#define DA9063_SWITCH_SR_50MV 0x30
705#define DA9063_SWITCH_SR_DIS 0x40
706#define DA9063_CP_EN_MODE 0x80
707
708/* DA9063_REGL_Bxxxx_CONT common bits (addr=0x20-0x25) */
709#define DA9063_BUCK_EN 0x01
710#define DA9063_BUCK_GPI_MASK 0x06
711#define DA9063_BUCK_GPI_OFF 0x00
712#define DA9063_BUCK_GPI_GPIO1 0x02
713#define DA9063_BUCK_GPI_GPIO2 0x04
714#define DA9063_BUCK_GPI_GPIO13 0x06
715#define DA9063_BUCK_CONF 0x08
716#define DA9063_VBUCK_GPI_MASK 0x60
717#define DA9063_VBUCK_GPI_OFF 0x00
718#define DA9063_VBUCK_GPI_GPIO1 0x20
719#define DA9063_VBUCK_GPI_GPIO2 0x40
720#define DA9063_VBUCK_GPI_GPIO13 0x60
721
722/* DA9063_REG_BCORE1_CONT specific bits (addr=0x21) */
723#define DA9063_CORE_SW_EN 0x10
724#define DA9063_CORE_SW_CONF 0x80
725
726/* DA9063_REG_BPERI_CONT specific bits (addr=0x25) */
727#define DA9063_PERI_SW_EN 0x10
728#define DA9063_PERI_SW_CONF 0x80
729
730/* DA9063_REG_LDOx_CONT common bits (addr=0x26-0x30) */
731#define DA9063_LDO_EN 0x01
732#define DA9063_LDO_GPI_MASK 0x06
733#define DA9063_LDO_GPI_OFF 0x00
734#define DA9063_LDO_GPI_GPIO1 0x02
735#define DA9063_LDO_GPI_GPIO2 0x04
736#define DA9063_LDO_GPI_GPIO13 0x06
737#define DA9063_LDO_PD_DIS 0x08
738#define DA9063_VLDO_GPI_MASK 0x60
739#define DA9063_VLDO_GPI_OFF 0x00
740#define DA9063_VLDO_GPI_GPIO1 0x20
741#define DA9063_VLDO_GPI_GPIO2 0x40
742#define DA9063_VLDO_GPI_GPIO13 0x60
743#define DA9063_LDO_CONF 0x80
744
745/* DA9063_REG_LDO5_CONT specific bits (addr=0x2A) */
746#define DA9063_VLDO5_SEL 0x10
747
748/* DA9063_REG_LDO6_CONT specific bits (addr=0x2B) */
749#define DA9063_VLDO6_SEL 0x10
750
751/* DA9063_REG_LDO7_CONT specific bits (addr=0x2C) */
752#define DA9063_VLDO7_SEL 0x10
753
754/* DA9063_REG_LDO8_CONT specific bits (addr=0x2D) */
755#define DA9063_VLDO8_SEL 0x10
756
757/* DA9063_REG_LDO9_CONT specific bits (addr=0x2E) */
758#define DA9063_VLDO9_SEL 0x10
759
760/* DA9063_REG_LDO10_CONT specific bits (addr=0x2F) */
761#define DA9063_VLDO10_SEL 0x10
762
763/* DA9063_REG_LDO11_CONT specific bits (addr=0x30) */
764#define DA9063_VLDO11_SEL 0x10
765
766/* DA9063_REG_VIB (addr=0x31) */
767#define DA9063_VIB_SET_MASK 0x3F
768#define DA9063_VIB_SET_OFF 0
769#define DA9063_VIB_SET_MAX 0x3F
770
771/* DA9063_REG_DVC_1 (addr=0x32) */
772#define DA9063_VBCORE1_SEL 0x01
773#define DA9063_VBCORE2_SEL 0x02
774#define DA9063_VBPRO_SEL 0x04
775#define DA9063_VBMEM_SEL 0x08
776#define DA9063_VBPERI_SEL 0x10
777#define DA9063_VLDO1_SEL 0x20
778#define DA9063_VLDO2_SEL 0x40
779#define DA9063_VLDO3_SEL 0x80
780
781/* DA9063_REG_DVC_2 (addr=0x33) */
782#define DA9063_VBIO_SEL 0x01
783#define DA9063_VLDO4_SEL 0x80
784
785/* DA9063_REG_ADC_MAN (addr=0x34) */
786#define DA9063_ADC_MUX_MASK 0x0F
787#define DA9063_ADC_MUX_VSYS 0x00
788#define DA9063_ADC_MUX_ADCIN1 0x01
789#define DA9063_ADC_MUX_ADCIN2 0x02
790#define DA9063_ADC_MUX_ADCIN3 0x03
791#define DA9063_ADC_MUX_T_SENSE 0x04
792#define DA9063_ADC_MUX_VBBAT 0x05
793#define DA9063_ADC_MUX_LDO_G1 0x08
794#define DA9063_ADC_MUX_LDO_G2 0x09
795#define DA9063_ADC_MUX_LDO_G3 0x0A
796#define DA9063_ADC_MAN 0x10
797#define DA9063_ADC_MODE 0x20
798
799/* DA9063_REG_ADC_CONT (addr=0x35) */
800#define DA9063_ADC_AUTO_VSYS_EN 0x01
801#define DA9063_ADC_AUTO_AD1_EN 0x02
802#define DA9063_ADC_AUTO_AD2_EN 0x04
803#define DA9063_ADC_AUTO_AD3_EN 0x08
804#define DA9063_ADC_AD1_ISRC_EN 0x10
805#define DA9063_ADC_AD2_ISRC_EN 0x20
806#define DA9063_ADC_AD3_ISRC_EN 0x40
807#define DA9063_COMP1V2_EN 0x80
808
809/* DA9063_REG_VSYS_MON (addr=0x36) */
810#define DA9063_VSYS_VAL_MASK 0xFF
811#define DA9063_VSYS_VAL_BASE 0x00
812
813/* DA9063_REG_ADC_RES_L (addr=0x37) */
814#define DA9063_ADC_RES_L_BITS 2
815#define DA9063_ADC_RES_L_MASK 0xC0
816
817/* DA9063_REG_ADC_RES_H (addr=0x38) */
818#define DA9063_ADC_RES_M_BITS 8
819#define DA9063_ADC_RES_M_MASK 0xFF
820
821/* DA9063_REG_(xxx_RES/ADC_RES_H) (addr=0x39-0x3F) */
822#define DA9063_ADC_VAL_MASK 0xFF
823
824/* DA9063_REG_COUNT_S (addr=0x40) */
825#define DA9063_RTC_READ 0x80
826#define DA9063_COUNT_SEC_MASK 0x3F
827
828/* DA9063_REG_COUNT_MI (addr=0x41) */
829#define DA9063_COUNT_MIN_MASK 0x3F
830
831/* DA9063_REG_COUNT_H (addr=0x42) */
832#define DA9063_COUNT_HOUR_MASK 0x1F
833
834/* DA9063_REG_COUNT_D (addr=0x43) */
835#define DA9063_COUNT_DAY_MASK 0x1F
836
837/* DA9063_REG_COUNT_MO (addr=0x44) */
838#define DA9063_COUNT_MONTH_MASK 0x0F
839
840/* DA9063_REG_COUNT_Y (addr=0x45) */
841#define DA9063_COUNT_YEAR_MASK 0x3F
842#define DA9063_MONITOR 0x40
843
844/* DA9063_REG_ALARM_MI (addr=0x46) */
845#define DA9063_ALARM_STATUS_ALARM 0x80
846#define DA9063_ALARM_STATUS_TICK 0x40
847#define DA9063_ALARM_MIN_MASK 0x3F
848
849/* DA9063_REG_ALARM_H (addr=0x47) */
850#define DA9063_ALARM_HOUR_MASK 0x1F
851
852/* DA9063_REG_ALARM_D (addr=0x48) */
853#define DA9063_ALARM_DAY_MASK 0x1F
854
855/* DA9063_REG_ALARM_MO (addr=0x49) */
856#define DA9063_TICK_WAKE 0x20
857#define DA9063_TICK_TYPE 0x10
858#define DA9063_TICK_TYPE_SEC 0x00
859#define DA9063_TICK_TYPE_MIN 0x10
860#define DA9063_ALARM_MONTH_MASK 0x0F
861
862/* DA9063_REG_ALARM_Y (addr=0x4A) */
863#define DA9063_TICK_ON 0x80
864#define DA9063_ALARM_ON 0x40
865#define DA9063_ALARM_YEAR_MASK 0x3F
866
867/* DA9063_REG_WAIT (addr=0x97)*/
868#define DA9063_REG_WAIT_TIME_MASK 0xF
869#define DA9063_WAIT_TIME_0_US 0x0
870#define DA9063_WAIT_TIME_512_US 0x1
871#define DA9063_WAIT_TIME_1_MS 0x2
872#define DA9063_WAIT_TIME_2_MS 0x3
873#define DA9063_WAIT_TIME_4_1_MS 0x4
874#define DA9063_WAIT_TIME_8_2_MS 0x5
875#define DA9063_WAIT_TIME_16_4_MS 0x6
876#define DA9063_WAIT_TIME_32_8_MS 0x7
877#define DA9063_WAIT_TIME_65_5_MS 0x8
878#define DA9063_WAIT_TIME_128_MS 0x9
879#define DA9063_WAIT_TIME_256_MS 0xA
880#define DA9063_WAIT_TIME_512_MS 0xB
881#define DA9063_WAIT_TIME_1_S 0xC
882#define DA9063_WAIT_TIME_2_1_S 0xD
883
884/* DA9063_REG_EN_32K (addr=0x98)*/
885#define DA9063_STABILIZ_TIME_MASK 0x7
886#define DA9063_CRYSTAL 0x08
887#define DA9063_DELAY_MODE 0x10
888#define DA9063_OUT_CLOCK 0x20
889#define DA9063_RTC_CLOCK 0x40
890#define DA9063_OUT_32K_EN 0x80
891
892/* DA9063_REG_CHIP_VARIANT */
893#define DA9063_CHIP_VARIANT_SHIFT 4
894
895/* DA9063_REG_BUCK_ILIM_A (addr=0x9A) */
896#define DA9063_BIO_ILIM_MASK 0x0F
897#define DA9063_BMEM_ILIM_MASK 0xF0
898
899/* DA9063_REG_BUCK_ILIM_B (addr=0x9B) */
900#define DA9063_BPRO_ILIM_MASK 0x0F
901#define DA9063_BPERI_ILIM_MASK 0xF0
902
903/* DA9063_REG_BUCK_ILIM_C (addr=0x9C) */
904#define DA9063_BCORE1_ILIM_MASK 0x0F
905#define DA9063_BCORE2_ILIM_MASK 0xF0
906
907/* DA9063_REG_Bxxxx_CFG common bits (addr=0x9D-0xA2) */
908#define DA9063_BUCK_FB_MASK 0x07
909#define DA9063_BUCK_PD_DIS_SHIFT 5
910#define DA9063_BUCK_MODE_MASK 0xC0
911#define DA9063_BUCK_MODE_MANUAL 0x00
912#define DA9063_BUCK_MODE_SLEEP 0x40
913#define DA9063_BUCK_MODE_SYNC 0x80
914#define DA9063_BUCK_MODE_AUTO 0xC0
915
916/* DA9063_REG_BPRO_CFG (addr=0x9F) */
917#define DA9063_BPRO_VTTR_EN 0x08
918#define DA9063_BPRO_VTT_EN 0x10
919
920/* DA9063_REG_VBxxxx_A/B (addr=0xA3-0xA8, 0xB4-0xB9) */
921#define DA9063_VBUCK_MASK 0x7F
922#define DA9063_VBUCK_BIAS 0
923#define DA9063_BUCK_SL 0x80
924
925/* DA9063_REG_VLDOx_A/B (addr=0xA9-0x3, 0xBA-0xC4) */
926#define DA9063_LDO_SL 0x80
927
928/* DA9063_REG_VLDO1_A/B (addr=0xA9, 0xBA) */
929#define DA9063_VLDO1_MASK 0x3F
930#define DA9063_VLDO1_BIAS 0
931
932/* DA9063_REG_VLDO2_A/B (addr=0xAA, 0xBB) */
933#define DA9063_VLDO2_MASK 0x3F
934#define DA9063_VLDO2_BIAS 0
935
936/* DA9063_REG_VLDO3_A/B (addr=0xAB, 0xBC) */
937#define DA9063_VLDO3_MASK 0x7F
938#define DA9063_VLDO3_BIAS 0
939
940/* DA9063_REG_VLDO4_A/B (addr=0xAC, 0xBD) */
941#define DA9063_VLDO4_MASK 0x7F
942#define DA9063_VLDO4_BIAS 0
943
944/* DA9063_REG_VLDO5_A/B (addr=0xAD, 0xBE) */
945#define DA9063_VLDO5_MASK 0x3F
946#define DA9063_VLDO5_BIAS 2
947
948/* DA9063_REG_VLDO6_A/B (addr=0xAE, 0xBF) */
949#define DA9063_VLDO6_MASK 0x3F
950#define DA9063_VLDO6_BIAS 2
951
952/* DA9063_REG_VLDO7_A/B (addr=0xAF, 0xC0) */
953#define DA9063_VLDO7_MASK 0x3F
954#define DA9063_VLDO7_BIAS 2
955
956/* DA9063_REG_VLDO8_A/B (addr=0xB0, 0xC1) */
957#define DA9063_VLDO8_MASK 0x3F
958#define DA9063_VLDO8_BIAS 2
959
960/* DA9063_REG_VLDO9_A/B (addr=0xB1, 0xC2) */
961#define DA9063_VLDO9_MASK 0x3F
962#define DA9063_VLDO9_BIAS 3
963
964/* DA9063_REG_VLDO10_A/B (addr=0xB2, 0xC3) */
965#define DA9063_VLDO10_MASK 0x3F
966#define DA9063_VLDO10_BIAS 2
967
968/* DA9063_REG_VLDO11_A/B (addr=0xB3, 0xC4) */
969#define DA9063_VLDO11_MASK 0x3F
970#define DA9063_VLDO11_BIAS 2
971
972/* DA9063_REG_GPO11_LED (addr=0xC6) */
973/* DA9063_REG_GPO14_LED (addr=0xC7) */
974/* DA9063_REG_GPO15_LED (addr=0xC8) */
975#define DA9063_GPIO_DIM 0x80
976#define DA9063_GPIO_PWM_MASK 0x7F
977
978/* DA9063_REG_CONFIG_H (addr=0x10D) */
979#define DA9063_PWM_CLK_MASK 0x01
980#define DA9063_PWM_CLK_PWM2MHZ 0x00
981#define DA9063_PWM_CLK_PWM1MHZ 0x01
982#define DA9063_LDO8_MODE_MASK 0x02
983#define DA9063_LDO8_MODE_LDO 0
984#define DA9063_LDO8_MODE_VIBR 0x02
985#define DA9063_MERGE_SENSE_MASK 0x04
986#define DA9063_MERGE_SENSE_GP_FB2 0x00
987#define DA9063_MERGE_SENSE_GPIO4 0x04
988#define DA9063_BCORE_MERGE 0x08
989#define DA9063_BPRO_OD 0x10
990#define DA9063_BCORE2_OD 0x20
991#define DA9063_BCORE1_OD 0x40
992#define DA9063_BUCK_MERGE 0x80
993
994/* DA9063_REG_CONFIG_I (addr=0x10E) */
995#define DA9063_NONKEY_PIN_MASK 0x03
996#define DA9063_NONKEY_PIN_PORT 0x00
997#define DA9063_NONKEY_PIN_SWDOWN 0x01
998#define DA9063_NONKEY_PIN_AUTODOWN 0x02
999#define DA9063_NONKEY_PIN_AUTOFLPRT 0x03
1000
1001/* DA9063_REG_MON_REG_5 (addr=0x116) */
1002#define DA9063_MON_A8_IDX_MASK 0x07
1003#define DA9063_MON_A8_IDX_NONE 0x00
1004#define DA9063_MON_A8_IDX_BCORE1 0x01
1005#define DA9063_MON_A8_IDX_BCORE2 0x02
1006#define DA9063_MON_A8_IDX_BPRO 0x03
1007#define DA9063_MON_A8_IDX_LDO3 0x04
1008#define DA9063_MON_A8_IDX_LDO4 0x05
1009#define DA9063_MON_A8_IDX_LDO11 0x06
1010#define DA9063_MON_A9_IDX_MASK 0x70
1011#define DA9063_MON_A9_IDX_NONE 0x00
1012#define DA9063_MON_A9_IDX_BIO 0x01
1013#define DA9063_MON_A9_IDX_BMEM 0x02
1014#define DA9063_MON_A9_IDX_BPERI 0x03
1015#define DA9063_MON_A9_IDX_LDO1 0x04
1016#define DA9063_MON_A9_IDX_LDO2 0x05
1017#define DA9063_MON_A9_IDX_LDO5 0x06
1018
1019/* DA9063_REG_MON_REG_6 (addr=0x117) */
1020#define DA9063_MON_A10_IDX_MASK 0x07
1021#define DA9063_MON_A10_IDX_NONE 0x00
1022#define DA9063_MON_A10_IDX_LDO6 0x01
1023#define DA9063_MON_A10_IDX_LDO7 0x02
1024#define DA9063_MON_A10_IDX_LDO8 0x03
1025#define DA9063_MON_A10_IDX_LDO9 0x04
1026#define DA9063_MON_A10_IDX_LDO10 0x05
1027
1028#endif /* _DA9063_REG_H */
diff --git a/include/linux/mfd/davinci_voicecodec.h b/include/linux/mfd/davinci_voicecodec.h
index 13a1ee95a233..5166935ce66d 100644
--- a/include/linux/mfd/davinci_voicecodec.h
+++ b/include/linux/mfd/davinci_voicecodec.h
@@ -30,6 +30,8 @@
30 30
31#include <mach/hardware.h> 31#include <mach/hardware.h>
32 32
33struct regmap;
34
33/* 35/*
34 * Register values. 36 * Register values.
35 */ 37 */
@@ -113,6 +115,7 @@ struct davinci_vc {
113 115
114 /* Memory resources */ 116 /* Memory resources */
115 void __iomem *base; 117 void __iomem *base;
118 struct regmap *regmap;
116 119
117 /* MFD cells */ 120 /* MFD cells */
118 struct mfd_cell cells[DAVINCI_VC_CELLS]; 121 struct mfd_cell cells[DAVINCI_VC_CELLS];
diff --git a/include/linux/mfd/mcp.h b/include/linux/mfd/mcp.h
index a9e8bd157673..f682953043ba 100644
--- a/include/linux/mfd/mcp.h
+++ b/include/linux/mfd/mcp.h
@@ -10,6 +10,8 @@
10#ifndef MCP_H 10#ifndef MCP_H
11#define MCP_H 11#define MCP_H
12 12
13#include <linux/device.h>
14
13struct mcp_ops; 15struct mcp_ops;
14 16
15struct mcp { 17struct mcp {
diff --git a/include/linux/mfd/palmas.h b/include/linux/mfd/palmas.h
index 1a8dd7afe084..9974e387e483 100644
--- a/include/linux/mfd/palmas.h
+++ b/include/linux/mfd/palmas.h
@@ -160,7 +160,8 @@ enum palmas_regulators {
160 PALMAS_REG_SMPS7, 160 PALMAS_REG_SMPS7,
161 PALMAS_REG_SMPS8, 161 PALMAS_REG_SMPS8,
162 PALMAS_REG_SMPS9, 162 PALMAS_REG_SMPS9,
163 PALMAS_REG_SMPS10, 163 PALMAS_REG_SMPS10_OUT2,
164 PALMAS_REG_SMPS10_OUT1,
164 /* LDO regulators */ 165 /* LDO regulators */
165 PALMAS_REG_LDO1, 166 PALMAS_REG_LDO1,
166 PALMAS_REG_LDO2, 167 PALMAS_REG_LDO2,
@@ -183,6 +184,50 @@ enum palmas_regulators {
183 PALMAS_NUM_REGS, 184 PALMAS_NUM_REGS,
184}; 185};
185 186
187/* External controll signal name */
188enum {
189 PALMAS_EXT_CONTROL_ENABLE1 = 0x1,
190 PALMAS_EXT_CONTROL_ENABLE2 = 0x2,
191 PALMAS_EXT_CONTROL_NSLEEP = 0x4,
192};
193
194/*
195 * Palmas device resources can be controlled externally for
196 * enabling/disabling it rather than register write through i2c.
197 * Add the external controlled requestor ID for different resources.
198 */
199enum palmas_external_requestor_id {
200 PALMAS_EXTERNAL_REQSTR_ID_REGEN1,
201 PALMAS_EXTERNAL_REQSTR_ID_REGEN2,
202 PALMAS_EXTERNAL_REQSTR_ID_SYSEN1,
203 PALMAS_EXTERNAL_REQSTR_ID_SYSEN2,
204 PALMAS_EXTERNAL_REQSTR_ID_CLK32KG,
205 PALMAS_EXTERNAL_REQSTR_ID_CLK32KGAUDIO,
206 PALMAS_EXTERNAL_REQSTR_ID_REGEN3,
207 PALMAS_EXTERNAL_REQSTR_ID_SMPS12,
208 PALMAS_EXTERNAL_REQSTR_ID_SMPS3,
209 PALMAS_EXTERNAL_REQSTR_ID_SMPS45,
210 PALMAS_EXTERNAL_REQSTR_ID_SMPS6,
211 PALMAS_EXTERNAL_REQSTR_ID_SMPS7,
212 PALMAS_EXTERNAL_REQSTR_ID_SMPS8,
213 PALMAS_EXTERNAL_REQSTR_ID_SMPS9,
214 PALMAS_EXTERNAL_REQSTR_ID_SMPS10,
215 PALMAS_EXTERNAL_REQSTR_ID_LDO1,
216 PALMAS_EXTERNAL_REQSTR_ID_LDO2,
217 PALMAS_EXTERNAL_REQSTR_ID_LDO3,
218 PALMAS_EXTERNAL_REQSTR_ID_LDO4,
219 PALMAS_EXTERNAL_REQSTR_ID_LDO5,
220 PALMAS_EXTERNAL_REQSTR_ID_LDO6,
221 PALMAS_EXTERNAL_REQSTR_ID_LDO7,
222 PALMAS_EXTERNAL_REQSTR_ID_LDO8,
223 PALMAS_EXTERNAL_REQSTR_ID_LDO9,
224 PALMAS_EXTERNAL_REQSTR_ID_LDOLN,
225 PALMAS_EXTERNAL_REQSTR_ID_LDOUSB,
226
227 /* Last entry */
228 PALMAS_EXTERNAL_REQSTR_ID_MAX,
229};
230
186struct palmas_pmic_platform_data { 231struct palmas_pmic_platform_data {
187 /* An array of pointers to regulator init data indexed by regulator 232 /* An array of pointers to regulator init data indexed by regulator
188 * ID 233 * ID
@@ -258,6 +303,7 @@ struct palmas_platform_data {
258 */ 303 */
259 int mux_from_pdata; 304 int mux_from_pdata;
260 u8 pad1, pad2; 305 u8 pad1, pad2;
306 bool pm_off;
261 307
262 struct palmas_pmic_platform_data *pmic_pdata; 308 struct palmas_pmic_platform_data *pmic_pdata;
263 struct palmas_gpadc_platform_data *gpadc_pdata; 309 struct palmas_gpadc_platform_data *gpadc_pdata;
@@ -355,9 +401,9 @@ struct palmas_pmic {
355 int smps123; 401 int smps123;
356 int smps457; 402 int smps457;
357 403
358 int range[PALMAS_REG_SMPS10]; 404 int range[PALMAS_REG_SMPS10_OUT1];
359 unsigned int ramp_delay[PALMAS_REG_SMPS10]; 405 unsigned int ramp_delay[PALMAS_REG_SMPS10_OUT1];
360 unsigned int current_reg_mode[PALMAS_REG_SMPS10]; 406 unsigned int current_reg_mode[PALMAS_REG_SMPS10_OUT1];
361}; 407};
362 408
363struct palmas_resource { 409struct palmas_resource {
@@ -371,17 +417,15 @@ struct palmas_usb {
371 417
372 struct extcon_dev edev; 418 struct extcon_dev edev;
373 419
374 /* used to set vbus, in atomic path */
375 struct work_struct set_vbus_work;
376
377 int id_otg_irq; 420 int id_otg_irq;
378 int id_irq; 421 int id_irq;
379 int vbus_otg_irq; 422 int vbus_otg_irq;
380 int vbus_irq; 423 int vbus_irq;
381 424
382 int vbus_enable;
383
384 enum palmas_usb_state linkstat; 425 enum palmas_usb_state linkstat;
426 int wakeup;
427 bool enable_vbus_detection;
428 bool enable_id_detection;
385}; 429};
386 430
387#define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator) 431#define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator)
@@ -449,7 +493,7 @@ enum usb_irq_events {
449#define PALMAS_DVFS_BASE 0x180 493#define PALMAS_DVFS_BASE 0x180
450#define PALMAS_PMU_CONTROL_BASE 0x1A0 494#define PALMAS_PMU_CONTROL_BASE 0x1A0
451#define PALMAS_RESOURCE_BASE 0x1D4 495#define PALMAS_RESOURCE_BASE 0x1D4
452#define PALMAS_PU_PD_OD_BASE 0x1F4 496#define PALMAS_PU_PD_OD_BASE 0x1F0
453#define PALMAS_LED_BASE 0x200 497#define PALMAS_LED_BASE 0x200
454#define PALMAS_INTERRUPT_BASE 0x210 498#define PALMAS_INTERRUPT_BASE 0x210
455#define PALMAS_USB_OTG_BASE 0x250 499#define PALMAS_USB_OTG_BASE 0x250
@@ -1734,16 +1778,20 @@ enum usb_irq_events {
1734#define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0 1778#define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0
1735 1779
1736/* Registers for function PAD_CONTROL */ 1780/* Registers for function PAD_CONTROL */
1737#define PALMAS_PU_PD_INPUT_CTRL1 0x0 1781#define PALMAS_OD_OUTPUT_CTRL2 0x2
1738#define PALMAS_PU_PD_INPUT_CTRL2 0x1 1782#define PALMAS_POLARITY_CTRL2 0x3
1739#define PALMAS_PU_PD_INPUT_CTRL3 0x2 1783#define PALMAS_PU_PD_INPUT_CTRL1 0x4
1740#define PALMAS_OD_OUTPUT_CTRL 0x4 1784#define PALMAS_PU_PD_INPUT_CTRL2 0x5
1741#define PALMAS_POLARITY_CTRL 0x5 1785#define PALMAS_PU_PD_INPUT_CTRL3 0x6
1742#define PALMAS_PRIMARY_SECONDARY_PAD1 0x6 1786#define PALMAS_PU_PD_INPUT_CTRL5 0x7
1743#define PALMAS_PRIMARY_SECONDARY_PAD2 0x7 1787#define PALMAS_OD_OUTPUT_CTRL 0x8
1744#define PALMAS_I2C_SPI 0x8 1788#define PALMAS_POLARITY_CTRL 0x9
1745#define PALMAS_PU_PD_INPUT_CTRL4 0x9 1789#define PALMAS_PRIMARY_SECONDARY_PAD1 0xA
1746#define PALMAS_PRIMARY_SECONDARY_PAD3 0xA 1790#define PALMAS_PRIMARY_SECONDARY_PAD2 0xB
1791#define PALMAS_I2C_SPI 0xC
1792#define PALMAS_PU_PD_INPUT_CTRL4 0xD
1793#define PALMAS_PRIMARY_SECONDARY_PAD3 0xE
1794#define PALMAS_PRIMARY_SECONDARY_PAD4 0xF
1747 1795
1748/* Bit definitions for PU_PD_INPUT_CTRL1 */ 1796/* Bit definitions for PU_PD_INPUT_CTRL1 */
1749#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40 1797#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40
@@ -2501,6 +2549,15 @@ enum usb_irq_events {
2501#define PALMAS_PU_PD_GPIO_CTRL1 0x6 2549#define PALMAS_PU_PD_GPIO_CTRL1 0x6
2502#define PALMAS_PU_PD_GPIO_CTRL2 0x7 2550#define PALMAS_PU_PD_GPIO_CTRL2 0x7
2503#define PALMAS_OD_OUTPUT_GPIO_CTRL 0x8 2551#define PALMAS_OD_OUTPUT_GPIO_CTRL 0x8
2552#define PALMAS_GPIO_DATA_IN2 0x9
2553#define PALMAS_GPIO_DATA_DIR2 0x0A
2554#define PALMAS_GPIO_DATA_OUT2 0x0B
2555#define PALMAS_GPIO_DEBOUNCE_EN2 0x0C
2556#define PALMAS_GPIO_CLEAR_DATA_OUT2 0x0D
2557#define PALMAS_GPIO_SET_DATA_OUT2 0x0E
2558#define PALMAS_PU_PD_GPIO_CTRL3 0x0F
2559#define PALMAS_PU_PD_GPIO_CTRL4 0x10
2560#define PALMAS_OD_OUTPUT_GPIO_CTRL2 0x11
2504 2561
2505/* Bit definitions for GPIO_DATA_IN */ 2562/* Bit definitions for GPIO_DATA_IN */
2506#define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80 2563#define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80
@@ -2866,4 +2923,9 @@ static inline int palmas_irq_get_virq(struct palmas *palmas, int irq)
2866 return regmap_irq_get_virq(palmas->irq_data, irq); 2923 return regmap_irq_get_virq(palmas->irq_data, irq);
2867} 2924}
2868 2925
2926
2927int palmas_ext_control_req_config(struct palmas *palmas,
2928 enum palmas_external_requestor_id ext_control_req_id,
2929 int ext_ctrl, bool enable);
2930
2869#endif /* __LINUX_MFD_PALMAS_H */ 2931#endif /* __LINUX_MFD_PALMAS_H */
diff --git a/include/linux/mfd/rtsx_common.h b/include/linux/mfd/rtsx_common.h
index 2b13970596f5..443176ee1ab0 100644
--- a/include/linux/mfd/rtsx_common.h
+++ b/include/linux/mfd/rtsx_common.h
@@ -1,6 +1,6 @@
1/* Driver for Realtek driver-based card reader 1/* Driver for Realtek driver-based card reader
2 * 2 *
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved. 3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the 6 * under the terms of the GNU General Public License as published by the
@@ -17,7 +17,6 @@
17 * 17 *
18 * Author: 18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn> 19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21 */ 20 */
22 21
23#ifndef __RTSX_COMMON_H 22#ifndef __RTSX_COMMON_H
diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h
index 7a9f7089435d..d1382dfbeff0 100644
--- a/include/linux/mfd/rtsx_pci.h
+++ b/include/linux/mfd/rtsx_pci.h
@@ -1,6 +1,6 @@
1/* Driver for Realtek PCI-Express card reader 1/* Driver for Realtek PCI-Express card reader
2 * 2 *
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved. 3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the 6 * under the terms of the GNU General Public License as published by the
@@ -17,7 +17,6 @@
17 * 17 *
18 * Author: 18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn> 19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21 */ 20 */
22 21
23#ifndef __RTSX_PCI_H 22#ifndef __RTSX_PCI_H
@@ -25,8 +24,7 @@
25 24
26#include <linux/sched.h> 25#include <linux/sched.h>
27#include <linux/pci.h> 26#include <linux/pci.h>
28 27#include <linux/mfd/rtsx_common.h>
29#include "rtsx_common.h"
30 28
31#define MAX_RW_REG_CNT 1024 29#define MAX_RW_REG_CNT 1024
32 30
@@ -184,11 +182,26 @@
184#define CARD_SHARE_BAROSSA_SD 0x01 182#define CARD_SHARE_BAROSSA_SD 0x01
185#define CARD_SHARE_BAROSSA_MS 0x02 183#define CARD_SHARE_BAROSSA_MS 0x02
186 184
185/* CARD_DRIVE_SEL */
186#define MS_DRIVE_8mA (0x01 << 6)
187#define MMC_DRIVE_8mA (0x01 << 4)
188#define XD_DRIVE_8mA (0x01 << 2)
189#define GPIO_DRIVE_8mA 0x01
190#define RTS5209_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | MMC_DRIVE_8mA |\
191 XD_DRIVE_8mA | GPIO_DRIVE_8mA)
192#define RTL8411_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | MMC_DRIVE_8mA |\
193 XD_DRIVE_8mA)
194#define RTSX_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | GPIO_DRIVE_8mA)
195
187/* SD30_DRIVE_SEL */ 196/* SD30_DRIVE_SEL */
188#define DRIVER_TYPE_A 0x05 197#define DRIVER_TYPE_A 0x05
189#define DRIVER_TYPE_B 0x03 198#define DRIVER_TYPE_B 0x03
190#define DRIVER_TYPE_C 0x02 199#define DRIVER_TYPE_C 0x02
191#define DRIVER_TYPE_D 0x01 200#define DRIVER_TYPE_D 0x01
201#define CFG_DRIVER_TYPE_A 0x02
202#define CFG_DRIVER_TYPE_B 0x03
203#define CFG_DRIVER_TYPE_C 0x01
204#define CFG_DRIVER_TYPE_D 0x00
192 205
193/* FPDCTL */ 206/* FPDCTL */
194#define SSC_POWER_DOWN 0x01 207#define SSC_POWER_DOWN 0x01
@@ -521,6 +534,10 @@
521#define SAMPLE_VAR_CLK0 (0x01 << 4) 534#define SAMPLE_VAR_CLK0 (0x01 << 4)
522#define SAMPLE_VAR_CLK1 (0x02 << 4) 535#define SAMPLE_VAR_CLK1 (0x02 << 4)
523 536
537/* HOST_SLEEP_STATE */
538#define HOST_ENTER_S1 1
539#define HOST_ENTER_S3 2
540
524#define MS_CFG 0xFD40 541#define MS_CFG 0xFD40
525#define MS_TPC 0xFD41 542#define MS_TPC 0xFD41
526#define MS_TRANS_CFG 0xFD42 543#define MS_TRANS_CFG 0xFD42
@@ -669,6 +686,7 @@
669#define PME_FORCE_CTL 0xFE56 686#define PME_FORCE_CTL 0xFE56
670#define ASPM_FORCE_CTL 0xFE57 687#define ASPM_FORCE_CTL 0xFE57
671#define PM_CLK_FORCE_CTL 0xFE58 688#define PM_CLK_FORCE_CTL 0xFE58
689#define FUNC_FORCE_CTL 0xFE59
672#define PERST_GLITCH_WIDTH 0xFE5C 690#define PERST_GLITCH_WIDTH 0xFE5C
673#define CHANGE_LINK_STATE 0xFE5B 691#define CHANGE_LINK_STATE 0xFE5B
674#define RESET_LOAD_REG 0xFE5E 692#define RESET_LOAD_REG 0xFE5E
@@ -684,6 +702,13 @@
684 702
685#define DUMMY_REG_RESET_0 0xFE90 703#define DUMMY_REG_RESET_0 0xFE90
686 704
705#define AUTOLOAD_CFG_BASE 0xFF00
706
707#define PM_CTRL1 0xFF44
708#define PM_CTRL2 0xFF45
709#define PM_CTRL3 0xFF46
710#define PM_CTRL4 0xFF47
711
687/* Memory mapping */ 712/* Memory mapping */
688#define SRAM_BASE 0xE600 713#define SRAM_BASE 0xE600
689#define RBUF_BASE 0xF400 714#define RBUF_BASE 0xF400
@@ -726,6 +751,11 @@
726#define PHY_FLD4 0x1E 751#define PHY_FLD4 0x1E
727#define PHY_DUM_REG 0x1F 752#define PHY_DUM_REG 0x1F
728 753
754#define LCTLR 0x80
755#define PCR_SETTING_REG1 0x724
756#define PCR_SETTING_REG2 0x814
757#define PCR_SETTING_REG3 0x747
758
729#define rtsx_pci_init_cmd(pcr) ((pcr)->ci = 0) 759#define rtsx_pci_init_cmd(pcr) ((pcr)->ci = 0)
730 760
731struct rtsx_pcr; 761struct rtsx_pcr;
@@ -747,6 +777,8 @@ struct pcr_ops {
747 u8 voltage); 777 u8 voltage);
748 unsigned int (*cd_deglitch)(struct rtsx_pcr *pcr); 778 unsigned int (*cd_deglitch)(struct rtsx_pcr *pcr);
749 int (*conv_clk_and_div_n)(int clk, int dir); 779 int (*conv_clk_and_div_n)(int clk, int dir);
780 void (*fetch_vendor_settings)(struct rtsx_pcr *pcr);
781 void (*force_power_down)(struct rtsx_pcr *pcr, u8 pm_state);
750}; 782};
751 783
752enum PDEV_STAT {PDEV_STAT_IDLE, PDEV_STAT_RUN}; 784enum PDEV_STAT {PDEV_STAT_IDLE, PDEV_STAT_RUN};
@@ -788,7 +820,6 @@ struct rtsx_pcr {
788 struct completion *finish_me; 820 struct completion *finish_me;
789 821
790 unsigned int cur_clock; 822 unsigned int cur_clock;
791 bool ms_pmos;
792 bool remove_pci; 823 bool remove_pci;
793 bool msi_en; 824 bool msi_en;
794 825
@@ -806,6 +837,19 @@ struct rtsx_pcr {
806#define IC_VER_D 3 837#define IC_VER_D 3
807 u8 ic_version; 838 u8 ic_version;
808 839
840 u8 sd30_drive_sel_1v8;
841 u8 sd30_drive_sel_3v3;
842 u8 card_drive_sel;
843#define ASPM_L1_EN 0x02
844 u8 aspm_en;
845
846#define PCR_MS_PMOS (1 << 0)
847#define PCR_REVERSE_SOCKET (1 << 1)
848 u32 flags;
849
850 u32 tx_initial_phase;
851 u32 rx_initial_phase;
852
809 const u32 *sd_pull_ctl_enable_tbl; 853 const u32 *sd_pull_ctl_enable_tbl;
810 const u32 *sd_pull_ctl_disable_tbl; 854 const u32 *sd_pull_ctl_disable_tbl;
811 const u32 *ms_pull_ctl_enable_tbl; 855 const u32 *ms_pull_ctl_enable_tbl;
@@ -822,6 +866,18 @@ struct rtsx_pcr {
822#define PCI_VID(pcr) ((pcr)->pci->vendor) 866#define PCI_VID(pcr) ((pcr)->pci->vendor)
823#define PCI_PID(pcr) ((pcr)->pci->device) 867#define PCI_PID(pcr) ((pcr)->pci->device)
824 868
869#define SDR104_PHASE(val) ((val) & 0xFF)
870#define SDR50_PHASE(val) (((val) >> 8) & 0xFF)
871#define DDR50_PHASE(val) (((val) >> 16) & 0xFF)
872#define SDR104_TX_PHASE(pcr) SDR104_PHASE((pcr)->tx_initial_phase)
873#define SDR50_TX_PHASE(pcr) SDR50_PHASE((pcr)->tx_initial_phase)
874#define DDR50_TX_PHASE(pcr) DDR50_PHASE((pcr)->tx_initial_phase)
875#define SDR104_RX_PHASE(pcr) SDR104_PHASE((pcr)->rx_initial_phase)
876#define SDR50_RX_PHASE(pcr) SDR50_PHASE((pcr)->rx_initial_phase)
877#define DDR50_RX_PHASE(pcr) DDR50_PHASE((pcr)->rx_initial_phase)
878#define SET_CLOCK_PHASE(sdr104, sdr50, ddr50) \
879 (((ddr50) << 16) | ((sdr50) << 8) | (sdr104))
880
825void rtsx_pci_start_run(struct rtsx_pcr *pcr); 881void rtsx_pci_start_run(struct rtsx_pcr *pcr);
826int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data); 882int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data);
827int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data); 883int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data);
diff --git a/include/linux/mfd/samsung/s2mps11.h b/include/linux/mfd/samsung/s2mps11.h
index 4e94dc65f987..b3ddf98dec37 100644
--- a/include/linux/mfd/samsung/s2mps11.h
+++ b/include/linux/mfd/samsung/s2mps11.h
@@ -167,11 +167,8 @@ enum s2mps11_regulators {
167 S2MPS11_BUCK8, 167 S2MPS11_BUCK8,
168 S2MPS11_BUCK9, 168 S2MPS11_BUCK9,
169 S2MPS11_BUCK10, 169 S2MPS11_BUCK10,
170 S2MPS11_AP_EN32KHZ,
171 S2MPS11_CP_EN32KHZ,
172 S2MPS11_BT_EN32KHZ,
173 170
174 S2MPS11_REG_MAX, 171 S2MPS11_REGULATOR_MAX,
175}; 172};
176 173
177#define S2MPS11_BUCK_MIN1 600000 174#define S2MPS11_BUCK_MIN1 600000
@@ -191,7 +188,17 @@ enum s2mps11_regulators {
191#define S2MPS11_BUCK_N_VOLTAGES (S2MPS11_BUCK_VSEL_MASK + 1) 188#define S2MPS11_BUCK_N_VOLTAGES (S2MPS11_BUCK_VSEL_MASK + 1)
192#define S2MPS11_RAMP_DELAY 25000 /* uV/us */ 189#define S2MPS11_RAMP_DELAY 25000 /* uV/us */
193 190
191
192#define S2MPS11_BUCK2_RAMP_SHIFT 6
193#define S2MPS11_BUCK34_RAMP_SHIFT 4
194#define S2MPS11_BUCK5_RAMP_SHIFT 6
195#define S2MPS11_BUCK16_RAMP_SHIFT 4
196#define S2MPS11_BUCK7810_RAMP_SHIFT 2
197#define S2MPS11_BUCK9_RAMP_SHIFT 0
198#define S2MPS11_BUCK2_RAMP_EN_SHIFT 3
199#define S2MPS11_BUCK3_RAMP_EN_SHIFT 2
200#define S2MPS11_BUCK4_RAMP_EN_SHIFT 1
201#define S2MPS11_BUCK6_RAMP_EN_SHIFT 0
194#define S2MPS11_PMIC_EN_SHIFT 6 202#define S2MPS11_PMIC_EN_SHIFT 6
195#define S2MPS11_REGULATOR_MAX (S2MPS11_REG_MAX - 3)
196 203
197#endif /* __LINUX_MFD_S2MPS11_H */ 204#endif /* __LINUX_MFD_S2MPS11_H */
diff --git a/include/linux/mfd/ti_am335x_tscadc.h b/include/linux/mfd/ti_am335x_tscadc.h
index db1791bb997a..25f2c611ab01 100644
--- a/include/linux/mfd/ti_am335x_tscadc.h
+++ b/include/linux/mfd/ti_am335x_tscadc.h
@@ -121,7 +121,6 @@
121#define SEQ_STATUS BIT(5) 121#define SEQ_STATUS BIT(5)
122 122
123#define ADC_CLK 3000000 123#define ADC_CLK 3000000
124#define MAX_CLK_DIV 7
125#define TOTAL_STEPS 16 124#define TOTAL_STEPS 16
126#define TOTAL_CHANNELS 8 125#define TOTAL_CHANNELS 8
127 126
diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h
index ce3511326f80..b22883d60500 100644
--- a/include/linux/mfd/tmio.h
+++ b/include/linux/mfd/tmio.h
@@ -108,7 +108,6 @@ struct tmio_mmc_data {
108 unsigned int cd_gpio; 108 unsigned int cd_gpio;
109 void (*set_pwr)(struct platform_device *host, int state); 109 void (*set_pwr)(struct platform_device *host, int state);
110 void (*set_clk_div)(struct platform_device *host, int state); 110 void (*set_clk_div)(struct platform_device *host, int state);
111 int (*get_cd)(struct platform_device *host);
112 int (*write16_hook)(struct tmio_mmc_host *host, int addr); 111 int (*write16_hook)(struct tmio_mmc_host *host, int addr);
113 /* clock management callbacks */ 112 /* clock management callbacks */
114 int (*clk_enable)(struct platform_device *pdev, unsigned int *f); 113 int (*clk_enable)(struct platform_device *pdev, unsigned int *f);
diff --git a/include/linux/mfd/tps65217.h b/include/linux/mfd/tps65217.h
index 29eab2bd3dfa..a5a7f0130e96 100644
--- a/include/linux/mfd/tps65217.h
+++ b/include/linux/mfd/tps65217.h
@@ -244,24 +244,6 @@ struct tps65217_board {
244}; 244};
245 245
246/** 246/**
247 * struct tps_info - packages regulator constraints
248 * @name: Voltage regulator name
249 * @min_uV: minimum micro volts
250 * @max_uV: minimum micro volts
251 * @vsel_to_uv: Function pointer to get voltage from selector
252 * @uv_to_vsel: Function pointer to get selector from voltage
253 *
254 * This data is used to check the regualtor voltage limits while setting.
255 */
256struct tps_info {
257 const char *name;
258 int min_uV;
259 int max_uV;
260 int (*vsel_to_uv)(unsigned int vsel);
261 int (*uv_to_vsel)(int uV, unsigned int *vsel);
262};
263
264/**
265 * struct tps65217 - tps65217 sub-driver chip access routines 247 * struct tps65217 - tps65217 sub-driver chip access routines
266 * 248 *
267 * Device data may be used to access the TPS65217 chip 249 * Device data may be used to access the TPS65217 chip
@@ -273,7 +255,6 @@ struct tps65217 {
273 unsigned int id; 255 unsigned int id;
274 struct regulator_desc desc[TPS65217_NUM_REGULATOR]; 256 struct regulator_desc desc[TPS65217_NUM_REGULATOR];
275 struct regulator_dev *rdev[TPS65217_NUM_REGULATOR]; 257 struct regulator_dev *rdev[TPS65217_NUM_REGULATOR];
276 struct tps_info *info[TPS65217_NUM_REGULATOR];
277 struct regmap *regmap; 258 struct regmap *regmap;
278}; 259};
279 260
diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h
index 7e7fbce7a308..81f639bc1ae6 100644
--- a/include/linux/mfd/twl6040.h
+++ b/include/linux/mfd/twl6040.h
@@ -185,6 +185,7 @@
185 185
186#define TWL6040_GPO_MAX 3 186#define TWL6040_GPO_MAX 3
187 187
188/* TODO: All platform data struct can be removed */
188struct twl6040_codec_data { 189struct twl6040_codec_data {
189 u16 hs_left_step; 190 u16 hs_left_step;
190 u16 hs_right_step; 191 u16 hs_right_step;
@@ -229,7 +230,6 @@ struct twl6040 {
229 int audpwron; 230 int audpwron;
230 int power_count; 231 int power_count;
231 int rev; 232 int rev;
232 u8 vibra_ctrl_cache[2];
233 233
234 /* PLL configuration */ 234 /* PLL configuration */
235 int pll; 235 int pll;
diff --git a/include/linux/mfd/ucb1x00.h b/include/linux/mfd/ucb1x00.h
index 28af41756360..88f90cbf8e6a 100644
--- a/include/linux/mfd/ucb1x00.h
+++ b/include/linux/mfd/ucb1x00.h
@@ -10,6 +10,7 @@
10#ifndef UCB1200_H 10#ifndef UCB1200_H
11#define UCB1200_H 11#define UCB1200_H
12 12
13#include <linux/device.h>
13#include <linux/mfd/mcp.h> 14#include <linux/mfd/mcp.h>
14#include <linux/gpio.h> 15#include <linux/gpio.h>
15#include <linux/mutex.h> 16#include <linux/mutex.h>
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-09 17:59:08 -0400