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authorLinus Torvalds <torvalds@linux-foundation.org>2014-04-07 13:24:18 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-04-07 13:24:18 -0400
commite5744abb2fa3629aa5a94e21ca1eae32ff2fe00b (patch)
treeef90c96390256b073f5255d224aecb2fc1f6ee84 /include/linux/mfd
parentc29aa153ef0469cddf0146d41ce6494bd76be78b (diff)
parent2d28ca731b9bb6262f7711241628c7844b0cf7dc (diff)
Merge tag 'mfd-for-linus-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
Pull MFD updates from Lee Jones: "Changes to existing drivers: - Use of managed resources - omap, twl4030, ti_am335x_tscadc - Advanced error handling - omap - Rework clk management - omap - Device Tree (re-)work - tc3589x, pm8921, da9055, sec - IRC management overhaul and !BROKEN - pm8921 - Convert to regmap - ssbi, pm8921 - Use simple power-management ops - ucb1x00 - Include file clean-up - adp5520, cs5535, janz, lpc_ich, - lpc_sch, max14577, mcp-sa11x0, pcf50633-adc, rc5t583, rdc321x-southbridge, retu, smsc-ece1099, ti-ssp, ti_am335x_tscadc, tps65912, vexpress-config, wm8350, ywm8350 - Various bug fixes across the subsystem - NULL/invalid pointer dereference prevention - Resource leak mitigation, - Variable used initialised - Staticise various containers - Enforce return value checks New drivers/supported devices: - Add support for s2mps14 and s2mpa01 to sec - Add support for da9063 (v5) to da9063 - Add support for atom-c2000 to gpio-ich - Add support for come-{mbt10,cbt6,chl6} to kempld - Add support for da9053 to da9052 - Add support for itco-wdt (v3) and baytrail to lpc_ich - Add new drivers for tps65218, rtsx_usb, bcm590xx (Re-)moved drivers: - twl4030 ==> drivers/iio - ti-ssp ==> /dev/null" * tag 'mfd-for-linus-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (103 commits) mfd: wm5110: Correct default for HEADPHONE_DETECT_1 mfd: arizona: Correct small errors in the DT binding documentation mfd: arizona: Mark DSP clocking register as volatile mfd: devicetree: bindings: Add pm8xxx RTC description mfd: kempld-core: Fix potential hang-up during boot mfd: sec-core: Fix uninitialized 'regmap_rtc' on S2MPA01 mfd: tps65910: Fix regmap_irq_chip_data leak on mfd_add_devices fail mfd: tps65910: Fix possible invalid pointer dereference on regmap_add_irq_chip fail mfd: sec-core: Fix I2C dummy device resource leak on probe failure mfd: sec-core: Add of_compatible strings for clock MFD cells mfd: Remove obsolete ti-ssp driver Documentation: mfd: s2mps11: Describe S5M8767 and S2MPS14 clocks mfd: bcm590xx: Fix type argument for module device table mfd: lpc_ich: Add support for Intel Bay Trail SoC mfd: lpc_ich: Add support for NM10 GPIO mfd: lpc_ich: Change Avoton to iTCO v3 watchdog: iTCO_wdt: Add support for v3 silicon mfd: lpc_ich: Add support for iTCO v3 mfd: lpc_ich: Remove lpc_ich_cfg struct use mfd: lpc_ich: Only configure watchdog or GPIO when present ...
Diffstat (limited to 'include/linux/mfd')
-rw-r--r--include/linux/mfd/arizona/registers.h84
-rw-r--r--include/linux/mfd/bcm590xx.h31
-rw-r--r--include/linux/mfd/da9052/da9052.h1
-rw-r--r--include/linux/mfd/da9063/core.h6
-rw-r--r--include/linux/mfd/da9063/registers.h120
-rw-r--r--include/linux/mfd/lpc_ich.h25
-rw-r--r--include/linux/mfd/max14577-private.h8
-rw-r--r--include/linux/mfd/max14577.h5
-rw-r--r--include/linux/mfd/pm8xxx/irq.h59
-rw-r--r--include/linux/mfd/pm8xxx/pm8921.h30
-rw-r--r--include/linux/mfd/rtsx_usb.h628
-rw-r--r--include/linux/mfd/tps65218.h284
12 files changed, 1109 insertions, 172 deletions
diff --git a/include/linux/mfd/arizona/registers.h b/include/linux/mfd/arizona/registers.h
index 3ddaa634b19d..7b35c21170d5 100644
--- a/include/linux/mfd/arizona/registers.h
+++ b/include/linux/mfd/arizona/registers.h
@@ -1034,6 +1034,27 @@
1034#define ARIZONA_DSP1_STATUS_1 0x1104 1034#define ARIZONA_DSP1_STATUS_1 0x1104
1035#define ARIZONA_DSP1_STATUS_2 0x1105 1035#define ARIZONA_DSP1_STATUS_2 0x1105
1036#define ARIZONA_DSP1_STATUS_3 0x1106 1036#define ARIZONA_DSP1_STATUS_3 0x1106
1037#define ARIZONA_DSP1_STATUS_4 0x1107
1038#define ARIZONA_DSP1_WDMA_BUFFER_1 0x1110
1039#define ARIZONA_DSP1_WDMA_BUFFER_2 0x1111
1040#define ARIZONA_DSP1_WDMA_BUFFER_3 0x1112
1041#define ARIZONA_DSP1_WDMA_BUFFER_4 0x1113
1042#define ARIZONA_DSP1_WDMA_BUFFER_5 0x1114
1043#define ARIZONA_DSP1_WDMA_BUFFER_6 0x1115
1044#define ARIZONA_DSP1_WDMA_BUFFER_7 0x1116
1045#define ARIZONA_DSP1_WDMA_BUFFER_8 0x1117
1046#define ARIZONA_DSP1_RDMA_BUFFER_1 0x1120
1047#define ARIZONA_DSP1_RDMA_BUFFER_2 0x1121
1048#define ARIZONA_DSP1_RDMA_BUFFER_3 0x1122
1049#define ARIZONA_DSP1_RDMA_BUFFER_4 0x1123
1050#define ARIZONA_DSP1_RDMA_BUFFER_5 0x1124
1051#define ARIZONA_DSP1_RDMA_BUFFER_6 0x1125
1052#define ARIZONA_DSP1_WDMA_CONFIG_1 0x1130
1053#define ARIZONA_DSP1_WDMA_CONFIG_2 0x1131
1054#define ARIZONA_DSP1_WDMA_OFFSET_1 0x1132
1055#define ARIZONA_DSP1_RDMA_CONFIG_1 0x1134
1056#define ARIZONA_DSP1_RDMA_OFFSET_1 0x1135
1057#define ARIZONA_DSP1_EXTERNAL_START_SELECT_1 0x1138
1037#define ARIZONA_DSP1_SCRATCH_0 0x1140 1058#define ARIZONA_DSP1_SCRATCH_0 0x1140
1038#define ARIZONA_DSP1_SCRATCH_1 0x1141 1059#define ARIZONA_DSP1_SCRATCH_1 0x1141
1039#define ARIZONA_DSP1_SCRATCH_2 0x1142 1060#define ARIZONA_DSP1_SCRATCH_2 0x1142
@@ -1043,6 +1064,27 @@
1043#define ARIZONA_DSP2_STATUS_1 0x1204 1064#define ARIZONA_DSP2_STATUS_1 0x1204
1044#define ARIZONA_DSP2_STATUS_2 0x1205 1065#define ARIZONA_DSP2_STATUS_2 0x1205
1045#define ARIZONA_DSP2_STATUS_3 0x1206 1066#define ARIZONA_DSP2_STATUS_3 0x1206
1067#define ARIZONA_DSP2_STATUS_4 0x1207
1068#define ARIZONA_DSP2_WDMA_BUFFER_1 0x1210
1069#define ARIZONA_DSP2_WDMA_BUFFER_2 0x1211
1070#define ARIZONA_DSP2_WDMA_BUFFER_3 0x1212
1071#define ARIZONA_DSP2_WDMA_BUFFER_4 0x1213
1072#define ARIZONA_DSP2_WDMA_BUFFER_5 0x1214
1073#define ARIZONA_DSP2_WDMA_BUFFER_6 0x1215
1074#define ARIZONA_DSP2_WDMA_BUFFER_7 0x1216
1075#define ARIZONA_DSP2_WDMA_BUFFER_8 0x1217
1076#define ARIZONA_DSP2_RDMA_BUFFER_1 0x1220
1077#define ARIZONA_DSP2_RDMA_BUFFER_2 0x1221
1078#define ARIZONA_DSP2_RDMA_BUFFER_3 0x1222
1079#define ARIZONA_DSP2_RDMA_BUFFER_4 0x1223
1080#define ARIZONA_DSP2_RDMA_BUFFER_5 0x1224
1081#define ARIZONA_DSP2_RDMA_BUFFER_6 0x1225
1082#define ARIZONA_DSP2_WDMA_CONFIG_1 0x1230
1083#define ARIZONA_DSP2_WDMA_CONFIG_2 0x1231
1084#define ARIZONA_DSP2_WDMA_OFFSET_1 0x1232
1085#define ARIZONA_DSP2_RDMA_CONFIG_1 0x1234
1086#define ARIZONA_DSP2_RDMA_OFFSET_1 0x1235
1087#define ARIZONA_DSP2_EXTERNAL_START_SELECT_1 0x1238
1046#define ARIZONA_DSP2_SCRATCH_0 0x1240 1088#define ARIZONA_DSP2_SCRATCH_0 0x1240
1047#define ARIZONA_DSP2_SCRATCH_1 0x1241 1089#define ARIZONA_DSP2_SCRATCH_1 0x1241
1048#define ARIZONA_DSP2_SCRATCH_2 0x1242 1090#define ARIZONA_DSP2_SCRATCH_2 0x1242
@@ -1052,6 +1094,27 @@
1052#define ARIZONA_DSP3_STATUS_1 0x1304 1094#define ARIZONA_DSP3_STATUS_1 0x1304
1053#define ARIZONA_DSP3_STATUS_2 0x1305 1095#define ARIZONA_DSP3_STATUS_2 0x1305
1054#define ARIZONA_DSP3_STATUS_3 0x1306 1096#define ARIZONA_DSP3_STATUS_3 0x1306
1097#define ARIZONA_DSP3_STATUS_4 0x1307
1098#define ARIZONA_DSP3_WDMA_BUFFER_1 0x1310
1099#define ARIZONA_DSP3_WDMA_BUFFER_2 0x1311
1100#define ARIZONA_DSP3_WDMA_BUFFER_3 0x1312
1101#define ARIZONA_DSP3_WDMA_BUFFER_4 0x1313
1102#define ARIZONA_DSP3_WDMA_BUFFER_5 0x1314
1103#define ARIZONA_DSP3_WDMA_BUFFER_6 0x1315
1104#define ARIZONA_DSP3_WDMA_BUFFER_7 0x1316
1105#define ARIZONA_DSP3_WDMA_BUFFER_8 0x1317
1106#define ARIZONA_DSP3_RDMA_BUFFER_1 0x1320
1107#define ARIZONA_DSP3_RDMA_BUFFER_2 0x1321
1108#define ARIZONA_DSP3_RDMA_BUFFER_3 0x1322
1109#define ARIZONA_DSP3_RDMA_BUFFER_4 0x1323
1110#define ARIZONA_DSP3_RDMA_BUFFER_5 0x1324
1111#define ARIZONA_DSP3_RDMA_BUFFER_6 0x1325
1112#define ARIZONA_DSP3_WDMA_CONFIG_1 0x1330
1113#define ARIZONA_DSP3_WDMA_CONFIG_2 0x1331
1114#define ARIZONA_DSP3_WDMA_OFFSET_1 0x1332
1115#define ARIZONA_DSP3_RDMA_CONFIG_1 0x1334
1116#define ARIZONA_DSP3_RDMA_OFFSET_1 0x1335
1117#define ARIZONA_DSP3_EXTERNAL_START_SELECT_1 0x1338
1055#define ARIZONA_DSP3_SCRATCH_0 0x1340 1118#define ARIZONA_DSP3_SCRATCH_0 0x1340
1056#define ARIZONA_DSP3_SCRATCH_1 0x1341 1119#define ARIZONA_DSP3_SCRATCH_1 0x1341
1057#define ARIZONA_DSP3_SCRATCH_2 0x1342 1120#define ARIZONA_DSP3_SCRATCH_2 0x1342
@@ -1061,6 +1124,27 @@
1061#define ARIZONA_DSP4_STATUS_1 0x1404 1124#define ARIZONA_DSP4_STATUS_1 0x1404
1062#define ARIZONA_DSP4_STATUS_2 0x1405 1125#define ARIZONA_DSP4_STATUS_2 0x1405
1063#define ARIZONA_DSP4_STATUS_3 0x1406 1126#define ARIZONA_DSP4_STATUS_3 0x1406
1127#define ARIZONA_DSP4_STATUS_4 0x1407
1128#define ARIZONA_DSP4_WDMA_BUFFER_1 0x1410
1129#define ARIZONA_DSP4_WDMA_BUFFER_2 0x1411
1130#define ARIZONA_DSP4_WDMA_BUFFER_3 0x1412
1131#define ARIZONA_DSP4_WDMA_BUFFER_4 0x1413
1132#define ARIZONA_DSP4_WDMA_BUFFER_5 0x1414
1133#define ARIZONA_DSP4_WDMA_BUFFER_6 0x1415
1134#define ARIZONA_DSP4_WDMA_BUFFER_7 0x1416
1135#define ARIZONA_DSP4_WDMA_BUFFER_8 0x1417
1136#define ARIZONA_DSP4_RDMA_BUFFER_1 0x1420
1137#define ARIZONA_DSP4_RDMA_BUFFER_2 0x1421
1138#define ARIZONA_DSP4_RDMA_BUFFER_3 0x1422
1139#define ARIZONA_DSP4_RDMA_BUFFER_4 0x1423
1140#define ARIZONA_DSP4_RDMA_BUFFER_5 0x1424
1141#define ARIZONA_DSP4_RDMA_BUFFER_6 0x1425
1142#define ARIZONA_DSP4_WDMA_CONFIG_1 0x1430
1143#define ARIZONA_DSP4_WDMA_CONFIG_2 0x1431
1144#define ARIZONA_DSP4_WDMA_OFFSET_1 0x1432
1145#define ARIZONA_DSP4_RDMA_CONFIG_1 0x1434
1146#define ARIZONA_DSP4_RDMA_OFFSET_1 0x1435
1147#define ARIZONA_DSP4_EXTERNAL_START_SELECT_1 0x1438
1064#define ARIZONA_DSP4_SCRATCH_0 0x1440 1148#define ARIZONA_DSP4_SCRATCH_0 0x1440
1065#define ARIZONA_DSP4_SCRATCH_1 0x1441 1149#define ARIZONA_DSP4_SCRATCH_1 0x1441
1066#define ARIZONA_DSP4_SCRATCH_2 0x1442 1150#define ARIZONA_DSP4_SCRATCH_2 0x1442
diff --git a/include/linux/mfd/bcm590xx.h b/include/linux/mfd/bcm590xx.h
new file mode 100644
index 000000000000..434df2d4e587
--- /dev/null
+++ b/include/linux/mfd/bcm590xx.h
@@ -0,0 +1,31 @@
1/*
2 * Broadcom BCM590xx PMU
3 *
4 * Copyright 2014 Linaro Limited
5 * Author: Matt Porter <mporter@linaro.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14#ifndef __LINUX_MFD_BCM590XX_H
15#define __LINUX_MFD_BCM590XX_H
16
17#include <linux/device.h>
18#include <linux/i2c.h>
19#include <linux/regmap.h>
20
21/* max register address */
22#define BCM590XX_MAX_REGISTER 0xe7
23
24struct bcm590xx {
25 struct device *dev;
26 struct i2c_client *i2c_client;
27 struct regmap *regmap;
28 unsigned int id;
29};
30
31#endif /* __LINUX_MFD_BCM590XX_H */
diff --git a/include/linux/mfd/da9052/da9052.h b/include/linux/mfd/da9052/da9052.h
index 21e21b81cc75..bba65f51a0b5 100644
--- a/include/linux/mfd/da9052/da9052.h
+++ b/include/linux/mfd/da9052/da9052.h
@@ -83,6 +83,7 @@ enum da9052_chip_id {
83 DA9053_AA, 83 DA9053_AA,
84 DA9053_BA, 84 DA9053_BA,
85 DA9053_BB, 85 DA9053_BB,
86 DA9053_BC,
86}; 87};
87 88
88struct da9052_pdata; 89struct da9052_pdata;
diff --git a/include/linux/mfd/da9063/core.h b/include/linux/mfd/da9063/core.h
index 2d2a0af675fd..00a9aac5d1e8 100644
--- a/include/linux/mfd/da9063/core.h
+++ b/include/linux/mfd/da9063/core.h
@@ -33,6 +33,10 @@ enum da9063_models {
33 PMIC_DA9063 = 0x61, 33 PMIC_DA9063 = 0x61,
34}; 34};
35 35
36enum da9063_variant_codes {
37 PMIC_DA9063_BB = 0x5
38};
39
36/* Interrupts */ 40/* Interrupts */
37enum da9063_irqs { 41enum da9063_irqs {
38 DA9063_IRQ_ONKEY = 0, 42 DA9063_IRQ_ONKEY = 0,
@@ -72,7 +76,7 @@ struct da9063 {
72 /* Device */ 76 /* Device */
73 struct device *dev; 77 struct device *dev;
74 unsigned short model; 78 unsigned short model;
75 unsigned short revision; 79 unsigned char variant_code;
76 unsigned int flags; 80 unsigned int flags;
77 81
78 /* Control interface */ 82 /* Control interface */
diff --git a/include/linux/mfd/da9063/registers.h b/include/linux/mfd/da9063/registers.h
index 5834813fb5f3..09a85c699da1 100644
--- a/include/linux/mfd/da9063/registers.h
+++ b/include/linux/mfd/da9063/registers.h
@@ -17,11 +17,7 @@
17#define _DA9063_REG_H 17#define _DA9063_REG_H
18 18
19#define DA9063_I2C_PAGE_SEL_SHIFT 1 19#define DA9063_I2C_PAGE_SEL_SHIFT 1
20
21#define DA9063_EVENT_REG_NUM 4 20#define DA9063_EVENT_REG_NUM 4
22#define DA9210_EVENT_REG_NUM 2
23#define DA9063_EXT_EVENT_REG_NUM (DA9063_EVENT_REG_NUM + \
24 DA9210_EVENT_REG_NUM)
25 21
26/* Page selection I2C or SPI always in the begining of any page. */ 22/* Page selection I2C or SPI always in the begining of any page. */
27/* Page 0 : I2C access 0x000 - 0x0FF SPI access 0x000 - 0x07F */ 23/* Page 0 : I2C access 0x000 - 0x0FF SPI access 0x000 - 0x07F */
@@ -61,9 +57,9 @@
61#define DA9063_REG_GPIO_10_11 0x1A 57#define DA9063_REG_GPIO_10_11 0x1A
62#define DA9063_REG_GPIO_12_13 0x1B 58#define DA9063_REG_GPIO_12_13 0x1B
63#define DA9063_REG_GPIO_14_15 0x1C 59#define DA9063_REG_GPIO_14_15 0x1C
64#define DA9063_REG_GPIO_MODE_0_7 0x1D 60#define DA9063_REG_GPIO_MODE0_7 0x1D
65#define DA9063_REG_GPIO_MODE_8_15 0x1E 61#define DA9063_REG_GPIO_MODE8_15 0x1E
66#define DA9063_REG_GPIO_SWITCH_CONT 0x1F 62#define DA9063_REG_SWITCH_CONT 0x1F
67 63
68/* Regulator Control Registers */ 64/* Regulator Control Registers */
69#define DA9063_REG_BCORE2_CONT 0x20 65#define DA9063_REG_BCORE2_CONT 0x20
@@ -83,7 +79,7 @@
83#define DA9063_REG_LDO9_CONT 0x2E 79#define DA9063_REG_LDO9_CONT 0x2E
84#define DA9063_REG_LDO10_CONT 0x2F 80#define DA9063_REG_LDO10_CONT 0x2F
85#define DA9063_REG_LDO11_CONT 0x30 81#define DA9063_REG_LDO11_CONT 0x30
86#define DA9063_REG_VIB 0x31 82#define DA9063_REG_SUPPLIES 0x31
87#define DA9063_REG_DVC_1 0x32 83#define DA9063_REG_DVC_1 0x32
88#define DA9063_REG_DVC_2 0x33 84#define DA9063_REG_DVC_2 0x33
89 85
@@ -97,9 +93,9 @@
97#define DA9063_REG_ADCIN1_RES 0x3A 93#define DA9063_REG_ADCIN1_RES 0x3A
98#define DA9063_REG_ADCIN2_RES 0x3B 94#define DA9063_REG_ADCIN2_RES 0x3B
99#define DA9063_REG_ADCIN3_RES 0x3C 95#define DA9063_REG_ADCIN3_RES 0x3C
100#define DA9063_REG_MON1_RES 0x3D 96#define DA9063_REG_MON_A8_RES 0x3D
101#define DA9063_REG_MON2_RES 0x3E 97#define DA9063_REG_MON_A9_RES 0x3E
102#define DA9063_REG_MON3_RES 0x3F 98#define DA9063_REG_MON_A10_RES 0x3F
103 99
104/* RTC Calendar and Alarm Registers */ 100/* RTC Calendar and Alarm Registers */
105#define DA9063_REG_COUNT_S 0x40 101#define DA9063_REG_COUNT_S 0x40
@@ -108,15 +104,16 @@
108#define DA9063_REG_COUNT_D 0x43 104#define DA9063_REG_COUNT_D 0x43
109#define DA9063_REG_COUNT_MO 0x44 105#define DA9063_REG_COUNT_MO 0x44
110#define DA9063_REG_COUNT_Y 0x45 106#define DA9063_REG_COUNT_Y 0x45
111#define DA9063_REG_ALARM_MI 0x46 107#define DA9063_REG_ALARM_S 0x46
112#define DA9063_REG_ALARM_H 0x47 108#define DA9063_REG_ALARM_MI 0x47
113#define DA9063_REG_ALARM_D 0x48 109#define DA9063_REG_ALARM_H 0x48
114#define DA9063_REG_ALARM_MO 0x49 110#define DA9063_REG_ALARM_D 0x49
115#define DA9063_REG_ALARM_Y 0x4A 111#define DA9063_REG_ALARM_MO 0x4A
116#define DA9063_REG_SECOND_A 0x4B 112#define DA9063_REG_ALARM_Y 0x4B
117#define DA9063_REG_SECOND_B 0x4C 113#define DA9063_REG_SECOND_A 0x4C
118#define DA9063_REG_SECOND_C 0x4D 114#define DA9063_REG_SECOND_B 0x4D
119#define DA9063_REG_SECOND_D 0x4E 115#define DA9063_REG_SECOND_C 0x4E
116#define DA9063_REG_SECOND_D 0x4F
120 117
121/* Sequencer Control Registers */ 118/* Sequencer Control Registers */
122#define DA9063_REG_SEQ 0x81 119#define DA9063_REG_SEQ 0x81
@@ -226,35 +223,37 @@
226#define DA9063_REG_CONFIG_J 0x10F 223#define DA9063_REG_CONFIG_J 0x10F
227#define DA9063_REG_CONFIG_K 0x110 224#define DA9063_REG_CONFIG_K 0x110
228#define DA9063_REG_CONFIG_L 0x111 225#define DA9063_REG_CONFIG_L 0x111
229#define DA9063_REG_MON_REG_1 0x112 226#define DA9063_REG_CONFIG_M 0x112
230#define DA9063_REG_MON_REG_2 0x113 227#define DA9063_REG_CONFIG_N 0x113
231#define DA9063_REG_MON_REG_3 0x114 228
232#define DA9063_REG_MON_REG_4 0x115 229#define DA9063_REG_MON_REG_1 0x114
233#define DA9063_REG_MON_REG_5 0x116 230#define DA9063_REG_MON_REG_2 0x115
234#define DA9063_REG_MON_REG_6 0x117 231#define DA9063_REG_MON_REG_3 0x116
235#define DA9063_REG_TRIM_CLDR 0x118 232#define DA9063_REG_MON_REG_4 0x117
236 233#define DA9063_REG_MON_REG_5 0x11E
234#define DA9063_REG_MON_REG_6 0x11F
235#define DA9063_REG_TRIM_CLDR 0x120
237/* General Purpose Registers */ 236/* General Purpose Registers */
238#define DA9063_REG_GP_ID_0 0x119 237#define DA9063_REG_GP_ID_0 0x121
239#define DA9063_REG_GP_ID_1 0x11A 238#define DA9063_REG_GP_ID_1 0x122
240#define DA9063_REG_GP_ID_2 0x11B 239#define DA9063_REG_GP_ID_2 0x123
241#define DA9063_REG_GP_ID_3 0x11C 240#define DA9063_REG_GP_ID_3 0x124
242#define DA9063_REG_GP_ID_4 0x11D 241#define DA9063_REG_GP_ID_4 0x125
243#define DA9063_REG_GP_ID_5 0x11E 242#define DA9063_REG_GP_ID_5 0x126
244#define DA9063_REG_GP_ID_6 0x11F 243#define DA9063_REG_GP_ID_6 0x127
245#define DA9063_REG_GP_ID_7 0x120 244#define DA9063_REG_GP_ID_7 0x128
246#define DA9063_REG_GP_ID_8 0x121 245#define DA9063_REG_GP_ID_8 0x129
247#define DA9063_REG_GP_ID_9 0x122 246#define DA9063_REG_GP_ID_9 0x12A
248#define DA9063_REG_GP_ID_10 0x123 247#define DA9063_REG_GP_ID_10 0x12B
249#define DA9063_REG_GP_ID_11 0x124 248#define DA9063_REG_GP_ID_11 0x12C
250#define DA9063_REG_GP_ID_12 0x125 249#define DA9063_REG_GP_ID_12 0x12D
251#define DA9063_REG_GP_ID_13 0x126 250#define DA9063_REG_GP_ID_13 0x12E
252#define DA9063_REG_GP_ID_14 0x127 251#define DA9063_REG_GP_ID_14 0x12F
253#define DA9063_REG_GP_ID_15 0x128 252#define DA9063_REG_GP_ID_15 0x130
254#define DA9063_REG_GP_ID_16 0x129 253#define DA9063_REG_GP_ID_16 0x131
255#define DA9063_REG_GP_ID_17 0x12A 254#define DA9063_REG_GP_ID_17 0x132
256#define DA9063_REG_GP_ID_18 0x12B 255#define DA9063_REG_GP_ID_18 0x133
257#define DA9063_REG_GP_ID_19 0x12C 256#define DA9063_REG_GP_ID_19 0x134
258 257
259/* Chip ID and variant */ 258/* Chip ID and variant */
260#define DA9063_REG_CHIP_ID 0x181 259#define DA9063_REG_CHIP_ID 0x181
@@ -405,8 +404,10 @@
405/* DA9063_REG_CONTROL_B (addr=0x0F) */ 404/* DA9063_REG_CONTROL_B (addr=0x0F) */
406#define DA9063_CHG_SEL 0x01 405#define DA9063_CHG_SEL 0x01
407#define DA9063_WATCHDOG_PD 0x02 406#define DA9063_WATCHDOG_PD 0x02
407#define DA9063_RESET_BLINKING 0x04
408#define DA9063_NRES_MODE 0x08 408#define DA9063_NRES_MODE 0x08
409#define DA9063_NONKEY_LOCK 0x10 409#define DA9063_NONKEY_LOCK 0x10
410#define DA9063_BUCK_SLOWSTART 0x80
410 411
411/* DA9063_REG_CONTROL_C (addr=0x10) */ 412/* DA9063_REG_CONTROL_C (addr=0x10) */
412#define DA9063_DEBOUNCING_MASK 0x07 413#define DA9063_DEBOUNCING_MASK 0x07
@@ -466,6 +467,7 @@
466#define DA9063_GPADC_PAUSE 0x02 467#define DA9063_GPADC_PAUSE 0x02
467#define DA9063_PMIF_DIS 0x04 468#define DA9063_PMIF_DIS 0x04
468#define DA9063_HS2WIRE_DIS 0x08 469#define DA9063_HS2WIRE_DIS 0x08
470#define DA9063_CLDR_PAUSE 0x10
469#define DA9063_BBAT_DIS 0x20 471#define DA9063_BBAT_DIS 0x20
470#define DA9063_OUT_32K_PAUSE 0x40 472#define DA9063_OUT_32K_PAUSE 0x40
471#define DA9063_PMCONT_DIS 0x80 473#define DA9063_PMCONT_DIS 0x80
@@ -660,7 +662,7 @@
660#define DA9063_GPIO15_TYPE_GPO 0x04 662#define DA9063_GPIO15_TYPE_GPO 0x04
661#define DA9063_GPIO15_NO_WAKEUP 0x80 663#define DA9063_GPIO15_NO_WAKEUP 0x80
662 664
663/* DA9063_REG_GPIO_MODE_0_7 (addr=0x1D) */ 665/* DA9063_REG_GPIO_MODE0_7 (addr=0x1D) */
664#define DA9063_GPIO0_MODE 0x01 666#define DA9063_GPIO0_MODE 0x01
665#define DA9063_GPIO1_MODE 0x02 667#define DA9063_GPIO1_MODE 0x02
666#define DA9063_GPIO2_MODE 0x04 668#define DA9063_GPIO2_MODE 0x04
@@ -670,7 +672,7 @@
670#define DA9063_GPIO6_MODE 0x40 672#define DA9063_GPIO6_MODE 0x40
671#define DA9063_GPIO7_MODE 0x80 673#define DA9063_GPIO7_MODE 0x80
672 674
673/* DA9063_REG_GPIO_MODE_8_15 (addr=0x1E) */ 675/* DA9063_REG_GPIO_MODE8_15 (addr=0x1E) */
674#define DA9063_GPIO8_MODE 0x01 676#define DA9063_GPIO8_MODE 0x01
675#define DA9063_GPIO9_MODE 0x02 677#define DA9063_GPIO9_MODE 0x02
676#define DA9063_GPIO10_MODE 0x04 678#define DA9063_GPIO10_MODE 0x04
@@ -702,12 +704,12 @@
702#define DA9063_SWITCH_SR_5MV 0x10 704#define DA9063_SWITCH_SR_5MV 0x10
703#define DA9063_SWITCH_SR_10MV 0x20 705#define DA9063_SWITCH_SR_10MV 0x20
704#define DA9063_SWITCH_SR_50MV 0x30 706#define DA9063_SWITCH_SR_50MV 0x30
705#define DA9063_SWITCH_SR_DIS 0x40 707#define DA9063_CORE_SW_INTERNAL 0x40
706#define DA9063_CP_EN_MODE 0x80 708#define DA9063_CP_EN_MODE 0x80
707 709
708/* DA9063_REGL_Bxxxx_CONT common bits (addr=0x20-0x25) */ 710/* DA9063_REGL_Bxxxx_CONT common bits (addr=0x20-0x25) */
709#define DA9063_BUCK_EN 0x01 711#define DA9063_BUCK_EN 0x01
710#define DA9063_BUCK_GPI_MASK 0x06 712#define DA9063_BUCK_GPI_MASK 0x06
711#define DA9063_BUCK_GPI_OFF 0x00 713#define DA9063_BUCK_GPI_OFF 0x00
712#define DA9063_BUCK_GPI_GPIO1 0x02 714#define DA9063_BUCK_GPI_GPIO1 0x02
713#define DA9063_BUCK_GPI_GPIO2 0x04 715#define DA9063_BUCK_GPI_GPIO2 0x04
@@ -841,25 +843,27 @@
841#define DA9063_COUNT_YEAR_MASK 0x3F 843#define DA9063_COUNT_YEAR_MASK 0x3F
842#define DA9063_MONITOR 0x40 844#define DA9063_MONITOR 0x40
843 845
844/* DA9063_REG_ALARM_MI (addr=0x46) */ 846/* DA9063_REG_ALARM_S (addr=0x46) */
847#define DA9063_ALARM_S_MASK 0x3F
845#define DA9063_ALARM_STATUS_ALARM 0x80 848#define DA9063_ALARM_STATUS_ALARM 0x80
846#define DA9063_ALARM_STATUS_TICK 0x40 849#define DA9063_ALARM_STATUS_TICK 0x40
850/* DA9063_REG_ALARM_MI (addr=0x47) */
847#define DA9063_ALARM_MIN_MASK 0x3F 851#define DA9063_ALARM_MIN_MASK 0x3F
848 852
849/* DA9063_REG_ALARM_H (addr=0x47) */ 853/* DA9063_REG_ALARM_H (addr=0x48) */
850#define DA9063_ALARM_HOUR_MASK 0x1F 854#define DA9063_ALARM_HOUR_MASK 0x1F
851 855
852/* DA9063_REG_ALARM_D (addr=0x48) */ 856/* DA9063_REG_ALARM_D (addr=0x49) */
853#define DA9063_ALARM_DAY_MASK 0x1F 857#define DA9063_ALARM_DAY_MASK 0x1F
854 858
855/* DA9063_REG_ALARM_MO (addr=0x49) */ 859/* DA9063_REG_ALARM_MO (addr=0x4A) */
856#define DA9063_TICK_WAKE 0x20 860#define DA9063_TICK_WAKE 0x20
857#define DA9063_TICK_TYPE 0x10 861#define DA9063_TICK_TYPE 0x10
858#define DA9063_TICK_TYPE_SEC 0x00 862#define DA9063_TICK_TYPE_SEC 0x00
859#define DA9063_TICK_TYPE_MIN 0x10 863#define DA9063_TICK_TYPE_MIN 0x10
860#define DA9063_ALARM_MONTH_MASK 0x0F 864#define DA9063_ALARM_MONTH_MASK 0x0F
861 865
862/* DA9063_REG_ALARM_Y (addr=0x4A) */ 866/* DA9063_REG_ALARM_Y (addr=0x4B) */
863#define DA9063_TICK_ON 0x80 867#define DA9063_TICK_ON 0x80
864#define DA9063_ALARM_ON 0x40 868#define DA9063_ALARM_ON 0x40
865#define DA9063_ALARM_YEAR_MASK 0x3F 869#define DA9063_ALARM_YEAR_MASK 0x3F
@@ -906,7 +910,7 @@
906 910
907/* DA9063_REG_Bxxxx_CFG common bits (addr=0x9D-0xA2) */ 911/* DA9063_REG_Bxxxx_CFG common bits (addr=0x9D-0xA2) */
908#define DA9063_BUCK_FB_MASK 0x07 912#define DA9063_BUCK_FB_MASK 0x07
909#define DA9063_BUCK_PD_DIS_SHIFT 5 913#define DA9063_BUCK_PD_DIS_MASK 0x20
910#define DA9063_BUCK_MODE_MASK 0xC0 914#define DA9063_BUCK_MODE_MASK 0xC0
911#define DA9063_BUCK_MODE_MANUAL 0x00 915#define DA9063_BUCK_MODE_MANUAL 0x00
912#define DA9063_BUCK_MODE_SLEEP 0x40 916#define DA9063_BUCK_MODE_SLEEP 0x40
diff --git a/include/linux/mfd/lpc_ich.h b/include/linux/mfd/lpc_ich.h
index 3e1df644c407..8feac782fa83 100644
--- a/include/linux/mfd/lpc_ich.h
+++ b/include/linux/mfd/lpc_ich.h
@@ -21,23 +21,26 @@
21#define LPC_ICH_H 21#define LPC_ICH_H
22 22
23/* Watchdog resources */ 23/* Watchdog resources */
24#define ICH_RES_IO_TCO 0 24#define ICH_RES_IO_TCO 0
25#define ICH_RES_IO_SMI 1 25#define ICH_RES_IO_SMI 1
26#define ICH_RES_MEM_OFF 2 26#define ICH_RES_MEM_OFF 2
27#define ICH_RES_MEM_GCS 0 27#define ICH_RES_MEM_GCS_PMC 0
28 28
29/* GPIO resources */ 29/* GPIO resources */
30#define ICH_RES_GPIO 0 30#define ICH_RES_GPIO 0
31#define ICH_RES_GPE0 1 31#define ICH_RES_GPE0 1
32 32
33/* GPIO compatibility */ 33/* GPIO compatibility */
34#define ICH_I3100_GPIO 0x401 34enum {
35#define ICH_V5_GPIO 0x501 35 ICH_I3100_GPIO,
36#define ICH_V6_GPIO 0x601 36 ICH_V5_GPIO,
37#define ICH_V7_GPIO 0x701 37 ICH_V6_GPIO,
38#define ICH_V9_GPIO 0x801 38 ICH_V7_GPIO,
39#define ICH_V10CORP_GPIO 0xa01 39 ICH_V9_GPIO,
40#define ICH_V10CONS_GPIO 0xa11 40 ICH_V10CORP_GPIO,
41 ICH_V10CONS_GPIO,
42 AVOTON_GPIO,
43};
41 44
42struct lpc_ich_info { 45struct lpc_ich_info {
43 char name[32]; 46 char name[32];
diff --git a/include/linux/mfd/max14577-private.h b/include/linux/mfd/max14577-private.h
index a3d0185196d3..c9b332fb0d5d 100644
--- a/include/linux/mfd/max14577-private.h
+++ b/include/linux/mfd/max14577-private.h
@@ -248,14 +248,6 @@ enum max14577_charger_reg {
248/* MAX14577 regulator SFOUT LDO voltage, fixed, uV */ 248/* MAX14577 regulator SFOUT LDO voltage, fixed, uV */
249#define MAX14577_REGULATOR_SAFEOUT_VOLTAGE 4900000 249#define MAX14577_REGULATOR_SAFEOUT_VOLTAGE 4900000
250 250
251enum max14577_irq_source {
252 MAX14577_IRQ_INT1 = 0,
253 MAX14577_IRQ_INT2,
254 MAX14577_IRQ_INT3,
255
256 MAX14577_IRQ_REGS_NUM,
257};
258
259enum max14577_irq { 251enum max14577_irq {
260 /* INT1 */ 252 /* INT1 */
261 MAX14577_IRQ_INT1_ADC, 253 MAX14577_IRQ_INT1_ADC,
diff --git a/include/linux/mfd/max14577.h b/include/linux/mfd/max14577.h
index 247b021dfaaf..736d39c3ec0d 100644
--- a/include/linux/mfd/max14577.h
+++ b/include/linux/mfd/max14577.h
@@ -25,13 +25,8 @@
25#ifndef __MAX14577_H__ 25#ifndef __MAX14577_H__
26#define __MAX14577_H__ 26#define __MAX14577_H__
27 27
28#include <linux/mfd/max14577-private.h>
29#include <linux/regulator/consumer.h> 28#include <linux/regulator/consumer.h>
30 29
31/*
32 * MAX14577 Regulator
33 */
34
35/* MAX14577 regulator IDs */ 30/* MAX14577 regulator IDs */
36enum max14577_regulators { 31enum max14577_regulators {
37 MAX14577_SAFEOUT = 0, 32 MAX14577_SAFEOUT = 0,
diff --git a/include/linux/mfd/pm8xxx/irq.h b/include/linux/mfd/pm8xxx/irq.h
deleted file mode 100644
index f83d6b43ecbb..000000000000
--- a/include/linux/mfd/pm8xxx/irq.h
+++ /dev/null
@@ -1,59 +0,0 @@
1/*
2 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13/*
14 * Qualcomm PMIC irq 8xxx driver header file
15 *
16 */
17
18#ifndef __MFD_PM8XXX_IRQ_H
19#define __MFD_PM8XXX_IRQ_H
20
21#include <linux/errno.h>
22#include <linux/err.h>
23
24struct pm8xxx_irq_core_data {
25 u32 rev;
26 int nirqs;
27};
28
29struct pm8xxx_irq_platform_data {
30 int irq_base;
31 struct pm8xxx_irq_core_data irq_cdata;
32 int devirq;
33 int irq_trigger_flag;
34};
35
36struct pm_irq_chip;
37
38#ifdef CONFIG_MFD_PM8XXX_IRQ
39int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq);
40struct pm_irq_chip *pm8xxx_irq_init(struct device *dev,
41 const struct pm8xxx_irq_platform_data *pdata);
42int pm8xxx_irq_exit(struct pm_irq_chip *chip);
43#else
44static inline int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq)
45{
46 return -ENXIO;
47}
48static inline struct pm_irq_chip *pm8xxx_irq_init(
49 const struct device *dev,
50 const struct pm8xxx_irq_platform_data *pdata)
51{
52 return ERR_PTR(-ENXIO);
53}
54static inline int pm8xxx_irq_exit(struct pm_irq_chip *chip)
55{
56 return -ENXIO;
57}
58#endif /* CONFIG_MFD_PM8XXX_IRQ */
59#endif /* __MFD_PM8XXX_IRQ_H */
diff --git a/include/linux/mfd/pm8xxx/pm8921.h b/include/linux/mfd/pm8xxx/pm8921.h
deleted file mode 100644
index 00fa3de7659d..000000000000
--- a/include/linux/mfd/pm8xxx/pm8921.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13/*
14 * Qualcomm PMIC 8921 driver header file
15 *
16 */
17
18#ifndef __MFD_PM8921_H
19#define __MFD_PM8921_H
20
21#include <linux/mfd/pm8xxx/irq.h>
22
23#define PM8921_NR_IRQS 256
24
25struct pm8921_platform_data {
26 int irq_base;
27 struct pm8xxx_irq_platform_data *irq_pdata;
28};
29
30#endif
diff --git a/include/linux/mfd/rtsx_usb.h b/include/linux/mfd/rtsx_usb.h
new file mode 100644
index 000000000000..c446e4fd6b5c
--- /dev/null
+++ b/include/linux/mfd/rtsx_usb.h
@@ -0,0 +1,628 @@
1/* Driver for Realtek RTS5139 USB card reader
2 *
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, see <http://www.gnu.org/licenses/>.
16 *
17 * Author:
18 * Roger Tseng <rogerable@realtek.com>
19 */
20
21#ifndef __RTSX_USB_H
22#define __RTSX_USB_H
23
24#include <linux/usb.h>
25
26/* related module names */
27#define RTSX_USB_SD_CARD 0
28#define RTSX_USB_MS_CARD 1
29
30/* endpoint numbers */
31#define EP_BULK_OUT 1
32#define EP_BULK_IN 2
33#define EP_INTR_IN 3
34
35/* USB vendor requests */
36#define RTSX_USB_REQ_REG_OP 0x00
37#define RTSX_USB_REQ_POLL 0x02
38
39/* miscellaneous parameters */
40#define MIN_DIV_N 60
41#define MAX_DIV_N 120
42
43#define MAX_PHASE 15
44#define RX_TUNING_CNT 3
45
46#define QFN24 0
47#define LQFP48 1
48#define CHECK_PKG(ucr, pkg) ((ucr)->package == (pkg))
49
50/* data structures */
51struct rtsx_ucr {
52 u16 vendor_id;
53 u16 product_id;
54
55 int package;
56 u8 ic_version;
57 bool is_rts5179;
58
59 unsigned int cur_clk;
60
61 u8 *cmd_buf;
62 unsigned int cmd_idx;
63 u8 *rsp_buf;
64
65 struct usb_device *pusb_dev;
66 struct usb_interface *pusb_intf;
67 struct usb_sg_request current_sg;
68 unsigned char *iobuf;
69 dma_addr_t iobuf_dma;
70
71 struct timer_list sg_timer;
72 struct mutex dev_mutex;
73};
74
75/* buffer size */
76#define IOBUF_SIZE 1024
77
78/* prototypes of exported functions */
79extern int rtsx_usb_get_card_status(struct rtsx_ucr *ucr, u16 *status);
80
81extern int rtsx_usb_read_register(struct rtsx_ucr *ucr, u16 addr, u8 *data);
82extern int rtsx_usb_write_register(struct rtsx_ucr *ucr, u16 addr, u8 mask,
83 u8 data);
84
85extern int rtsx_usb_ep0_write_register(struct rtsx_ucr *ucr, u16 addr, u8 mask,
86 u8 data);
87extern int rtsx_usb_ep0_read_register(struct rtsx_ucr *ucr, u16 addr,
88 u8 *data);
89
90extern void rtsx_usb_add_cmd(struct rtsx_ucr *ucr, u8 cmd_type,
91 u16 reg_addr, u8 mask, u8 data);
92extern int rtsx_usb_send_cmd(struct rtsx_ucr *ucr, u8 flag, int timeout);
93extern int rtsx_usb_get_rsp(struct rtsx_ucr *ucr, int rsp_len, int timeout);
94extern int rtsx_usb_transfer_data(struct rtsx_ucr *ucr, unsigned int pipe,
95 void *buf, unsigned int len, int use_sg,
96 unsigned int *act_len, int timeout);
97
98extern int rtsx_usb_read_ppbuf(struct rtsx_ucr *ucr, u8 *buf, int buf_len);
99extern int rtsx_usb_write_ppbuf(struct rtsx_ucr *ucr, u8 *buf, int buf_len);
100extern int rtsx_usb_switch_clock(struct rtsx_ucr *ucr, unsigned int card_clock,
101 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
102extern int rtsx_usb_card_exclusive_check(struct rtsx_ucr *ucr, int card);
103
104/* card status */
105#define SD_CD 0x01
106#define MS_CD 0x02
107#define XD_CD 0x04
108#define CD_MASK (SD_CD | MS_CD | XD_CD)
109#define SD_WP 0x08
110
111/* reader command field offset & parameters */
112#define READ_REG_CMD 0
113#define WRITE_REG_CMD 1
114#define CHECK_REG_CMD 2
115
116#define PACKET_TYPE 4
117#define CNT_H 5
118#define CNT_L 6
119#define STAGE_FLAG 7
120#define CMD_OFFSET 8
121#define SEQ_WRITE_DATA_OFFSET 12
122
123#define BATCH_CMD 0
124#define SEQ_READ 1
125#define SEQ_WRITE 2
126
127#define STAGE_R 0x01
128#define STAGE_DI 0x02
129#define STAGE_DO 0x04
130#define STAGE_MS_STATUS 0x08
131#define STAGE_XD_STATUS 0x10
132#define MODE_C 0x00
133#define MODE_CR (STAGE_R)
134#define MODE_CDIR (STAGE_R | STAGE_DI)
135#define MODE_CDOR (STAGE_R | STAGE_DO)
136
137#define EP0_OP_SHIFT 14
138#define EP0_READ_REG_CMD 2
139#define EP0_WRITE_REG_CMD 3
140
141#define rtsx_usb_cmd_hdr_tag(ucr) \
142 do { \
143 ucr->cmd_buf[0] = 'R'; \
144 ucr->cmd_buf[1] = 'T'; \
145 ucr->cmd_buf[2] = 'C'; \
146 ucr->cmd_buf[3] = 'R'; \
147 } while (0)
148
149static inline void rtsx_usb_init_cmd(struct rtsx_ucr *ucr)
150{
151 rtsx_usb_cmd_hdr_tag(ucr);
152 ucr->cmd_idx = 0;
153 ucr->cmd_buf[PACKET_TYPE] = BATCH_CMD;
154}
155
156/* internal register address */
157#define FPDCTL 0xFC00
158#define SSC_DIV_N_0 0xFC07
159#define SSC_CTL1 0xFC09
160#define SSC_CTL2 0xFC0A
161#define CFG_MODE 0xFC0E
162#define CFG_MODE_1 0xFC0F
163#define RCCTL 0xFC14
164#define SOF_WDOG 0xFC28
165#define SYS_DUMMY0 0xFC30
166
167#define MS_BLKEND 0xFD30
168#define MS_READ_START 0xFD31
169#define MS_READ_COUNT 0xFD32
170#define MS_WRITE_START 0xFD33
171#define MS_WRITE_COUNT 0xFD34
172#define MS_COMMAND 0xFD35
173#define MS_OLD_BLOCK_0 0xFD36
174#define MS_OLD_BLOCK_1 0xFD37
175#define MS_NEW_BLOCK_0 0xFD38
176#define MS_NEW_BLOCK_1 0xFD39
177#define MS_LOG_BLOCK_0 0xFD3A
178#define MS_LOG_BLOCK_1 0xFD3B
179#define MS_BUS_WIDTH 0xFD3C
180#define MS_PAGE_START 0xFD3D
181#define MS_PAGE_LENGTH 0xFD3E
182#define MS_CFG 0xFD40
183#define MS_TPC 0xFD41
184#define MS_TRANS_CFG 0xFD42
185#define MS_TRANSFER 0xFD43
186#define MS_INT_REG 0xFD44
187#define MS_BYTE_CNT 0xFD45
188#define MS_SECTOR_CNT_L 0xFD46
189#define MS_SECTOR_CNT_H 0xFD47
190#define MS_DBUS_H 0xFD48
191
192#define CARD_DMA1_CTL 0xFD5C
193#define CARD_PULL_CTL1 0xFD60
194#define CARD_PULL_CTL2 0xFD61
195#define CARD_PULL_CTL3 0xFD62
196#define CARD_PULL_CTL4 0xFD63
197#define CARD_PULL_CTL5 0xFD64
198#define CARD_PULL_CTL6 0xFD65
199#define CARD_EXIST 0xFD6F
200#define CARD_INT_PEND 0xFD71
201
202#define LDO_POWER_CFG 0xFD7B
203
204#define SD_CFG1 0xFDA0
205#define SD_CFG2 0xFDA1
206#define SD_CFG3 0xFDA2
207#define SD_STAT1 0xFDA3
208#define SD_STAT2 0xFDA4
209#define SD_BUS_STAT 0xFDA5
210#define SD_PAD_CTL 0xFDA6
211#define SD_SAMPLE_POINT_CTL 0xFDA7
212#define SD_PUSH_POINT_CTL 0xFDA8
213#define SD_CMD0 0xFDA9
214#define SD_CMD1 0xFDAA
215#define SD_CMD2 0xFDAB
216#define SD_CMD3 0xFDAC
217#define SD_CMD4 0xFDAD
218#define SD_CMD5 0xFDAE
219#define SD_BYTE_CNT_L 0xFDAF
220#define SD_BYTE_CNT_H 0xFDB0
221#define SD_BLOCK_CNT_L 0xFDB1
222#define SD_BLOCK_CNT_H 0xFDB2
223#define SD_TRANSFER 0xFDB3
224#define SD_CMD_STATE 0xFDB5
225#define SD_DATA_STATE 0xFDB6
226#define SD_VPCLK0_CTL 0xFC2A
227#define SD_VPCLK1_CTL 0xFC2B
228#define SD_DCMPS0_CTL 0xFC2C
229#define SD_DCMPS1_CTL 0xFC2D
230
231#define CARD_DMA1_CTL 0xFD5C
232
233#define HW_VERSION 0xFC01
234
235#define SSC_CLK_FPGA_SEL 0xFC02
236#define CLK_DIV 0xFC03
237#define SFSM_ED 0xFC04
238
239#define CD_DEGLITCH_WIDTH 0xFC20
240#define CD_DEGLITCH_EN 0xFC21
241#define AUTO_DELINK_EN 0xFC23
242
243#define FPGA_PULL_CTL 0xFC1D
244#define CARD_CLK_SOURCE 0xFC2E
245
246#define CARD_SHARE_MODE 0xFD51
247#define CARD_DRIVE_SEL 0xFD52
248#define CARD_STOP 0xFD53
249#define CARD_OE 0xFD54
250#define CARD_AUTO_BLINK 0xFD55
251#define CARD_GPIO 0xFD56
252#define SD30_DRIVE_SEL 0xFD57
253
254#define CARD_DATA_SOURCE 0xFD5D
255#define CARD_SELECT 0xFD5E
256
257#define CARD_CLK_EN 0xFD79
258#define CARD_PWR_CTL 0xFD7A
259
260#define OCPCTL 0xFD80
261#define OCPPARA1 0xFD81
262#define OCPPARA2 0xFD82
263#define OCPSTAT 0xFD83
264
265#define HS_USB_STAT 0xFE01
266#define HS_VCONTROL 0xFE26
267#define HS_VSTAIN 0xFE27
268#define HS_VLOADM 0xFE28
269#define HS_VSTAOUT 0xFE29
270
271#define MC_IRQ 0xFF00
272#define MC_IRQEN 0xFF01
273#define MC_FIFO_CTL 0xFF02
274#define MC_FIFO_BC0 0xFF03
275#define MC_FIFO_BC1 0xFF04
276#define MC_FIFO_STAT 0xFF05
277#define MC_FIFO_MODE 0xFF06
278#define MC_FIFO_RD_PTR0 0xFF07
279#define MC_FIFO_RD_PTR1 0xFF08
280#define MC_DMA_CTL 0xFF10
281#define MC_DMA_TC0 0xFF11
282#define MC_DMA_TC1 0xFF12
283#define MC_DMA_TC2 0xFF13
284#define MC_DMA_TC3 0xFF14
285#define MC_DMA_RST 0xFF15
286
287#define RBUF_SIZE_MASK 0xFBFF
288#define RBUF_BASE 0xF000
289#define PPBUF_BASE1 0xF800
290#define PPBUF_BASE2 0xFA00
291
292/* internal register value macros */
293#define POWER_OFF 0x03
294#define PARTIAL_POWER_ON 0x02
295#define POWER_ON 0x00
296#define POWER_MASK 0x03
297#define LDO3318_PWR_MASK 0x0C
298#define LDO_ON 0x00
299#define LDO_SUSPEND 0x08
300#define LDO_OFF 0x0C
301#define DV3318_AUTO_PWR_OFF 0x10
302#define FORCE_LDO_POWERB 0x60
303
304/* LDO_POWER_CFG */
305#define TUNE_SD18_MASK 0x1C
306#define TUNE_SD18_1V7 0x00
307#define TUNE_SD18_1V8 (0x01 << 2)
308#define TUNE_SD18_1V9 (0x02 << 2)
309#define TUNE_SD18_2V0 (0x03 << 2)
310#define TUNE_SD18_2V7 (0x04 << 2)
311#define TUNE_SD18_2V8 (0x05 << 2)
312#define TUNE_SD18_2V9 (0x06 << 2)
313#define TUNE_SD18_3V3 (0x07 << 2)
314
315/* CLK_DIV */
316#define CLK_CHANGE 0x80
317#define CLK_DIV_1 0x00
318#define CLK_DIV_2 0x01
319#define CLK_DIV_4 0x02
320#define CLK_DIV_8 0x03
321
322#define SSC_POWER_MASK 0x01
323#define SSC_POWER_DOWN 0x01
324#define SSC_POWER_ON 0x00
325
326#define FPGA_VER 0x80
327#define HW_VER_MASK 0x0F
328
329#define EXTEND_DMA1_ASYNC_SIGNAL 0x02
330
331/* CFG_MODE*/
332#define XTAL_FREE 0x80
333#define CLK_MODE_MASK 0x03
334#define CLK_MODE_12M_XTAL 0x00
335#define CLK_MODE_NON_XTAL 0x01
336#define CLK_MODE_24M_OSC 0x02
337#define CLK_MODE_48M_OSC 0x03
338
339/* CFG_MODE_1*/
340#define RTS5179 0x02
341
342#define NYET_EN 0x01
343#define NYET_MSAK 0x01
344
345#define SD30_DRIVE_MASK 0x07
346#define SD20_DRIVE_MASK 0x03
347
348#define DISABLE_SD_CD 0x08
349#define DISABLE_MS_CD 0x10
350#define DISABLE_XD_CD 0x20
351#define SD_CD_DEGLITCH_EN 0x01
352#define MS_CD_DEGLITCH_EN 0x02
353#define XD_CD_DEGLITCH_EN 0x04
354
355#define CARD_SHARE_LQFP48 0x04
356#define CARD_SHARE_QFN24 0x00
357#define CARD_SHARE_LQFP_SEL 0x04
358#define CARD_SHARE_XD 0x00
359#define CARD_SHARE_SD 0x01
360#define CARD_SHARE_MS 0x02
361#define CARD_SHARE_MASK 0x03
362
363
364/* SD30_DRIVE_SEL */
365#define DRIVER_TYPE_A 0x05
366#define DRIVER_TYPE_B 0x03
367#define DRIVER_TYPE_C 0x02
368#define DRIVER_TYPE_D 0x01
369
370/* SD_BUS_STAT */
371#define SD_CLK_TOGGLE_EN 0x80
372#define SD_CLK_FORCE_STOP 0x40
373#define SD_DAT3_STATUS 0x10
374#define SD_DAT2_STATUS 0x08
375#define SD_DAT1_STATUS 0x04
376#define SD_DAT0_STATUS 0x02
377#define SD_CMD_STATUS 0x01
378
379/* SD_PAD_CTL */
380#define SD_IO_USING_1V8 0x80
381#define SD_IO_USING_3V3 0x7F
382#define TYPE_A_DRIVING 0x00
383#define TYPE_B_DRIVING 0x01
384#define TYPE_C_DRIVING 0x02
385#define TYPE_D_DRIVING 0x03
386
387/* CARD_CLK_EN */
388#define SD_CLK_EN 0x04
389#define MS_CLK_EN 0x08
390
391/* CARD_SELECT */
392#define SD_MOD_SEL 2
393#define MS_MOD_SEL 3
394
395/* CARD_SHARE_MODE */
396#define CARD_SHARE_LQFP48 0x04
397#define CARD_SHARE_QFN24 0x00
398#define CARD_SHARE_LQFP_SEL 0x04
399#define CARD_SHARE_XD 0x00
400#define CARD_SHARE_SD 0x01
401#define CARD_SHARE_MS 0x02
402#define CARD_SHARE_MASK 0x03
403
404/* SSC_CTL1 */
405#define SSC_RSTB 0x80
406#define SSC_8X_EN 0x40
407#define SSC_FIX_FRAC 0x20
408#define SSC_SEL_1M 0x00
409#define SSC_SEL_2M 0x08
410#define SSC_SEL_4M 0x10
411#define SSC_SEL_8M 0x18
412
413/* SSC_CTL2 */
414#define SSC_DEPTH_MASK 0x03
415#define SSC_DEPTH_DISALBE 0x00
416#define SSC_DEPTH_2M 0x01
417#define SSC_DEPTH_1M 0x02
418#define SSC_DEPTH_512K 0x03
419
420/* SD_VPCLK0_CTL */
421#define PHASE_CHANGE 0x80
422#define PHASE_NOT_RESET 0x40
423
424/* SD_TRANSFER */
425#define SD_TRANSFER_START 0x80
426#define SD_TRANSFER_END 0x40
427#define SD_STAT_IDLE 0x20
428#define SD_TRANSFER_ERR 0x10
429#define SD_TM_NORMAL_WRITE 0x00
430#define SD_TM_AUTO_WRITE_3 0x01
431#define SD_TM_AUTO_WRITE_4 0x02
432#define SD_TM_AUTO_READ_3 0x05
433#define SD_TM_AUTO_READ_4 0x06
434#define SD_TM_CMD_RSP 0x08
435#define SD_TM_AUTO_WRITE_1 0x09
436#define SD_TM_AUTO_WRITE_2 0x0A
437#define SD_TM_NORMAL_READ 0x0C
438#define SD_TM_AUTO_READ_1 0x0D
439#define SD_TM_AUTO_READ_2 0x0E
440#define SD_TM_AUTO_TUNING 0x0F
441
442/* SD_CFG1 */
443#define SD_CLK_DIVIDE_0 0x00
444#define SD_CLK_DIVIDE_256 0xC0
445#define SD_CLK_DIVIDE_128 0x80
446#define SD_CLK_DIVIDE_MASK 0xC0
447#define SD_BUS_WIDTH_1BIT 0x00
448#define SD_BUS_WIDTH_4BIT 0x01
449#define SD_BUS_WIDTH_8BIT 0x02
450#define SD_ASYNC_FIFO_RST 0x10
451#define SD_20_MODE 0x00
452#define SD_DDR_MODE 0x04
453#define SD_30_MODE 0x08
454
455/* SD_CFG2 */
456#define SD_CALCULATE_CRC7 0x00
457#define SD_NO_CALCULATE_CRC7 0x80
458#define SD_CHECK_CRC16 0x00
459#define SD_NO_CHECK_CRC16 0x40
460#define SD_WAIT_CRC_TO_EN 0x20
461#define SD_WAIT_BUSY_END 0x08
462#define SD_NO_WAIT_BUSY_END 0x00
463#define SD_CHECK_CRC7 0x00
464#define SD_NO_CHECK_CRC7 0x04
465#define SD_RSP_LEN_0 0x00
466#define SD_RSP_LEN_6 0x01
467#define SD_RSP_LEN_17 0x02
468#define SD_RSP_TYPE_R0 0x04
469#define SD_RSP_TYPE_R1 0x01
470#define SD_RSP_TYPE_R1b 0x09
471#define SD_RSP_TYPE_R2 0x02
472#define SD_RSP_TYPE_R3 0x05
473#define SD_RSP_TYPE_R4 0x05
474#define SD_RSP_TYPE_R5 0x01
475#define SD_RSP_TYPE_R6 0x01
476#define SD_RSP_TYPE_R7 0x01
477
478/* SD_STAT1 */
479#define SD_CRC7_ERR 0x80
480#define SD_CRC16_ERR 0x40
481#define SD_CRC_WRITE_ERR 0x20
482#define SD_CRC_WRITE_ERR_MASK 0x1C
483#define GET_CRC_TIME_OUT 0x02
484#define SD_TUNING_COMPARE_ERR 0x01
485
486/* SD_DATA_STATE */
487#define SD_DATA_IDLE 0x80
488
489/* CARD_DATA_SOURCE */
490#define PINGPONG_BUFFER 0x01
491#define RING_BUFFER 0x00
492
493/* CARD_OE */
494#define SD_OUTPUT_EN 0x04
495#define MS_OUTPUT_EN 0x08
496
497/* CARD_STOP */
498#define SD_STOP 0x04
499#define MS_STOP 0x08
500#define SD_CLR_ERR 0x40
501#define MS_CLR_ERR 0x80
502
503/* CARD_CLK_SOURCE */
504#define CRC_FIX_CLK (0x00 << 0)
505#define CRC_VAR_CLK0 (0x01 << 0)
506#define CRC_VAR_CLK1 (0x02 << 0)
507#define SD30_FIX_CLK (0x00 << 2)
508#define SD30_VAR_CLK0 (0x01 << 2)
509#define SD30_VAR_CLK1 (0x02 << 2)
510#define SAMPLE_FIX_CLK (0x00 << 4)
511#define SAMPLE_VAR_CLK0 (0x01 << 4)
512#define SAMPLE_VAR_CLK1 (0x02 << 4)
513
514/* SD_SAMPLE_POINT_CTL */
515#define DDR_FIX_RX_DAT 0x00
516#define DDR_VAR_RX_DAT 0x80
517#define DDR_FIX_RX_DAT_EDGE 0x00
518#define DDR_FIX_RX_DAT_14_DELAY 0x40
519#define DDR_FIX_RX_CMD 0x00
520#define DDR_VAR_RX_CMD 0x20
521#define DDR_FIX_RX_CMD_POS_EDGE 0x00
522#define DDR_FIX_RX_CMD_14_DELAY 0x10
523#define SD20_RX_POS_EDGE 0x00
524#define SD20_RX_14_DELAY 0x08
525#define SD20_RX_SEL_MASK 0x08
526
527/* SD_PUSH_POINT_CTL */
528#define DDR_FIX_TX_CMD_DAT 0x00
529#define DDR_VAR_TX_CMD_DAT 0x80
530#define DDR_FIX_TX_DAT_14_TSU 0x00
531#define DDR_FIX_TX_DAT_12_TSU 0x40
532#define DDR_FIX_TX_CMD_NEG_EDGE 0x00
533#define DDR_FIX_TX_CMD_14_AHEAD 0x20
534#define SD20_TX_NEG_EDGE 0x00
535#define SD20_TX_14_AHEAD 0x10
536#define SD20_TX_SEL_MASK 0x10
537#define DDR_VAR_SDCLK_POL_SWAP 0x01
538
539/* MS_CFG */
540#define SAMPLE_TIME_RISING 0x00
541#define SAMPLE_TIME_FALLING 0x80
542#define PUSH_TIME_DEFAULT 0x00
543#define PUSH_TIME_ODD 0x40
544#define NO_EXTEND_TOGGLE 0x00
545#define EXTEND_TOGGLE_CHK 0x20
546#define MS_BUS_WIDTH_1 0x00
547#define MS_BUS_WIDTH_4 0x10
548#define MS_BUS_WIDTH_8 0x18
549#define MS_2K_SECTOR_MODE 0x04
550#define MS_512_SECTOR_MODE 0x00
551#define MS_TOGGLE_TIMEOUT_EN 0x00
552#define MS_TOGGLE_TIMEOUT_DISEN 0x01
553#define MS_NO_CHECK_INT 0x02
554
555/* MS_TRANS_CFG */
556#define WAIT_INT 0x80
557#define NO_WAIT_INT 0x00
558#define NO_AUTO_READ_INT_REG 0x00
559#define AUTO_READ_INT_REG 0x40
560#define MS_CRC16_ERR 0x20
561#define MS_RDY_TIMEOUT 0x10
562#define MS_INT_CMDNK 0x08
563#define MS_INT_BREQ 0x04
564#define MS_INT_ERR 0x02
565#define MS_INT_CED 0x01
566
567/* MS_TRANSFER */
568#define MS_TRANSFER_START 0x80
569#define MS_TRANSFER_END 0x40
570#define MS_TRANSFER_ERR 0x20
571#define MS_BS_STATE 0x10
572#define MS_TM_READ_BYTES 0x00
573#define MS_TM_NORMAL_READ 0x01
574#define MS_TM_WRITE_BYTES 0x04
575#define MS_TM_NORMAL_WRITE 0x05
576#define MS_TM_AUTO_READ 0x08
577#define MS_TM_AUTO_WRITE 0x0C
578#define MS_TM_SET_CMD 0x06
579#define MS_TM_COPY_PAGE 0x07
580#define MS_TM_MULTI_READ 0x02
581#define MS_TM_MULTI_WRITE 0x03
582
583/* MC_FIFO_CTL */
584#define FIFO_FLUSH 0x01
585
586/* MC_DMA_RST */
587#define DMA_RESET 0x01
588
589/* MC_DMA_CTL */
590#define DMA_TC_EQ_0 0x80
591#define DMA_DIR_TO_CARD 0x00
592#define DMA_DIR_FROM_CARD 0x02
593#define DMA_EN 0x01
594#define DMA_128 (0 << 2)
595#define DMA_256 (1 << 2)
596#define DMA_512 (2 << 2)
597#define DMA_1024 (3 << 2)
598#define DMA_PACK_SIZE_MASK 0x0C
599
600/* CARD_INT_PEND */
601#define XD_INT 0x10
602#define MS_INT 0x08
603#define SD_INT 0x04
604
605/* LED operations*/
606static inline int rtsx_usb_turn_on_led(struct rtsx_ucr *ucr)
607{
608 return rtsx_usb_ep0_write_register(ucr, CARD_GPIO, 0x03, 0x02);
609}
610
611static inline int rtsx_usb_turn_off_led(struct rtsx_ucr *ucr)
612{
613 return rtsx_usb_ep0_write_register(ucr, CARD_GPIO, 0x03, 0x03);
614}
615
616/* HW error clearing */
617static inline void rtsx_usb_clear_fsm_err(struct rtsx_ucr *ucr)
618{
619 rtsx_usb_ep0_write_register(ucr, SFSM_ED, 0xf8, 0xf8);
620}
621
622static inline void rtsx_usb_clear_dma_err(struct rtsx_ucr *ucr)
623{
624 rtsx_usb_ep0_write_register(ucr, MC_FIFO_CTL,
625 FIFO_FLUSH, FIFO_FLUSH);
626 rtsx_usb_ep0_write_register(ucr, MC_DMA_RST, DMA_RESET, DMA_RESET);
627}
628#endif /* __RTS51139_H */
diff --git a/include/linux/mfd/tps65218.h b/include/linux/mfd/tps65218.h
new file mode 100644
index 000000000000..d2e357df5a0e
--- /dev/null
+++ b/include/linux/mfd/tps65218.h
@@ -0,0 +1,284 @@
1/*
2 * linux/mfd/tps65218.h
3 *
4 * Functions to access TPS65219 power management chip.
5 *
6 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether expressed or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License version 2 for more details.
16 */
17
18#ifndef __LINUX_MFD_TPS65218_H
19#define __LINUX_MFD_TPS65218_H
20
21#include <linux/i2c.h>
22#include <linux/regulator/driver.h>
23#include <linux/regulator/machine.h>
24#include <linux/bitops.h>
25
26/* TPS chip id list */
27#define TPS65218 0xF0
28
29/* I2C ID for TPS65218 part */
30#define TPS65218_I2C_ID 0x24
31
32/* All register addresses */
33#define TPS65218_REG_CHIPID 0x00
34#define TPS65218_REG_INT1 0x01
35#define TPS65218_REG_INT2 0x02
36#define TPS65218_REG_INT_MASK1 0x03
37#define TPS65218_REG_INT_MASK2 0x04
38#define TPS65218_REG_STATUS 0x05
39#define TPS65218_REG_CONTROL 0x06
40#define TPS65218_REG_FLAG 0x07
41
42#define TPS65218_REG_PASSWORD 0x10
43#define TPS65218_REG_ENABLE1 0x11
44#define TPS65218_REG_ENABLE2 0x12
45#define TPS65218_REG_CONFIG1 0x13
46#define TPS65218_REG_CONFIG2 0x14
47#define TPS65218_REG_CONFIG3 0x15
48#define TPS65218_REG_CONTROL_DCDC1 0x16
49#define TPS65218_REG_CONTROL_DCDC2 0x17
50#define TPS65218_REG_CONTROL_DCDC3 0x18
51#define TPS65218_REG_CONTROL_DCDC4 0x19
52#define TPS65218_REG_CONTRL_SLEW_RATE 0x1A
53#define TPS65218_REG_CONTROL_LDO1 0x1B
54#define TPS65218_REG_SEQ1 0x20
55#define TPS65218_REG_SEQ2 0x21
56#define TPS65218_REG_SEQ3 0x22
57#define TPS65218_REG_SEQ4 0x23
58#define TPS65218_REG_SEQ5 0x24
59#define TPS65218_REG_SEQ6 0x25
60#define TPS65218_REG_SEQ7 0x26
61
62/* Register field definitions */
63#define TPS65218_CHIPID_CHIP_MASK 0xF8
64#define TPS65218_CHIPID_REV_MASK 0x07
65
66#define TPS65218_INT1_VPRG BIT(5)
67#define TPS65218_INT1_AC BIT(4)
68#define TPS65218_INT1_PB BIT(3)
69#define TPS65218_INT1_HOT BIT(2)
70#define TPS65218_INT1_CC_AQC BIT(1)
71#define TPS65218_INT1_PRGC BIT(0)
72
73#define TPS65218_INT2_LS3_F BIT(5)
74#define TPS65218_INT2_LS2_F BIT(4)
75#define TPS65218_INT2_LS1_F BIT(3)
76#define TPS65218_INT2_LS3_I BIT(2)
77#define TPS65218_INT2_LS2_I BIT(1)
78#define TPS65218_INT2_LS1_I BIT(0)
79
80#define TPS65218_INT_MASK1_VPRG BIT(5)
81#define TPS65218_INT_MASK1_AC BIT(4)
82#define TPS65218_INT_MASK1_PB BIT(3)
83#define TPS65218_INT_MASK1_HOT BIT(2)
84#define TPS65218_INT_MASK1_CC_AQC BIT(1)
85#define TPS65218_INT_MASK1_PRGC BIT(0)
86
87#define TPS65218_INT_MASK2_LS3_F BIT(5)
88#define TPS65218_INT_MASK2_LS2_F BIT(4)
89#define TPS65218_INT_MASK2_LS1_F BIT(3)
90#define TPS65218_INT_MASK2_LS3_I BIT(2)
91#define TPS65218_INT_MASK2_LS2_I BIT(1)
92#define TPS65218_INT_MASK2_LS1_I BIT(0)
93
94#define TPS65218_STATUS_FSEAL BIT(7)
95#define TPS65218_STATUS_EE BIT(6)
96#define TPS65218_STATUS_AC_STATE BIT(5)
97#define TPS65218_STATUS_PB_STATE BIT(4)
98#define TPS65218_STATUS_STATE_MASK 0xC
99#define TPS65218_STATUS_CC_STAT 0x3
100
101#define TPS65218_CONTROL_OFFNPFO BIT(1)
102#define TPS65218_CONTROL_CC_AQ BIT(0)
103
104#define TPS65218_FLAG_GPO3_FLG BIT(7)
105#define TPS65218_FLAG_GPO2_FLG BIT(6)
106#define TPS65218_FLAG_GPO1_FLG BIT(5)
107#define TPS65218_FLAG_LDO1_FLG BIT(4)
108#define TPS65218_FLAG_DC4_FLG BIT(3)
109#define TPS65218_FLAG_DC3_FLG BIT(2)
110#define TPS65218_FLAG_DC2_FLG BIT(1)
111#define TPS65218_FLAG_DC1_FLG BIT(0)
112
113#define TPS65218_ENABLE1_DC6_EN BIT(5)
114#define TPS65218_ENABLE1_DC5_EN BIT(4)
115#define TPS65218_ENABLE1_DC4_EN BIT(3)
116#define TPS65218_ENABLE1_DC3_EN BIT(2)
117#define TPS65218_ENABLE1_DC2_EN BIT(1)
118#define TPS65218_ENABLE1_DC1_EN BIT(0)
119
120#define TPS65218_ENABLE2_GPIO3 BIT(6)
121#define TPS65218_ENABLE2_GPIO2 BIT(5)
122#define TPS65218_ENABLE2_GPIO1 BIT(4)
123#define TPS65218_ENABLE2_LS3_EN BIT(3)
124#define TPS65218_ENABLE2_LS2_EN BIT(2)
125#define TPS65218_ENABLE2_LS1_EN BIT(1)
126#define TPS65218_ENABLE2_LDO1_EN BIT(0)
127
128
129#define TPS65218_CONFIG1_TRST BIT(7)
130#define TPS65218_CONFIG1_GPO2_BUF BIT(6)
131#define TPS65218_CONFIG1_IO1_SEL BIT(5)
132#define TPS65218_CONFIG1_PGDLY_MASK 0x18
133#define TPS65218_CONFIG1_STRICT BIT(2)
134#define TPS65218_CONFIG1_UVLO_MASK 0x3
135
136#define TPS65218_CONFIG2_DC12_RST BIT(7)
137#define TPS65218_CONFIG2_UVLOHYS BIT(6)
138#define TPS65218_CONFIG2_LS3ILIM_MASK 0xC
139#define TPS65218_CONFIG2_LS2ILIM_MASK 0x3
140
141#define TPS65218_CONFIG3_LS3NPFO BIT(5)
142#define TPS65218_CONFIG3_LS2NPFO BIT(4)
143#define TPS65218_CONFIG3_LS1NPFO BIT(3)
144#define TPS65218_CONFIG3_LS3DCHRG BIT(2)
145#define TPS65218_CONFIG3_LS2DCHRG BIT(1)
146#define TPS65218_CONFIG3_LS1DCHRG BIT(0)
147
148#define TPS65218_CONTROL_DCDC1_PFM BIT(7)
149#define TPS65218_CONTROL_DCDC1_MASK 0x7F
150
151#define TPS65218_CONTROL_DCDC2_PFM BIT(7)
152#define TPS65218_CONTROL_DCDC2_MASK 0x3F
153
154#define TPS65218_CONTROL_DCDC3_PFM BIT(7)
155#define TPS65218_CONTROL_DCDC3_MASK 0x3F
156
157#define TPS65218_CONTROL_DCDC4_PFM BIT(7)
158#define TPS65218_CONTROL_DCDC4_MASK 0x3F
159
160#define TPS65218_SLEW_RATE_GO BIT(7)
161#define TPS65218_SLEW_RATE_GODSBL BIT(6)
162#define TPS65218_SLEW_RATE_SLEW_MASK 0x7
163
164#define TPS65218_CONTROL_LDO1_MASK 0x3F
165
166#define TPS65218_SEQ1_DLY8 BIT(7)
167#define TPS65218_SEQ1_DLY7 BIT(6)
168#define TPS65218_SEQ1_DLY6 BIT(5)
169#define TPS65218_SEQ1_DLY5 BIT(4)
170#define TPS65218_SEQ1_DLY4 BIT(3)
171#define TPS65218_SEQ1_DLY3 BIT(2)
172#define TPS65218_SEQ1_DLY2 BIT(1)
173#define TPS65218_SEQ1_DLY1 BIT(0)
174
175#define TPS65218_SEQ2_DLYFCTR BIT(7)
176#define TPS65218_SEQ2_DLY9 BIT(0)
177
178#define TPS65218_SEQ3_DC2_SEQ_MASK 0xF0
179#define TPS65218_SEQ3_DC1_SEQ_MASK 0xF
180
181#define TPS65218_SEQ4_DC4_SEQ_MASK 0xF0
182#define TPS65218_SEQ4_DC3_SEQ_MASK 0xF
183
184#define TPS65218_SEQ5_DC6_SEQ_MASK 0xF0
185#define TPS65218_SEQ5_DC5_SEQ_MASK 0xF
186
187#define TPS65218_SEQ6_LS1_SEQ_MASK 0xF0
188#define TPS65218_SEQ6_LDO1_SEQ_MASK 0xF
189
190#define TPS65218_SEQ7_GPO3_SEQ_MASK 0xF0
191#define TPS65218_SEQ7_GPO1_SEQ_MASK 0xF
192#define TPS65218_PROTECT_NONE 0
193#define TPS65218_PROTECT_L1 1
194
195enum tps65218_regulator_id {
196 /* DCDC's */
197 TPS65218_DCDC_1,
198 TPS65218_DCDC_2,
199 TPS65218_DCDC_3,
200 TPS65218_DCDC_4,
201 TPS65218_DCDC_5,
202 TPS65218_DCDC_6,
203 /* LDOs */
204 TPS65218_LDO_1,
205};
206
207#define TPS65218_MAX_REG_ID TPS65218_LDO_1
208
209/* Number of step-down converters available */
210#define TPS65218_NUM_DCDC 6
211/* Number of LDO voltage regulators available */
212#define TPS65218_NUM_LDO 1
213/* Number of total regulators available */
214#define TPS65218_NUM_REGULATOR (TPS65218_NUM_DCDC + TPS65218_NUM_LDO)
215
216/* Define the TPS65218 IRQ numbers */
217enum tps65218_irqs {
218 /* INT1 registers */
219 TPS65218_PRGC_IRQ,
220 TPS65218_CC_AQC_IRQ,
221 TPS65218_HOT_IRQ,
222 TPS65218_PB_IRQ,
223 TPS65218_AC_IRQ,
224 TPS65218_VPRG_IRQ,
225 TPS65218_INVALID1_IRQ,
226 TPS65218_INVALID2_IRQ,
227 /* INT2 registers */
228 TPS65218_LS1_I_IRQ,
229 TPS65218_LS2_I_IRQ,
230 TPS65218_LS3_I_IRQ,
231 TPS65218_LS1_F_IRQ,
232 TPS65218_LS2_F_IRQ,
233 TPS65218_LS3_F_IRQ,
234 TPS65218_INVALID3_IRQ,
235 TPS65218_INVALID4_IRQ,
236};
237
238/**
239 * struct tps_info - packages regulator constraints
240 * @id: Id of the regulator
241 * @name: Voltage regulator name
242 * @min_uV: minimum micro volts
243 * @max_uV: minimum micro volts
244 *
245 * This data is used to check the regualtor voltage limits while setting.
246 */
247struct tps_info {
248 int id;
249 const char *name;
250 int min_uV;
251 int max_uV;
252};
253
254/**
255 * struct tps65218 - tps65218 sub-driver chip access routines
256 *
257 * Device data may be used to access the TPS65218 chip
258 */
259
260struct tps65218 {
261 struct device *dev;
262 unsigned int id;
263
264 struct mutex tps_lock; /* lock guarding the data structure */
265 /* IRQ Data */
266 int irq;
267 u32 irq_mask;
268 struct regmap_irq_chip_data *irq_data;
269 struct regulator_desc desc[TPS65218_NUM_REGULATOR];
270 struct regulator_dev *rdev[TPS65218_NUM_REGULATOR];
271 struct tps_info *info[TPS65218_NUM_REGULATOR];
272 struct regmap *regmap;
273};
274
275int tps65218_reg_read(struct tps65218 *tps, unsigned int reg,
276 unsigned int *val);
277int tps65218_reg_write(struct tps65218 *tps, unsigned int reg,
278 unsigned int val, unsigned int level);
279int tps65218_set_bits(struct tps65218 *tps, unsigned int reg,
280 unsigned int mask, unsigned int val, unsigned int level);
281int tps65218_clear_bits(struct tps65218 *tps, unsigned int reg,
282 unsigned int mask, unsigned int level);
283
284#endif /* __LINUX_MFD_TPS65218_H */
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