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authorLinus Torvalds <torvalds@linux-foundation.org>2012-05-22 12:23:24 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-05-22 12:23:24 -0400
commit9bc747bea5fad819e0c0ad96e6a67ea0640dfe2b (patch)
treed500225e7a1c90a6bd17d3e63e2f6e781810db2b /include/linux/mfd
parent32b908eea9e5ecd1049008e134eadbfcd0da5e38 (diff)
parent0e896b1ddc1905df904df98c204bacf028219729 (diff)
Merge tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull first batch of arm-soc cleanups from Olof Johansson: "These cleanups are basically all over the place. The idea is to collect changes with minimal impact but large number of changes so we can avoid them from distracting in the diffstat in the other series. A significant number of lines get removed here, in particular because the ixp2000 and ixp23xx platforms get removed. These have never been extremely popular and have fallen into disuse over time with no active maintainer taking care of them. The u5500 soc never made it into a product, so we are removing it from the ux500 platform. Many good cleanups also went into the at91 and omap platforms, as has been the case for a number of releases." Trivial modify-delete conflicts in arch/arm/mach-{ixp2000,ixp23xx} * tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (152 commits) ARM: clps711x: Cleanup IRQ handling ARM clps711x: Removed unused header mach/time.h ARM: clps711x: Added note about support EP731x CPU to Kconfig ARM: clps711x: Added missing register definitions ARM: clps711x: Used own subarch directory for store header file Dove: Fix Section mismatch warnings ARM: orion5x: ts78xx debugging changes ARM: orion5x: remove PM dependency from ts78xx ARM: orion5x: ts78xx fix NAND resource off by one ARM: orion5x: ts78xx whitespace cleanups Orion5x: Fix Section mismatch warnings Orion5x: Fix warning: struct pci_dev declared inside paramter list ARM: clps711x: Combine header files into one for clps711x-targets ARM: S3C24XX: Use common macro to define resources on mach-qt2410.c ARM: S3C24XX: Use common macro to define resources on mach-osiris.c ARM: EXYNOS: Adapt to cpuidle core time keeping and irq enable ARM: S5PV210: Use common macro to define resources on mach-smdkv210.c ARM: S5PV210: Use common macro to define resources on dev-audio.c ARM: S5PC100: Use common macro to define resources on dev-audio.c ARM: S5P64X0: Use common macro to define resources on dev-audio.c ...
Diffstat (limited to 'include/linux/mfd')
-rw-r--r--include/linux/mfd/abx500.h5
-rw-r--r--include/linux/mfd/abx500/ab5500.h140
-rw-r--r--include/linux/mfd/db5500-prcmu.h105
-rw-r--r--include/linux/mfd/dbx500-prcmu.h242
4 files changed, 44 insertions, 448 deletions
diff --git a/include/linux/mfd/abx500.h b/include/linux/mfd/abx500.h
index ee96cd51d8b2..1318ca622633 100644
--- a/include/linux/mfd/abx500.h
+++ b/include/linux/mfd/abx500.h
@@ -6,7 +6,7 @@
6 * 6 *
7 * ABX500 core access functions. 7 * ABX500 core access functions.
8 * The abx500 interface is used for the Analog Baseband chip 8 * The abx500 interface is used for the Analog Baseband chip
9 * ab3100, ab5500, and ab8500. 9 * ab3100 and ab8500.
10 * 10 *
11 * Author: Mattias Wallin <mattias.wallin@stericsson.com> 11 * Author: Mattias Wallin <mattias.wallin@stericsson.com>
12 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> 12 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
@@ -30,9 +30,6 @@ struct device;
30#define AB3100_P1G 0xc6 30#define AB3100_P1G 0xc6
31#define AB3100_R2A 0xc7 31#define AB3100_R2A 0xc7
32#define AB3100_R2B 0xc8 32#define AB3100_R2B 0xc8
33#define AB5500_1_0 0x20
34#define AB5500_1_1 0x21
35#define AB5500_2_0 0x24
36 33
37/* 34/*
38 * AB3100, EVENTA1, A2 and A3 event register flags 35 * AB3100, EVENTA1, A2 and A3 event register flags
diff --git a/include/linux/mfd/abx500/ab5500.h b/include/linux/mfd/abx500/ab5500.h
deleted file mode 100644
index 54f820ed73bb..000000000000
--- a/include/linux/mfd/abx500/ab5500.h
+++ /dev/null
@@ -1,140 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson 2011
3 *
4 * License Terms: GNU General Public License v2
5 */
6#ifndef MFD_AB5500_H
7#define MFD_AB5500_H
8
9struct device;
10
11enum ab5500_devid {
12 AB5500_DEVID_ADC,
13 AB5500_DEVID_LEDS,
14 AB5500_DEVID_POWER,
15 AB5500_DEVID_REGULATORS,
16 AB5500_DEVID_SIM,
17 AB5500_DEVID_RTC,
18 AB5500_DEVID_CHARGER,
19 AB5500_DEVID_FUELGAUGE,
20 AB5500_DEVID_VIBRATOR,
21 AB5500_DEVID_CODEC,
22 AB5500_DEVID_USB,
23 AB5500_DEVID_OTP,
24 AB5500_DEVID_VIDEO,
25 AB5500_DEVID_DBIECI,
26 AB5500_DEVID_ONSWA,
27 AB5500_NUM_DEVICES,
28};
29
30enum ab5500_banks {
31 AB5500_BANK_VIT_IO_I2C_CLK_TST_OTP = 0,
32 AB5500_BANK_VDDDIG_IO_I2C_CLK_TST = 1,
33 AB5500_BANK_VDENC = 2,
34 AB5500_BANK_SIM_USBSIM = 3,
35 AB5500_BANK_LED = 4,
36 AB5500_BANK_ADC = 5,
37 AB5500_BANK_RTC = 6,
38 AB5500_BANK_STARTUP = 7,
39 AB5500_BANK_DBI_ECI = 8,
40 AB5500_BANK_CHG = 9,
41 AB5500_BANK_FG_BATTCOM_ACC = 10,
42 AB5500_BANK_USB = 11,
43 AB5500_BANK_IT = 12,
44 AB5500_BANK_VIBRA = 13,
45 AB5500_BANK_AUDIO_HEADSETUSB = 14,
46 AB5500_NUM_BANKS = 15,
47};
48
49enum ab5500_banks_addr {
50 AB5500_ADDR_VIT_IO_I2C_CLK_TST_OTP = 0x4A,
51 AB5500_ADDR_VDDDIG_IO_I2C_CLK_TST = 0x4B,
52 AB5500_ADDR_VDENC = 0x06,
53 AB5500_ADDR_SIM_USBSIM = 0x04,
54 AB5500_ADDR_LED = 0x10,
55 AB5500_ADDR_ADC = 0x0A,
56 AB5500_ADDR_RTC = 0x0F,
57 AB5500_ADDR_STARTUP = 0x03,
58 AB5500_ADDR_DBI_ECI = 0x07,
59 AB5500_ADDR_CHG = 0x0B,
60 AB5500_ADDR_FG_BATTCOM_ACC = 0x0C,
61 AB5500_ADDR_USB = 0x05,
62 AB5500_ADDR_IT = 0x0E,
63 AB5500_ADDR_VIBRA = 0x02,
64 AB5500_ADDR_AUDIO_HEADSETUSB = 0x0D,
65};
66
67/*
68 * Interrupt register offsets
69 * Bank : 0x0E
70 */
71#define AB5500_IT_SOURCE0_REG 0x20
72#define AB5500_IT_SOURCE1_REG 0x21
73#define AB5500_IT_SOURCE2_REG 0x22
74#define AB5500_IT_SOURCE3_REG 0x23
75#define AB5500_IT_SOURCE4_REG 0x24
76#define AB5500_IT_SOURCE5_REG 0x25
77#define AB5500_IT_SOURCE6_REG 0x26
78#define AB5500_IT_SOURCE7_REG 0x27
79#define AB5500_IT_SOURCE8_REG 0x28
80#define AB5500_IT_SOURCE9_REG 0x29
81#define AB5500_IT_SOURCE10_REG 0x2A
82#define AB5500_IT_SOURCE11_REG 0x2B
83#define AB5500_IT_SOURCE12_REG 0x2C
84#define AB5500_IT_SOURCE13_REG 0x2D
85#define AB5500_IT_SOURCE14_REG 0x2E
86#define AB5500_IT_SOURCE15_REG 0x2F
87#define AB5500_IT_SOURCE16_REG 0x30
88#define AB5500_IT_SOURCE17_REG 0x31
89#define AB5500_IT_SOURCE18_REG 0x32
90#define AB5500_IT_SOURCE19_REG 0x33
91#define AB5500_IT_SOURCE20_REG 0x34
92#define AB5500_IT_SOURCE21_REG 0x35
93#define AB5500_IT_SOURCE22_REG 0x36
94#define AB5500_IT_SOURCE23_REG 0x37
95
96#define AB5500_NUM_IRQ_REGS 23
97
98/**
99 * struct ab5500
100 * @access_mutex: lock out concurrent accesses to the AB registers
101 * @dev: a pointer to the device struct for this chip driver
102 * @ab5500_irq: the analog baseband irq
103 * @irq_base: the platform configuration irq base for subdevices
104 * @chip_name: name of this chip variant
105 * @chip_id: 8 bit chip ID for this chip variant
106 * @irq_lock: a lock to protect the mask
107 * @abb_events: a local bit mask of the prcmu wakeup events
108 * @event_mask: a local copy of the mask event registers
109 * @last_event_mask: a copy of the last event_mask written to hardware
110 * @startup_events: a copy of the first reading of the event registers
111 * @startup_events_read: whether the first events have been read
112 */
113struct ab5500 {
114 struct mutex access_mutex;
115 struct device *dev;
116 unsigned int ab5500_irq;
117 unsigned int irq_base;
118 char chip_name[32];
119 u8 chip_id;
120 struct mutex irq_lock;
121 u32 abb_events;
122 u8 mask[AB5500_NUM_IRQ_REGS];
123 u8 oldmask[AB5500_NUM_IRQ_REGS];
124 u8 startup_events[AB5500_NUM_IRQ_REGS];
125 bool startup_events_read;
126#ifdef CONFIG_DEBUG_FS
127 unsigned int debug_bank;
128 unsigned int debug_address;
129#endif
130};
131
132struct ab5500_platform_data {
133 struct {unsigned int base; unsigned int count; } irq;
134 void *dev_data[AB5500_NUM_DEVICES];
135 struct abx500_init_settings *init_settings;
136 unsigned int init_settings_sz;
137 bool pm_power_off;
138};
139
140#endif /* MFD_AB5500_H */
diff --git a/include/linux/mfd/db5500-prcmu.h b/include/linux/mfd/db5500-prcmu.h
deleted file mode 100644
index 5a049dfaf153..000000000000
--- a/include/linux/mfd/db5500-prcmu.h
+++ /dev/null
@@ -1,105 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 *
6 * U5500 PRCMU API.
7 */
8#ifndef __MFD_DB5500_PRCMU_H
9#define __MFD_DB5500_PRCMU_H
10
11static inline int prcmu_resetout(u8 resoutn, u8 state)
12{
13 return 0;
14}
15
16static inline int db5500_prcmu_set_epod(u16 epod_id, u8 epod_state)
17{
18 return 0;
19}
20
21static inline int db5500_prcmu_request_clock(u8 clock, bool enable)
22{
23 return 0;
24}
25
26static inline int db5500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
27 bool keep_ap_pll)
28{
29 return 0;
30}
31
32static inline int db5500_prcmu_config_esram0_deep_sleep(u8 state)
33{
34 return 0;
35}
36
37static inline u16 db5500_prcmu_get_reset_code(void)
38{
39 return 0;
40}
41
42static inline bool db5500_prcmu_is_ac_wake_requested(void)
43{
44 return 0;
45}
46
47static inline int db5500_prcmu_set_arm_opp(u8 opp)
48{
49 return 0;
50}
51
52static inline int db5500_prcmu_get_arm_opp(void)
53{
54 return 0;
55}
56
57static inline void db5500_prcmu_config_abb_event_readout(u32 abb_events) {}
58
59static inline void db5500_prcmu_get_abb_event_buffer(void __iomem **buf) {}
60
61static inline void db5500_prcmu_system_reset(u16 reset_code) {}
62
63static inline void db5500_prcmu_enable_wakeups(u32 wakeups) {}
64
65#ifdef CONFIG_MFD_DB5500_PRCMU
66
67void db5500_prcmu_early_init(void);
68int db5500_prcmu_set_display_clocks(void);
69int db5500_prcmu_disable_dsipll(void);
70int db5500_prcmu_enable_dsipll(void);
71int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
72int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
73
74#else /* !CONFIG_UX500_SOC_DB5500 */
75
76static inline void db5500_prcmu_early_init(void) {}
77
78static inline int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
79{
80 return -ENOSYS;
81}
82
83static inline int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
84{
85 return -ENOSYS;
86}
87
88static inline int db5500_prcmu_set_display_clocks(void)
89{
90 return 0;
91}
92
93static inline int db5500_prcmu_disable_dsipll(void)
94{
95 return 0;
96}
97
98static inline int db5500_prcmu_enable_dsipll(void)
99{
100 return 0;
101}
102
103#endif /* CONFIG_MFD_DB5500_PRCMU */
104
105#endif /* __MFD_DB5500_PRCMU_H */
diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h
index d7674eb7305f..5a13f93d8f1c 100644
--- a/include/linux/mfd/dbx500-prcmu.h
+++ b/include/linux/mfd/dbx500-prcmu.h
@@ -55,17 +55,6 @@ enum prcmu_wakeup_index {
55#define NUM_EPOD_ID 8 55#define NUM_EPOD_ID 8
56 56
57/* 57/*
58 * DB5500 EPODs
59 */
60#define DB5500_EPOD_ID_BASE 0x0100
61#define DB5500_EPOD_ID_SGA (DB5500_EPOD_ID_BASE + 0)
62#define DB5500_EPOD_ID_HVA (DB5500_EPOD_ID_BASE + 1)
63#define DB5500_EPOD_ID_SIA (DB5500_EPOD_ID_BASE + 2)
64#define DB5500_EPOD_ID_DISP (DB5500_EPOD_ID_BASE + 3)
65#define DB5500_EPOD_ID_ESRAM12 (DB5500_EPOD_ID_BASE + 6)
66#define DB5500_NUM_EPOD_ID 7
67
68/*
69 * state definition for EPOD (power domain) 58 * state definition for EPOD (power domain)
70 * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged 59 * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
71 * - EPOD_STATE_OFF: The EPOD is switched off 60 * - EPOD_STATE_OFF: The EPOD is switched off
@@ -80,29 +69,6 @@ enum prcmu_wakeup_index {
80#define EPOD_STATE_ON_CLK_OFF 0x03 69#define EPOD_STATE_ON_CLK_OFF 0x03
81#define EPOD_STATE_ON 0x04 70#define EPOD_STATE_ON 0x04
82 71
83/* DB5500 CLKOUT IDs */
84enum {
85 DB5500_CLKOUT0 = 0,
86 DB5500_CLKOUT1,
87};
88
89/* DB5500 CLKOUTx sources */
90enum {
91 DB5500_CLKOUT_REF_CLK_SEL0,
92 DB5500_CLKOUT_RTC_CLK0_SEL0,
93 DB5500_CLKOUT_ULP_CLK_SEL0,
94 DB5500_CLKOUT_STATIC0,
95 DB5500_CLKOUT_REFCLK,
96 DB5500_CLKOUT_ULPCLK,
97 DB5500_CLKOUT_ARMCLK,
98 DB5500_CLKOUT_SYSACC0CLK,
99 DB5500_CLKOUT_SOC0PLLCLK,
100 DB5500_CLKOUT_SOC1PLLCLK,
101 DB5500_CLKOUT_DDRPLLCLK,
102 DB5500_CLKOUT_TVCLK,
103 DB5500_CLKOUT_IRDACLK,
104};
105
106/* 72/*
107 * CLKOUT sources 73 * CLKOUT sources
108 */ 74 */
@@ -248,101 +214,66 @@ enum ddr_pwrst {
248}; 214};
249 215
250#include <linux/mfd/db8500-prcmu.h> 216#include <linux/mfd/db8500-prcmu.h>
251#include <linux/mfd/db5500-prcmu.h>
252 217
253#if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500) 218#if defined(CONFIG_UX500_SOC_DB8500)
254 219
255#include <mach/id.h> 220#include <mach/id.h>
256 221
257static inline void __init prcmu_early_init(void) 222static inline void __init prcmu_early_init(void)
258{ 223{
259 if (cpu_is_u5500()) 224 return db8500_prcmu_early_init();
260 return db5500_prcmu_early_init();
261 else
262 return db8500_prcmu_early_init();
263} 225}
264 226
265static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, 227static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
266 bool keep_ap_pll) 228 bool keep_ap_pll)
267{ 229{
268 if (cpu_is_u5500()) 230 return db8500_prcmu_set_power_state(state, keep_ulp_clk,
269 return db5500_prcmu_set_power_state(state, keep_ulp_clk, 231 keep_ap_pll);
270 keep_ap_pll);
271 else
272 return db8500_prcmu_set_power_state(state, keep_ulp_clk,
273 keep_ap_pll);
274} 232}
275 233
276static inline u8 prcmu_get_power_state_result(void) 234static inline u8 prcmu_get_power_state_result(void)
277{ 235{
278 if (cpu_is_u5500()) 236 return db8500_prcmu_get_power_state_result();
279 return -EINVAL;
280 else
281 return db8500_prcmu_get_power_state_result();
282} 237}
283 238
284static inline int prcmu_gic_decouple(void) 239static inline int prcmu_gic_decouple(void)
285{ 240{
286 if (cpu_is_u5500()) 241 return db8500_prcmu_gic_decouple();
287 return -EINVAL;
288 else
289 return db8500_prcmu_gic_decouple();
290} 242}
291 243
292static inline int prcmu_gic_recouple(void) 244static inline int prcmu_gic_recouple(void)
293{ 245{
294 if (cpu_is_u5500()) 246 return db8500_prcmu_gic_recouple();
295 return -EINVAL;
296 else
297 return db8500_prcmu_gic_recouple();
298} 247}
299 248
300static inline bool prcmu_gic_pending_irq(void) 249static inline bool prcmu_gic_pending_irq(void)
301{ 250{
302 if (cpu_is_u5500()) 251 return db8500_prcmu_gic_pending_irq();
303 return -EINVAL;
304 else
305 return db8500_prcmu_gic_pending_irq();
306} 252}
307 253
308static inline bool prcmu_is_cpu_in_wfi(int cpu) 254static inline bool prcmu_is_cpu_in_wfi(int cpu)
309{ 255{
310 if (cpu_is_u5500()) 256 return db8500_prcmu_is_cpu_in_wfi(cpu);
311 return -EINVAL;
312 else
313 return db8500_prcmu_is_cpu_in_wfi(cpu);
314} 257}
315 258
316static inline int prcmu_copy_gic_settings(void) 259static inline int prcmu_copy_gic_settings(void)
317{ 260{
318 if (cpu_is_u5500()) 261 return db8500_prcmu_copy_gic_settings();
319 return -EINVAL;
320 else
321 return db8500_prcmu_copy_gic_settings();
322} 262}
323 263
324static inline bool prcmu_pending_irq(void) 264static inline bool prcmu_pending_irq(void)
325{ 265{
326 if (cpu_is_u5500()) 266 return db8500_prcmu_pending_irq();
327 return -EINVAL;
328 else
329 return db8500_prcmu_pending_irq();
330} 267}
331 268
332static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) 269static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
333{ 270{
334 if (cpu_is_u5500()) 271 return db8500_prcmu_set_epod(epod_id, epod_state);
335 return -EINVAL;
336 else
337 return db8500_prcmu_set_epod(epod_id, epod_state);
338} 272}
339 273
340static inline void prcmu_enable_wakeups(u32 wakeups) 274static inline void prcmu_enable_wakeups(u32 wakeups)
341{ 275{
342 if (cpu_is_u5500()) 276 db8500_prcmu_enable_wakeups(wakeups);
343 db5500_prcmu_enable_wakeups(wakeups);
344 else
345 db8500_prcmu_enable_wakeups(wakeups);
346} 277}
347 278
348static inline void prcmu_disable_wakeups(void) 279static inline void prcmu_disable_wakeups(void)
@@ -352,18 +283,12 @@ static inline void prcmu_disable_wakeups(void)
352 283
353static inline void prcmu_config_abb_event_readout(u32 abb_events) 284static inline void prcmu_config_abb_event_readout(u32 abb_events)
354{ 285{
355 if (cpu_is_u5500()) 286 db8500_prcmu_config_abb_event_readout(abb_events);
356 db5500_prcmu_config_abb_event_readout(abb_events);
357 else
358 db8500_prcmu_config_abb_event_readout(abb_events);
359} 287}
360 288
361static inline void prcmu_get_abb_event_buffer(void __iomem **buf) 289static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
362{ 290{
363 if (cpu_is_u5500()) 291 db8500_prcmu_get_abb_event_buffer(buf);
364 db5500_prcmu_get_abb_event_buffer(buf);
365 else
366 db8500_prcmu_get_abb_event_buffer(buf);
367} 292}
368 293
369int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); 294int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
@@ -374,10 +299,7 @@ int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
374 299
375static inline int prcmu_request_clock(u8 clock, bool enable) 300static inline int prcmu_request_clock(u8 clock, bool enable)
376{ 301{
377 if (cpu_is_u5500()) 302 return db8500_prcmu_request_clock(clock, enable);
378 return db5500_prcmu_request_clock(clock, enable);
379 else
380 return db8500_prcmu_request_clock(clock, enable);
381} 303}
382 304
383unsigned long prcmu_clock_rate(u8 clock); 305unsigned long prcmu_clock_rate(u8 clock);
@@ -386,211 +308,133 @@ int prcmu_set_clock_rate(u8 clock, unsigned long rate);
386 308
387static inline int prcmu_set_ddr_opp(u8 opp) 309static inline int prcmu_set_ddr_opp(u8 opp)
388{ 310{
389 if (cpu_is_u5500()) 311 return db8500_prcmu_set_ddr_opp(opp);
390 return -EINVAL;
391 else
392 return db8500_prcmu_set_ddr_opp(opp);
393} 312}
394static inline int prcmu_get_ddr_opp(void) 313static inline int prcmu_get_ddr_opp(void)
395{ 314{
396 if (cpu_is_u5500()) 315 return db8500_prcmu_get_ddr_opp();
397 return -EINVAL;
398 else
399 return db8500_prcmu_get_ddr_opp();
400} 316}
401 317
402static inline int prcmu_set_arm_opp(u8 opp) 318static inline int prcmu_set_arm_opp(u8 opp)
403{ 319{
404 if (cpu_is_u5500()) 320 return db8500_prcmu_set_arm_opp(opp);
405 return -EINVAL;
406 else
407 return db8500_prcmu_set_arm_opp(opp);
408} 321}
409 322
410static inline int prcmu_get_arm_opp(void) 323static inline int prcmu_get_arm_opp(void)
411{ 324{
412 if (cpu_is_u5500()) 325 return db8500_prcmu_get_arm_opp();
413 return -EINVAL;
414 else
415 return db8500_prcmu_get_arm_opp();
416} 326}
417 327
418static inline int prcmu_set_ape_opp(u8 opp) 328static inline int prcmu_set_ape_opp(u8 opp)
419{ 329{
420 if (cpu_is_u5500()) 330 return db8500_prcmu_set_ape_opp(opp);
421 return -EINVAL;
422 else
423 return db8500_prcmu_set_ape_opp(opp);
424} 331}
425 332
426static inline int prcmu_get_ape_opp(void) 333static inline int prcmu_get_ape_opp(void)
427{ 334{
428 if (cpu_is_u5500()) 335 return db8500_prcmu_get_ape_opp();
429 return -EINVAL;
430 else
431 return db8500_prcmu_get_ape_opp();
432} 336}
433 337
434static inline void prcmu_system_reset(u16 reset_code) 338static inline void prcmu_system_reset(u16 reset_code)
435{ 339{
436 if (cpu_is_u5500()) 340 return db8500_prcmu_system_reset(reset_code);
437 return db5500_prcmu_system_reset(reset_code);
438 else
439 return db8500_prcmu_system_reset(reset_code);
440} 341}
441 342
442static inline u16 prcmu_get_reset_code(void) 343static inline u16 prcmu_get_reset_code(void)
443{ 344{
444 if (cpu_is_u5500()) 345 return db8500_prcmu_get_reset_code();
445 return db5500_prcmu_get_reset_code();
446 else
447 return db8500_prcmu_get_reset_code();
448} 346}
449 347
450void prcmu_ac_wake_req(void); 348void prcmu_ac_wake_req(void);
451void prcmu_ac_sleep_req(void); 349void prcmu_ac_sleep_req(void);
452static inline void prcmu_modem_reset(void) 350static inline void prcmu_modem_reset(void)
453{ 351{
454 if (cpu_is_u5500()) 352 return db8500_prcmu_modem_reset();
455 return;
456 else
457 return db8500_prcmu_modem_reset();
458} 353}
459 354
460static inline bool prcmu_is_ac_wake_requested(void) 355static inline bool prcmu_is_ac_wake_requested(void)
461{ 356{
462 if (cpu_is_u5500()) 357 return db8500_prcmu_is_ac_wake_requested();
463 return db5500_prcmu_is_ac_wake_requested();
464 else
465 return db8500_prcmu_is_ac_wake_requested();
466} 358}
467 359
468static inline int prcmu_set_display_clocks(void) 360static inline int prcmu_set_display_clocks(void)
469{ 361{
470 if (cpu_is_u5500()) 362 return db8500_prcmu_set_display_clocks();
471 return db5500_prcmu_set_display_clocks();
472 else
473 return db8500_prcmu_set_display_clocks();
474} 363}
475 364
476static inline int prcmu_disable_dsipll(void) 365static inline int prcmu_disable_dsipll(void)
477{ 366{
478 if (cpu_is_u5500()) 367 return db8500_prcmu_disable_dsipll();
479 return db5500_prcmu_disable_dsipll();
480 else
481 return db8500_prcmu_disable_dsipll();
482} 368}
483 369
484static inline int prcmu_enable_dsipll(void) 370static inline int prcmu_enable_dsipll(void)
485{ 371{
486 if (cpu_is_u5500()) 372 return db8500_prcmu_enable_dsipll();
487 return db5500_prcmu_enable_dsipll();
488 else
489 return db8500_prcmu_enable_dsipll();
490} 373}
491 374
492static inline int prcmu_config_esram0_deep_sleep(u8 state) 375static inline int prcmu_config_esram0_deep_sleep(u8 state)
493{ 376{
494 if (cpu_is_u5500()) 377 return db8500_prcmu_config_esram0_deep_sleep(state);
495 return -EINVAL;
496 else
497 return db8500_prcmu_config_esram0_deep_sleep(state);
498} 378}
499 379
500static inline int prcmu_config_hotdog(u8 threshold) 380static inline int prcmu_config_hotdog(u8 threshold)
501{ 381{
502 if (cpu_is_u5500()) 382 return db8500_prcmu_config_hotdog(threshold);
503 return -EINVAL;
504 else
505 return db8500_prcmu_config_hotdog(threshold);
506} 383}
507 384
508static inline int prcmu_config_hotmon(u8 low, u8 high) 385static inline int prcmu_config_hotmon(u8 low, u8 high)
509{ 386{
510 if (cpu_is_u5500()) 387 return db8500_prcmu_config_hotmon(low, high);
511 return -EINVAL;
512 else
513 return db8500_prcmu_config_hotmon(low, high);
514} 388}
515 389
516static inline int prcmu_start_temp_sense(u16 cycles32k) 390static inline int prcmu_start_temp_sense(u16 cycles32k)
517{ 391{
518 if (cpu_is_u5500()) 392 return db8500_prcmu_start_temp_sense(cycles32k);
519 return -EINVAL;
520 else
521 return db8500_prcmu_start_temp_sense(cycles32k);
522} 393}
523 394
524static inline int prcmu_stop_temp_sense(void) 395static inline int prcmu_stop_temp_sense(void)
525{ 396{
526 if (cpu_is_u5500()) 397 return db8500_prcmu_stop_temp_sense();
527 return -EINVAL;
528 else
529 return db8500_prcmu_stop_temp_sense();
530} 398}
531 399
532static inline u32 prcmu_read(unsigned int reg) 400static inline u32 prcmu_read(unsigned int reg)
533{ 401{
534 if (cpu_is_u5500()) 402 return db8500_prcmu_read(reg);
535 return -EINVAL;
536 else
537 return db8500_prcmu_read(reg);
538} 403}
539 404
540static inline void prcmu_write(unsigned int reg, u32 value) 405static inline void prcmu_write(unsigned int reg, u32 value)
541{ 406{
542 if (cpu_is_u5500()) 407 db8500_prcmu_write(reg, value);
543 return;
544 else
545 db8500_prcmu_write(reg, value);
546} 408}
547 409
548static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) 410static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
549{ 411{
550 if (cpu_is_u5500()) 412 db8500_prcmu_write_masked(reg, mask, value);
551 return;
552 else
553 db8500_prcmu_write_masked(reg, mask, value);
554} 413}
555 414
556static inline int prcmu_enable_a9wdog(u8 id) 415static inline int prcmu_enable_a9wdog(u8 id)
557{ 416{
558 if (cpu_is_u5500()) 417 return db8500_prcmu_enable_a9wdog(id);
559 return -EINVAL;
560 else
561 return db8500_prcmu_enable_a9wdog(id);
562} 418}
563 419
564static inline int prcmu_disable_a9wdog(u8 id) 420static inline int prcmu_disable_a9wdog(u8 id)
565{ 421{
566 if (cpu_is_u5500()) 422 return db8500_prcmu_disable_a9wdog(id);
567 return -EINVAL;
568 else
569 return db8500_prcmu_disable_a9wdog(id);
570} 423}
571 424
572static inline int prcmu_kick_a9wdog(u8 id) 425static inline int prcmu_kick_a9wdog(u8 id)
573{ 426{
574 if (cpu_is_u5500()) 427 return db8500_prcmu_kick_a9wdog(id);
575 return -EINVAL;
576 else
577 return db8500_prcmu_kick_a9wdog(id);
578} 428}
579 429
580static inline int prcmu_load_a9wdog(u8 id, u32 timeout) 430static inline int prcmu_load_a9wdog(u8 id, u32 timeout)
581{ 431{
582 if (cpu_is_u5500()) 432 return db8500_prcmu_load_a9wdog(id, timeout);
583 return -EINVAL;
584 else
585 return db8500_prcmu_load_a9wdog(id, timeout);
586} 433}
587 434
588static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off) 435static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
589{ 436{
590 if (cpu_is_u5500()) 437 return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
591 return -EINVAL;
592 else
593 return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
594} 438}
595#else 439#else
596 440
@@ -768,7 +612,7 @@ static inline void prcmu_clear(unsigned int reg, u32 bits)
768 prcmu_write_masked(reg, bits, 0); 612 prcmu_write_masked(reg, bits, 0);
769} 613}
770 614
771#if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500) 615#if defined(CONFIG_UX500_SOC_DB8500)
772 616
773/** 617/**
774 * prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1. 618 * prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1.