mfd: rtsx: Replace TAB by SPC after #define

Re-format coding-style, using uniform SPC after "#define" keyword instead of mixing using TAB and SPC. Signed-off-by: Micky Ching <micky_ching@realsil.com.cn> Signed-off-by: Lee Jones <lee.jones@linaro.org>
author: Micky Ching <micky_ching@realsil.com.cn> 2015-02-25 00:50:08 -0500
committer: Lee Jones <lee.jones@linaro.org> 2015-03-03 11:41:16 -0500
commit: 84f00b1b9631319361f6c36e2f5a8e833d09af5b (patch)
tree: 1dbd80e48ce86565ff9083fc41f554148d92e6e6 /include/linux/mfd
parent: b10848e6f9fa7638fc0713695a12c0735ffb52b7 (diff)
1 files changed, 127 insertions, 127 deletions
diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h
index 0c12628e91c6..a9c2a14fd521 100644
--- a/include/linux/mfd/rtsx_pci.h
+++ b/include/linux/mfd/rtsx_pci.h
@@ -175,9 +175,9 @@
 /* CARD_SHARE_MODE */
 #define CARD_SHARE_MASK                 0x0F
 #define CARD_SHARE_MULTI_LUN            0x00
-#define CARD_SHARE_NORMAL               0x00
+#define CARD_SHARE_NORMAL               0x00
-#define CARD_SHARE_48_SD                0x04
+#define CARD_SHARE_48_SD                0x04
-#define CARD_SHARE_48_MS                0x08
+#define CARD_SHARE_48_MS                0x08
 /* CARD_SHARE_MODE for barossa */
 #define CARD_SHARE_BAROSSA_SD           0x01
 #define CARD_SHARE_BAROSSA_MS           0x02
@@ -249,76 +249,76 @@
 #define CD_AUTO_DISABLE                 0x40
 /* SD_STAT1 */
-#define SD_CRC7_ERR                     0x80
+#define SD_CRC7_ERR                     0x80
-#define SD_CRC16_ERR                    0x40
+#define SD_CRC16_ERR                    0x40
-#define SD_CRC_WRITE_ERR                0x20
+#define SD_CRC_WRITE_ERR                0x20
-#define SD_CRC_WRITE_ERR_MASK           0x1C
+#define SD_CRC_WRITE_ERR_MASK           0x1C
-#define GET_CRC_TIME_OUT                0x02
+#define GET_CRC_TIME_OUT                0x02
-#define SD_TUNING_COMPARE_ERR           0x01
+#define SD_TUNING_COMPARE_ERR           0x01
 /* SD_STAT2 */
-#define SD_RSP_80CLK_TIMEOUT            0x01
+#define SD_RSP_80CLK_TIMEOUT            0x01
 /* SD_BUS_STAT */
-#define SD_CLK_TOGGLE_EN                0x80
+#define SD_CLK_TOGGLE_EN                0x80
-#define SD_CLK_FORCE_STOP               0x40
+#define SD_CLK_FORCE_STOP               0x40
-#define SD_DAT3_STATUS                  0x10
+#define SD_DAT3_STATUS                  0x10
-#define SD_DAT2_STATUS                  0x08
+#define SD_DAT2_STATUS                  0x08
-#define SD_DAT1_STATUS                  0x04
+#define SD_DAT1_STATUS                  0x04
-#define SD_DAT0_STATUS                  0x02
+#define SD_DAT0_STATUS                  0x02
-#define SD_CMD_STATUS                   0x01
+#define SD_CMD_STATUS                   0x01
 /* SD_PAD_CTL */
-#define SD_IO_USING_1V8                 0x80
+#define SD_IO_USING_1V8                 0x80
-#define SD_IO_USING_3V3                 0x7F
+#define SD_IO_USING_3V3                 0x7F
-#define TYPE_A_DRIVING                  0x00
+#define TYPE_A_DRIVING                  0x00
-#define TYPE_B_DRIVING                  0x01
+#define TYPE_B_DRIVING                  0x01
-#define TYPE_C_DRIVING                  0x02
+#define TYPE_C_DRIVING                  0x02
-#define TYPE_D_DRIVING                  0x03
+#define TYPE_D_DRIVING                  0x03
 /* SD_SAMPLE_POINT_CTL */
-#define DDR_FIX_RX_DAT                  0x00
+#define DDR_FIX_RX_DAT                  0x00
-#define DDR_VAR_RX_DAT                  0x80
+#define DDR_VAR_RX_DAT                  0x80
-#define DDR_FIX_RX_DAT_EDGE             0x00
+#define DDR_FIX_RX_DAT_EDGE             0x00
-#define DDR_FIX_RX_DAT_14_DELAY         0x40
+#define DDR_FIX_RX_DAT_14_DELAY         0x40
-#define DDR_FIX_RX_CMD                  0x00
+#define DDR_FIX_RX_CMD                  0x00
-#define DDR_VAR_RX_CMD                  0x20
+#define DDR_VAR_RX_CMD                  0x20
-#define DDR_FIX_RX_CMD_POS_EDGE         0x00
+#define DDR_FIX_RX_CMD_POS_EDGE         0x00
-#define DDR_FIX_RX_CMD_14_DELAY         0x10
+#define DDR_FIX_RX_CMD_14_DELAY         0x10
-#define SD20_RX_POS_EDGE                0x00
+#define SD20_RX_POS_EDGE                0x00
-#define SD20_RX_14_DELAY                0x08
+#define SD20_RX_14_DELAY                0x08
 #define SD20_RX_SEL_MASK                0x08
 /* SD_PUSH_POINT_CTL */
-#define DDR_FIX_TX_CMD_DAT              0x00
+#define DDR_FIX_TX_CMD_DAT              0x00
-#define DDR_VAR_TX_CMD_DAT              0x80
+#define DDR_VAR_TX_CMD_DAT              0x80
-#define DDR_FIX_TX_DAT_14_TSU           0x00
+#define DDR_FIX_TX_DAT_14_TSU           0x00
-#define DDR_FIX_TX_DAT_12_TSU           0x40
+#define DDR_FIX_TX_DAT_12_TSU           0x40
-#define DDR_FIX_TX_CMD_NEG_EDGE         0x00
+#define DDR_FIX_TX_CMD_NEG_EDGE         0x00
-#define DDR_FIX_TX_CMD_14_AHEAD         0x20
+#define DDR_FIX_TX_CMD_14_AHEAD         0x20
-#define SD20_TX_NEG_EDGE                0x00
+#define SD20_TX_NEG_EDGE                0x00
-#define SD20_TX_14_AHEAD                0x10
+#define SD20_TX_14_AHEAD                0x10
 #define SD20_TX_SEL_MASK                0x10
-#define DDR_VAR_SDCLK_POL_SWAP          0x01
+#define DDR_VAR_SDCLK_POL_SWAP          0x01
 /* SD_TRANSFER */
-#define SD_TRANSFER_START               0x80
+#define SD_TRANSFER_START               0x80
-#define SD_TRANSFER_END                 0x40
+#define SD_TRANSFER_END                 0x40
 #define SD_STAT_IDLE                    0x20
-#define SD_TRANSFER_ERR                 0x10
+#define SD_TRANSFER_ERR                 0x10
 /* SD Transfer Mode definition */
-#define SD_TM_NORMAL_WRITE              0x00
+#define SD_TM_NORMAL_WRITE              0x00
-#define SD_TM_AUTO_WRITE_3              0x01
+#define SD_TM_AUTO_WRITE_3              0x01
-#define SD_TM_AUTO_WRITE_4              0x02
+#define SD_TM_AUTO_WRITE_4              0x02
-#define SD_TM_AUTO_READ_3               0x05
+#define SD_TM_AUTO_READ_3               0x05
-#define SD_TM_AUTO_READ_4               0x06
+#define SD_TM_AUTO_READ_4               0x06
-#define SD_TM_CMD_RSP                   0x08
+#define SD_TM_CMD_RSP                   0x08
-#define SD_TM_AUTO_WRITE_1              0x09
+#define SD_TM_AUTO_WRITE_1              0x09
-#define SD_TM_AUTO_WRITE_2              0x0A
+#define SD_TM_AUTO_WRITE_2              0x0A
-#define SD_TM_NORMAL_READ               0x0C
+#define SD_TM_NORMAL_READ               0x0C
-#define SD_TM_AUTO_READ_1               0x0D
+#define SD_TM_AUTO_READ_1               0x0D
-#define SD_TM_AUTO_READ_2               0x0E
+#define SD_TM_AUTO_READ_2               0x0E
-#define SD_TM_AUTO_TUNING               0x0F
+#define SD_TM_AUTO_TUNING               0x0F
 /* SD_VPTX_CTL / SD_VPRX_CTL */
 #define PHASE_CHANGE                    0x80
@@ -332,15 +332,15 @@
 /* SD Configure 1 Register */
 #define SD_CLK_DIVIDE_0                 0x00
-#define SD_CLK_DIVIDE_256               0xC0
+#define SD_CLK_DIVIDE_256               0xC0
-#define SD_CLK_DIVIDE_128               0x80
+#define SD_CLK_DIVIDE_128               0x80
-#define SD_BUS_WIDTH_1BIT               0x00
+#define SD_BUS_WIDTH_1BIT               0x00
-#define SD_BUS_WIDTH_4BIT               0x01
+#define SD_BUS_WIDTH_4BIT               0x01
-#define SD_BUS_WIDTH_8BIT               0x02
+#define SD_BUS_WIDTH_8BIT               0x02
-#define SD_ASYNC_FIFO_NOT_RST           0x10
+#define SD_ASYNC_FIFO_NOT_RST           0x10
-#define SD_20_MODE                      0x00
+#define SD_20_MODE                      0x00
-#define SD_DDR_MODE                     0x04
+#define SD_DDR_MODE                     0x04
-#define SD_30_MODE                      0x08
+#define SD_30_MODE                      0x08
 #define SD_CLK_DIVIDE_MASK              0xC0
@@ -415,71 +415,71 @@
 #define CLK_DIV_8                       0x04
 /* MS_CFG */
-#define SAMPLE_TIME_RISING              0x00
+#define SAMPLE_TIME_RISING              0x00
-#define SAMPLE_TIME_FALLING             0x80
+#define SAMPLE_TIME_FALLING             0x80
-#define PUSH_TIME_DEFAULT               0x00
+#define PUSH_TIME_DEFAULT               0x00
-#define PUSH_TIME_ODD                   0x40
+#define PUSH_TIME_ODD                   0x40
-#define NO_EXTEND_TOGGLE                0x00
+#define NO_EXTEND_TOGGLE                0x00
-#define EXTEND_TOGGLE_CHK               0x20
+#define EXTEND_TOGGLE_CHK               0x20
-#define MS_BUS_WIDTH_1                  0x00
+#define MS_BUS_WIDTH_1                  0x00
-#define MS_BUS_WIDTH_4                  0x10
+#define MS_BUS_WIDTH_4                  0x10
-#define MS_BUS_WIDTH_8                  0x18
+#define MS_BUS_WIDTH_8                  0x18
-#define MS_2K_SECTOR_MODE               0x04
+#define MS_2K_SECTOR_MODE               0x04
-#define MS_512_SECTOR_MODE              0x00
+#define MS_512_SECTOR_MODE              0x00
-#define MS_TOGGLE_TIMEOUT_EN            0x00
+#define MS_TOGGLE_TIMEOUT_EN            0x00
-#define MS_TOGGLE_TIMEOUT_DISEN         0x01
+#define MS_TOGGLE_TIMEOUT_DISEN         0x01
 #define MS_NO_CHECK_INT                 0x02
 /* MS_TRANS_CFG */
-#define WAIT_INT                        0x80
+#define WAIT_INT                        0x80
-#define NO_WAIT_INT                     0x00
+#define NO_WAIT_INT                     0x00
-#define NO_AUTO_READ_INT_REG            0x00
+#define NO_AUTO_READ_INT_REG            0x00
-#define AUTO_READ_INT_REG               0x40
+#define AUTO_READ_INT_REG               0x40
-#define MS_CRC16_ERR                    0x20
+#define MS_CRC16_ERR                    0x20
-#define MS_RDY_TIMEOUT                  0x10
+#define MS_RDY_TIMEOUT                  0x10
-#define MS_INT_CMDNK                    0x08
+#define MS_INT_CMDNK                    0x08
-#define MS_INT_BREQ                     0x04
+#define MS_INT_BREQ                     0x04
-#define MS_INT_ERR                      0x02
+#define MS_INT_ERR                      0x02
-#define MS_INT_CED                      0x01
+#define MS_INT_CED                      0x01
 /* MS_TRANSFER */
-#define MS_TRANSFER_START               0x80
+#define MS_TRANSFER_START               0x80
-#define MS_TRANSFER_END                 0x40
+#define MS_TRANSFER_END                 0x40
-#define MS_TRANSFER_ERR                 0x20
+#define MS_TRANSFER_ERR                 0x20
-#define MS_BS_STATE                     0x10
+#define MS_BS_STATE                     0x10
-#define MS_TM_READ_BYTES                0x00
+#define MS_TM_READ_BYTES                0x00
-#define MS_TM_NORMAL_READ               0x01
+#define MS_TM_NORMAL_READ               0x01
-#define MS_TM_WRITE_BYTES               0x04
+#define MS_TM_WRITE_BYTES               0x04
-#define MS_TM_NORMAL_WRITE              0x05
+#define MS_TM_NORMAL_WRITE              0x05
-#define MS_TM_AUTO_READ                 0x08
+#define MS_TM_AUTO_READ                 0x08
-#define MS_TM_AUTO_WRITE                0x0C
+#define MS_TM_AUTO_WRITE                0x0C
 /* SD Configure 2 Register */
-#define SD_CALCULATE_CRC7               0x00
+#define SD_CALCULATE_CRC7               0x00
-#define SD_NO_CALCULATE_CRC7            0x80
+#define SD_NO_CALCULATE_CRC7            0x80
-#define SD_CHECK_CRC16                  0x00
+#define SD_CHECK_CRC16                  0x00
-#define SD_NO_CHECK_CRC16               0x40
+#define SD_NO_CHECK_CRC16               0x40
 #define SD_NO_CHECK_WAIT_CRC_TO         0x20
-#define SD_WAIT_BUSY_END                0x08
+#define SD_WAIT_BUSY_END                0x08
-#define SD_NO_WAIT_BUSY_END             0x00
+#define SD_NO_WAIT_BUSY_END             0x00
-#define SD_CHECK_CRC7                   0x00
+#define SD_CHECK_CRC7                   0x00
-#define SD_NO_CHECK_CRC7                0x04
+#define SD_NO_CHECK_CRC7                0x04
-#define SD_RSP_LEN_0                    0x00
+#define SD_RSP_LEN_0                    0x00
-#define SD_RSP_LEN_6                    0x01
+#define SD_RSP_LEN_6                    0x01
-#define SD_RSP_LEN_17                   0x02
+#define SD_RSP_LEN_17                   0x02
 /* SD/MMC Response Type Definition */
-#define SD_RSP_TYPE_R0                  0x04
+#define SD_RSP_TYPE_R0                  0x04
-#define SD_RSP_TYPE_R1                  0x01
+#define SD_RSP_TYPE_R1                  0x01
-#define SD_RSP_TYPE_R1b                 0x09
+#define SD_RSP_TYPE_R1b                 0x09
-#define SD_RSP_TYPE_R2                  0x02
+#define SD_RSP_TYPE_R2                  0x02
-#define SD_RSP_TYPE_R3                  0x05
+#define SD_RSP_TYPE_R3                  0x05
-#define SD_RSP_TYPE_R4                  0x05
+#define SD_RSP_TYPE_R4                  0x05
-#define SD_RSP_TYPE_R5                  0x01
+#define SD_RSP_TYPE_R5                  0x01
-#define SD_RSP_TYPE_R6                  0x01
+#define SD_RSP_TYPE_R6                  0x01
-#define SD_RSP_TYPE_R7                  0x01
+#define SD_RSP_TYPE_R7                  0x01
 /* SD_CONFIGURE3 */
-#define SD_RSP_80CLK_TIMEOUT_EN         0x01
+#define SD_RSP_80CLK_TIMEOUT_EN         0x01
 /* Card Transfer Reset Register */
 #define SPI_STOP                        0x01
@@ -574,13 +574,13 @@
 #define SRCTL                           0xFC13
-#define DCM_DRP_CTL                     0xFC23
+#define DCM_DRP_CTL                     0xFC23
-#define DCM_DRP_TRIG                    0xFC24
+#define DCM_DRP_TRIG                    0xFC24
-#define DCM_DRP_CFG                     0xFC25
+#define DCM_DRP_CFG                     0xFC25
-#define DCM_DRP_WR_DATA_L               0xFC26
+#define DCM_DRP_WR_DATA_L               0xFC26
-#define DCM_DRP_WR_DATA_H               0xFC27
+#define DCM_DRP_WR_DATA_H               0xFC27
-#define DCM_DRP_RD_DATA_L               0xFC28
+#define DCM_DRP_RD_DATA_L               0xFC28
-#define DCM_DRP_RD_DATA_H               0xFC29
+#define DCM_DRP_RD_DATA_H               0xFC29
 #define SD_VPCLK0_CTL                   0xFC2A
 #define SD_VPCLK1_CTL                   0xFC2B
 #define SD_DCMPS0_CTL                   0xFC2C
author	Micky Ching <micky_ching@realsil.com.cn>	2015-02-25 00:50:08 -0500
committer	Lee Jones <lee.jones@linaro.org>	2015-03-03 11:41:16 -0500
commit	84f00b1b9631319361f6c36e2f5a8e833d09af5b (patch)
tree	1dbd80e48ce86565ff9083fc41f554148d92e6e6 /include/linux/mfd
parent	b10848e6f9fa7638fc0713695a12c0735ffb52b7 (diff)

diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h index 0c12628e91c6..a9c2a14fd521 100644 --- a/include/linux/mfd/rtsx_pci.h +++ b/include/linux/mfd/rtsx_pci.h
@@ -175,9 +175,9 @@
175	/* CARD_SHARE_MODE */	175	/* CARD_SHARE_MODE */
176	#define CARD_SHARE_MASK 0x0F	176	#define CARD_SHARE_MASK 0x0F
177	#define CARD_SHARE_MULTI_LUN 0x00	177	#define CARD_SHARE_MULTI_LUN 0x00
178	#define CARD_SHARE_NORMAL 0x00	178	#define CARD_SHARE_NORMAL 0x00
179	#define CARD_SHARE_48_SD 0x04	179	#define CARD_SHARE_48_SD 0x04
180	#define CARD_SHARE_48_MS 0x08	180	#define CARD_SHARE_48_MS 0x08
181	/* CARD_SHARE_MODE for barossa */	181	/* CARD_SHARE_MODE for barossa */
182	#define CARD_SHARE_BAROSSA_SD 0x01	182	#define CARD_SHARE_BAROSSA_SD 0x01
183	#define CARD_SHARE_BAROSSA_MS 0x02	183	#define CARD_SHARE_BAROSSA_MS 0x02
@@ -249,76 +249,76 @@
249	#define CD_AUTO_DISABLE 0x40	249	#define CD_AUTO_DISABLE 0x40
250		250
251	/* SD_STAT1 */	251	/* SD_STAT1 */
252	#define SD_CRC7_ERR 0x80	252	#define SD_CRC7_ERR 0x80
253	#define SD_CRC16_ERR 0x40	253	#define SD_CRC16_ERR 0x40
254	#define SD_CRC_WRITE_ERR 0x20	254	#define SD_CRC_WRITE_ERR 0x20
255	#define SD_CRC_WRITE_ERR_MASK 0x1C	255	#define SD_CRC_WRITE_ERR_MASK 0x1C
256	#define GET_CRC_TIME_OUT 0x02	256	#define GET_CRC_TIME_OUT 0x02
257	#define SD_TUNING_COMPARE_ERR 0x01	257	#define SD_TUNING_COMPARE_ERR 0x01
258		258
259	/* SD_STAT2 */	259	/* SD_STAT2 */
260	#define SD_RSP_80CLK_TIMEOUT 0x01	260	#define SD_RSP_80CLK_TIMEOUT 0x01
261		261
262	/* SD_BUS_STAT */	262	/* SD_BUS_STAT */
263	#define SD_CLK_TOGGLE_EN 0x80	263	#define SD_CLK_TOGGLE_EN 0x80
264	#define SD_CLK_FORCE_STOP 0x40	264	#define SD_CLK_FORCE_STOP 0x40
265	#define SD_DAT3_STATUS 0x10	265	#define SD_DAT3_STATUS 0x10
266	#define SD_DAT2_STATUS 0x08	266	#define SD_DAT2_STATUS 0x08
267	#define SD_DAT1_STATUS 0x04	267	#define SD_DAT1_STATUS 0x04
268	#define SD_DAT0_STATUS 0x02	268	#define SD_DAT0_STATUS 0x02
269	#define SD_CMD_STATUS 0x01	269	#define SD_CMD_STATUS 0x01
270		270
271	/* SD_PAD_CTL */	271	/* SD_PAD_CTL */
272	#define SD_IO_USING_1V8 0x80	272	#define SD_IO_USING_1V8 0x80
273	#define SD_IO_USING_3V3 0x7F	273	#define SD_IO_USING_3V3 0x7F
274	#define TYPE_A_DRIVING 0x00	274	#define TYPE_A_DRIVING 0x00
275	#define TYPE_B_DRIVING 0x01	275	#define TYPE_B_DRIVING 0x01
276	#define TYPE_C_DRIVING 0x02	276	#define TYPE_C_DRIVING 0x02
277	#define TYPE_D_DRIVING 0x03	277	#define TYPE_D_DRIVING 0x03
278		278
279	/* SD_SAMPLE_POINT_CTL */	279	/* SD_SAMPLE_POINT_CTL */
280	#define DDR_FIX_RX_DAT 0x00	280	#define DDR_FIX_RX_DAT 0x00
281	#define DDR_VAR_RX_DAT 0x80	281	#define DDR_VAR_RX_DAT 0x80
282	#define DDR_FIX_RX_DAT_EDGE 0x00	282	#define DDR_FIX_RX_DAT_EDGE 0x00
283	#define DDR_FIX_RX_DAT_14_DELAY 0x40	283	#define DDR_FIX_RX_DAT_14_DELAY 0x40
284	#define DDR_FIX_RX_CMD 0x00	284	#define DDR_FIX_RX_CMD 0x00
285	#define DDR_VAR_RX_CMD 0x20	285	#define DDR_VAR_RX_CMD 0x20
286	#define DDR_FIX_RX_CMD_POS_EDGE 0x00	286	#define DDR_FIX_RX_CMD_POS_EDGE 0x00
287	#define DDR_FIX_RX_CMD_14_DELAY 0x10	287	#define DDR_FIX_RX_CMD_14_DELAY 0x10
288	#define SD20_RX_POS_EDGE 0x00	288	#define SD20_RX_POS_EDGE 0x00
289	#define SD20_RX_14_DELAY 0x08	289	#define SD20_RX_14_DELAY 0x08
290	#define SD20_RX_SEL_MASK 0x08	290	#define SD20_RX_SEL_MASK 0x08
291		291
292	/* SD_PUSH_POINT_CTL */	292	/* SD_PUSH_POINT_CTL */
293	#define DDR_FIX_TX_CMD_DAT 0x00	293	#define DDR_FIX_TX_CMD_DAT 0x00
294	#define DDR_VAR_TX_CMD_DAT 0x80	294	#define DDR_VAR_TX_CMD_DAT 0x80
295	#define DDR_FIX_TX_DAT_14_TSU 0x00	295	#define DDR_FIX_TX_DAT_14_TSU 0x00
296	#define DDR_FIX_TX_DAT_12_TSU 0x40	296	#define DDR_FIX_TX_DAT_12_TSU 0x40
297	#define DDR_FIX_TX_CMD_NEG_EDGE 0x00	297	#define DDR_FIX_TX_CMD_NEG_EDGE 0x00
298	#define DDR_FIX_TX_CMD_14_AHEAD 0x20	298	#define DDR_FIX_TX_CMD_14_AHEAD 0x20
299	#define SD20_TX_NEG_EDGE 0x00	299	#define SD20_TX_NEG_EDGE 0x00
300	#define SD20_TX_14_AHEAD 0x10	300	#define SD20_TX_14_AHEAD 0x10
301	#define SD20_TX_SEL_MASK 0x10	301	#define SD20_TX_SEL_MASK 0x10
302	#define DDR_VAR_SDCLK_POL_SWAP 0x01	302	#define DDR_VAR_SDCLK_POL_SWAP 0x01
303		303
304	/* SD_TRANSFER */	304	/* SD_TRANSFER */
305	#define SD_TRANSFER_START 0x80	305	#define SD_TRANSFER_START 0x80
306	#define SD_TRANSFER_END 0x40	306	#define SD_TRANSFER_END 0x40
307	#define SD_STAT_IDLE 0x20	307	#define SD_STAT_IDLE 0x20
308	#define SD_TRANSFER_ERR 0x10	308	#define SD_TRANSFER_ERR 0x10
309	/* SD Transfer Mode definition */	309	/* SD Transfer Mode definition */
310	#define SD_TM_NORMAL_WRITE 0x00	310	#define SD_TM_NORMAL_WRITE 0x00
311	#define SD_TM_AUTO_WRITE_3 0x01	311	#define SD_TM_AUTO_WRITE_3 0x01
312	#define SD_TM_AUTO_WRITE_4 0x02	312	#define SD_TM_AUTO_WRITE_4 0x02
313	#define SD_TM_AUTO_READ_3 0x05	313	#define SD_TM_AUTO_READ_3 0x05
314	#define SD_TM_AUTO_READ_4 0x06	314	#define SD_TM_AUTO_READ_4 0x06
315	#define SD_TM_CMD_RSP 0x08	315	#define SD_TM_CMD_RSP 0x08
316	#define SD_TM_AUTO_WRITE_1 0x09	316	#define SD_TM_AUTO_WRITE_1 0x09
317	#define SD_TM_AUTO_WRITE_2 0x0A	317	#define SD_TM_AUTO_WRITE_2 0x0A
318	#define SD_TM_NORMAL_READ 0x0C	318	#define SD_TM_NORMAL_READ 0x0C
319	#define SD_TM_AUTO_READ_1 0x0D	319	#define SD_TM_AUTO_READ_1 0x0D
320	#define SD_TM_AUTO_READ_2 0x0E	320	#define SD_TM_AUTO_READ_2 0x0E
321	#define SD_TM_AUTO_TUNING 0x0F	321	#define SD_TM_AUTO_TUNING 0x0F
322		322
323	/* SD_VPTX_CTL / SD_VPRX_CTL */	323	/* SD_VPTX_CTL / SD_VPRX_CTL */
324	#define PHASE_CHANGE 0x80	324	#define PHASE_CHANGE 0x80
@@ -332,15 +332,15 @@
332		332
333	/* SD Configure 1 Register */	333	/* SD Configure 1 Register */
334	#define SD_CLK_DIVIDE_0 0x00	334	#define SD_CLK_DIVIDE_0 0x00
335	#define SD_CLK_DIVIDE_256 0xC0	335	#define SD_CLK_DIVIDE_256 0xC0
336	#define SD_CLK_DIVIDE_128 0x80	336	#define SD_CLK_DIVIDE_128 0x80
337	#define SD_BUS_WIDTH_1BIT 0x00	337	#define SD_BUS_WIDTH_1BIT 0x00
338	#define SD_BUS_WIDTH_4BIT 0x01	338	#define SD_BUS_WIDTH_4BIT 0x01
339	#define SD_BUS_WIDTH_8BIT 0x02	339	#define SD_BUS_WIDTH_8BIT 0x02
340	#define SD_ASYNC_FIFO_NOT_RST 0x10	340	#define SD_ASYNC_FIFO_NOT_RST 0x10
341	#define SD_20_MODE 0x00	341	#define SD_20_MODE 0x00
342	#define SD_DDR_MODE 0x04	342	#define SD_DDR_MODE 0x04
343	#define SD_30_MODE 0x08	343	#define SD_30_MODE 0x08
344		344
345	#define SD_CLK_DIVIDE_MASK 0xC0	345	#define SD_CLK_DIVIDE_MASK 0xC0
346		346
@@ -415,71 +415,71 @@
415	#define CLK_DIV_8 0x04	415	#define CLK_DIV_8 0x04
416		416
417	/* MS_CFG */	417	/* MS_CFG */
418	#define SAMPLE_TIME_RISING 0x00	418	#define SAMPLE_TIME_RISING 0x00
419	#define SAMPLE_TIME_FALLING 0x80	419	#define SAMPLE_TIME_FALLING 0x80
420	#define PUSH_TIME_DEFAULT 0x00	420	#define PUSH_TIME_DEFAULT 0x00
421	#define PUSH_TIME_ODD 0x40	421	#define PUSH_TIME_ODD 0x40
422	#define NO_EXTEND_TOGGLE 0x00	422	#define NO_EXTEND_TOGGLE 0x00
423	#define EXTEND_TOGGLE_CHK 0x20	423	#define EXTEND_TOGGLE_CHK 0x20
424	#define MS_BUS_WIDTH_1 0x00	424	#define MS_BUS_WIDTH_1 0x00
425	#define MS_BUS_WIDTH_4 0x10	425	#define MS_BUS_WIDTH_4 0x10
426	#define MS_BUS_WIDTH_8 0x18	426	#define MS_BUS_WIDTH_8 0x18
427	#define MS_2K_SECTOR_MODE 0x04	427	#define MS_2K_SECTOR_MODE 0x04
428	#define MS_512_SECTOR_MODE 0x00	428	#define MS_512_SECTOR_MODE 0x00
429	#define MS_TOGGLE_TIMEOUT_EN 0x00	429	#define MS_TOGGLE_TIMEOUT_EN 0x00
430	#define MS_TOGGLE_TIMEOUT_DISEN 0x01	430	#define MS_TOGGLE_TIMEOUT_DISEN 0x01
431	#define MS_NO_CHECK_INT 0x02	431	#define MS_NO_CHECK_INT 0x02
432		432
433	/* MS_TRANS_CFG */	433	/* MS_TRANS_CFG */
434	#define WAIT_INT 0x80	434	#define WAIT_INT 0x80
435	#define NO_WAIT_INT 0x00	435	#define NO_WAIT_INT 0x00
436	#define NO_AUTO_READ_INT_REG 0x00	436	#define NO_AUTO_READ_INT_REG 0x00
437	#define AUTO_READ_INT_REG 0x40	437	#define AUTO_READ_INT_REG 0x40
438	#define MS_CRC16_ERR 0x20	438	#define MS_CRC16_ERR 0x20
439	#define MS_RDY_TIMEOUT 0x10	439	#define MS_RDY_TIMEOUT 0x10
440	#define MS_INT_CMDNK 0x08	440	#define MS_INT_CMDNK 0x08
441	#define MS_INT_BREQ 0x04	441	#define MS_INT_BREQ 0x04
442	#define MS_INT_ERR 0x02	442	#define MS_INT_ERR 0x02
443	#define MS_INT_CED 0x01	443	#define MS_INT_CED 0x01
444		444
445	/* MS_TRANSFER */	445	/* MS_TRANSFER */
446	#define MS_TRANSFER_START 0x80	446	#define MS_TRANSFER_START 0x80
447	#define MS_TRANSFER_END 0x40	447	#define MS_TRANSFER_END 0x40
448	#define MS_TRANSFER_ERR 0x20	448	#define MS_TRANSFER_ERR 0x20
449	#define MS_BS_STATE 0x10	449	#define MS_BS_STATE 0x10
450	#define MS_TM_READ_BYTES 0x00	450	#define MS_TM_READ_BYTES 0x00
451	#define MS_TM_NORMAL_READ 0x01	451	#define MS_TM_NORMAL_READ 0x01
452	#define MS_TM_WRITE_BYTES 0x04	452	#define MS_TM_WRITE_BYTES 0x04
453	#define MS_TM_NORMAL_WRITE 0x05	453	#define MS_TM_NORMAL_WRITE 0x05
454	#define MS_TM_AUTO_READ 0x08	454	#define MS_TM_AUTO_READ 0x08
455	#define MS_TM_AUTO_WRITE 0x0C	455	#define MS_TM_AUTO_WRITE 0x0C
456		456
457	/* SD Configure 2 Register */	457	/* SD Configure 2 Register */
458	#define SD_CALCULATE_CRC7 0x00	458	#define SD_CALCULATE_CRC7 0x00
459	#define SD_NO_CALCULATE_CRC7 0x80	459	#define SD_NO_CALCULATE_CRC7 0x80
460	#define SD_CHECK_CRC16 0x00	460	#define SD_CHECK_CRC16 0x00
461	#define SD_NO_CHECK_CRC16 0x40	461	#define SD_NO_CHECK_CRC16 0x40
462	#define SD_NO_CHECK_WAIT_CRC_TO 0x20	462	#define SD_NO_CHECK_WAIT_CRC_TO 0x20
463	#define SD_WAIT_BUSY_END 0x08	463	#define SD_WAIT_BUSY_END 0x08
464	#define SD_NO_WAIT_BUSY_END 0x00	464	#define SD_NO_WAIT_BUSY_END 0x00
465	#define SD_CHECK_CRC7 0x00	465	#define SD_CHECK_CRC7 0x00
466	#define SD_NO_CHECK_CRC7 0x04	466	#define SD_NO_CHECK_CRC7 0x04
467	#define SD_RSP_LEN_0 0x00	467	#define SD_RSP_LEN_0 0x00
468	#define SD_RSP_LEN_6 0x01	468	#define SD_RSP_LEN_6 0x01
469	#define SD_RSP_LEN_17 0x02	469	#define SD_RSP_LEN_17 0x02
470	/* SD/MMC Response Type Definition */	470	/* SD/MMC Response Type Definition */
471	#define SD_RSP_TYPE_R0 0x04	471	#define SD_RSP_TYPE_R0 0x04
472	#define SD_RSP_TYPE_R1 0x01	472	#define SD_RSP_TYPE_R1 0x01
473	#define SD_RSP_TYPE_R1b 0x09	473	#define SD_RSP_TYPE_R1b 0x09
474	#define SD_RSP_TYPE_R2 0x02	474	#define SD_RSP_TYPE_R2 0x02
475	#define SD_RSP_TYPE_R3 0x05	475	#define SD_RSP_TYPE_R3 0x05
476	#define SD_RSP_TYPE_R4 0x05	476	#define SD_RSP_TYPE_R4 0x05
477	#define SD_RSP_TYPE_R5 0x01	477	#define SD_RSP_TYPE_R5 0x01
478	#define SD_RSP_TYPE_R6 0x01	478	#define SD_RSP_TYPE_R6 0x01
479	#define SD_RSP_TYPE_R7 0x01	479	#define SD_RSP_TYPE_R7 0x01
480		480
481	/* SD_CONFIGURE3 */	481	/* SD_CONFIGURE3 */
482	#define SD_RSP_80CLK_TIMEOUT_EN 0x01	482	#define SD_RSP_80CLK_TIMEOUT_EN 0x01
483		483
484	/* Card Transfer Reset Register */	484	/* Card Transfer Reset Register */
485	#define SPI_STOP 0x01	485	#define SPI_STOP 0x01
@@ -574,13 +574,13 @@
574		574
575	#define SRCTL 0xFC13	575	#define SRCTL 0xFC13
576		576
577	#define DCM_DRP_CTL 0xFC23	577	#define DCM_DRP_CTL 0xFC23
578	#define DCM_DRP_TRIG 0xFC24	578	#define DCM_DRP_TRIG 0xFC24
579	#define DCM_DRP_CFG 0xFC25	579	#define DCM_DRP_CFG 0xFC25
580	#define DCM_DRP_WR_DATA_L 0xFC26	580	#define DCM_DRP_WR_DATA_L 0xFC26
581	#define DCM_DRP_WR_DATA_H 0xFC27	581	#define DCM_DRP_WR_DATA_H 0xFC27
582	#define DCM_DRP_RD_DATA_L 0xFC28	582	#define DCM_DRP_RD_DATA_L 0xFC28
583	#define DCM_DRP_RD_DATA_H 0xFC29	583	#define DCM_DRP_RD_DATA_H 0xFC29
584	#define SD_VPCLK0_CTL 0xFC2A	584	#define SD_VPCLK0_CTL 0xFC2A
585	#define SD_VPCLK1_CTL 0xFC2B	585	#define SD_VPCLK1_CTL 0xFC2B
586	#define SD_DCMPS0_CTL 0xFC2C	586	#define SD_DCMPS0_CTL 0xFC2C