Merge 'Linux v3.0' into Litmus

Some notes:
* Litmus^RT scheduling class is the topmost scheduling class
  (above stop_sched_class).
* scheduler_ipi() function (e.g., in smp_reschedule_interrupt())
  may increase IPI latencies.
* Added path into schedule() to quickly re-evaluate scheduling
  decision without becoming preemptive again. This used to be
  a standard path before the removal of BKL.

Conflicts:
	Makefile
	arch/arm/kernel/calls.S
	arch/arm/kernel/smp.c
	arch/x86/include/asm/unistd_32.h
	arch/x86/kernel/smp.c
	arch/x86/kernel/syscall_table_32.S
	include/linux/hrtimer.h
	kernel/printk.c
	kernel/sched.c
	kernel/sched_fair.c

40 files changed, 4631 insertions, 447 deletions

diff --git a/include/linux/mfd/88pm860x.h b/include/linux/mfd/88pm860x.h
index bfd23bef7363..63b4fb8e3b6f 100644
--- a/include/linux/mfd/88pm860x.h
+++ b/include/linux/mfd/88pm860x.h
@@ -131,14 +131,16 @@ enum {
         PM8607_ID_LDO8,
         PM8607_ID_LDO9,
         PM8607_ID_LDO10,
+        PM8607_ID_LDO11,
         PM8607_ID_LDO12,
         PM8607_ID_LDO13,
         PM8607_ID_LDO14,
+        PM8607_ID_LDO15,
 
         PM8607_ID_RG_MAX,
 };
 
-#define PM8607_VERSION                  (0x40)  /* 8607 chip ID */
+/* 8607 chip ID is 0x40 or 0x50 */
 #define PM8607_VERSION_MASK             (0xF0)  /* 8607 chip ID mask */
 
 /* Interrupt Registers */
@@ -310,8 +312,6 @@ struct pm860x_chip {
 
 };
 
-#define PM8607_MAX_REGULATOR    PM8607_ID_RG_MAX        /* 3 Bucks, 13 LDOs */
-
 enum {
         GI2C_PORT = 0,
         PI2C_PORT,
@@ -330,6 +330,11 @@ struct pm860x_led_pdata {
         unsigned long   flags;
 };
 
+struct pm860x_rtc_pdata {
+        int             (*sync)(unsigned int ticks);
+        int             vrtc;
+};
+
 struct pm860x_touch_pdata {
         int             gpadc_prebias;
         int             slot_cycle;
@@ -349,25 +354,34 @@ struct pm860x_power_pdata {
 struct pm860x_platform_data {
         struct pm860x_backlight_pdata   *backlight;
         struct pm860x_led_pdata         *led;
+        struct pm860x_rtc_pdata         *rtc;
         struct pm860x_touch_pdata       *touch;
         struct pm860x_power_pdata       *power;
+        struct regulator_init_data      *regulator;
 
         unsigned short  companion_addr; /* I2C address of companion chip */
         int             i2c_port;       /* Controlled by GI2C or PI2C */
         int             irq_mode;       /* Clear interrupt by read/write(0/1) */
         int             irq_base;       /* IRQ base number of 88pm860x */
-        struct regulator_init_data *regulator[PM8607_MAX_REGULATOR];
+        int             num_leds;
+        int             num_backlights;
+        int             num_regulators;
 };
 
-extern char pm860x_backlight_name[][MFD_NAME_SIZE];
-extern char pm860x_led_name[][MFD_NAME_SIZE];
-
 extern int pm860x_reg_read(struct i2c_client *, int);
 extern int pm860x_reg_write(struct i2c_client *, int, unsigned char);
 extern int pm860x_bulk_read(struct i2c_client *, int, int, unsigned char *);
 extern int pm860x_bulk_write(struct i2c_client *, int, int, unsigned char *);
 extern int pm860x_set_bits(struct i2c_client *, int, unsigned char,
                            unsigned char);
+extern int pm860x_page_reg_read(struct i2c_client *, int);
+extern int pm860x_page_reg_write(struct i2c_client *, int, unsigned char);
+extern int pm860x_page_bulk_read(struct i2c_client *, int, int,
+                                 unsigned char *);
+extern int pm860x_page_bulk_write(struct i2c_client *, int, int,
+                                  unsigned char *);
+extern int pm860x_page_set_bits(struct i2c_client *, int, unsigned char,
+                                unsigned char);
 
 extern int pm860x_device_init(struct pm860x_chip *chip,
                               struct pm860x_platform_data *pdata) __devinit ;
diff --git a/include/linux/mfd/ab8500.h b/include/linux/mfd/ab8500.h
index f5cec4500f38..b31843075198 100644
--- a/include/linux/mfd/ab8500.h
+++ b/include/linux/mfd/ab8500.h
@@ -10,6 +10,29 @@
 #include <linux/device.h>
 
 /*
+ * AB8500 bank addresses
+ */
+#define AB8500_SYS_CTRL1_BLOCK  0x1
+#define AB8500_SYS_CTRL2_BLOCK  0x2
+#define AB8500_REGU_CTRL1       0x3
+#define AB8500_REGU_CTRL2       0x4
+#define AB8500_USB              0x5
+#define AB8500_TVOUT            0x6
+#define AB8500_DBI              0x7
+#define AB8500_ECI_AV_ACC       0x8
+#define AB8500_RESERVED         0x9
+#define AB8500_GPADC            0xA
+#define AB8500_CHARGER          0xB
+#define AB8500_GAS_GAUGE        0xC
+#define AB8500_AUDIO            0xD
+#define AB8500_INTERRUPT        0xE
+#define AB8500_RTC              0xF
+#define AB8500_MISC             0x10
+#define AB8500_DEBUG            0x12
+#define AB8500_PROD_TEST        0x13
+#define AB8500_OTP_EMUL         0x15
+
+/*
  * Interrupts
  */
 
@@ -51,40 +74,84 @@
 #define AB8500_INT_ACC_DETECT_21DB_F    37
 #define AB8500_INT_ACC_DETECT_21DB_R    38
 #define AB8500_INT_GP_SW_ADC_CONV_END   39
-#define AB8500_INT_BTEMP_LOW            72
-#define AB8500_INT_BTEMP_LOW_MEDIUM     73
-#define AB8500_INT_BTEMP_MEDIUM_HIGH    74
-#define AB8500_INT_BTEMP_HIGH           75
-#define AB8500_INT_USB_CHARGER_NOT_OK   81
-#define AB8500_INT_ID_WAKEUP_R          82
-#define AB8500_INT_ID_DET_R1R           84
-#define AB8500_INT_ID_DET_R2R           85
-#define AB8500_INT_ID_DET_R3R           86
-#define AB8500_INT_ID_DET_R4R           87
-#define AB8500_INT_ID_WAKEUP_F          88
-#define AB8500_INT_ID_DET_R1F           90
-#define AB8500_INT_ID_DET_R2F           91
-#define AB8500_INT_ID_DET_R3F           92
-#define AB8500_INT_ID_DET_R4F           93
-#define AB8500_INT_USB_CHG_DET_DONE     94
-#define AB8500_INT_USB_CH_TH_PROT_F     96
-#define AB8500_INT_USB_CH_TH_PROP_R     97
-#define AB8500_INT_MAIN_CH_TH_PROP_F    98
-#define AB8500_INT_MAIN_CH_TH_PROT_R    99
-#define AB8500_INT_USB_CHARGER_NOT_OKF  103
-
-#define AB8500_NR_IRQS                  104
-#define AB8500_NUM_IRQ_REGS             13
+#define AB8500_INT_ACC_DETECT_1DB_F     33
+#define AB8500_INT_ACC_DETECT_1DB_R     34
+#define AB8500_INT_ACC_DETECT_22DB_F    35
+#define AB8500_INT_ACC_DETECT_22DB_R    36
+#define AB8500_INT_ACC_DETECT_21DB_F    37
+#define AB8500_INT_ACC_DETECT_21DB_R    38
+#define AB8500_INT_GP_SW_ADC_CONV_END   39
+#define AB8500_INT_GPIO6R               40
+#define AB8500_INT_GPIO7R               41
+#define AB8500_INT_GPIO8R               42
+#define AB8500_INT_GPIO9R               43
+#define AB8500_INT_GPIO10R              44
+#define AB8500_INT_GPIO11R              45
+#define AB8500_INT_GPIO12R              46
+#define AB8500_INT_GPIO13R              47
+#define AB8500_INT_GPIO24R              48
+#define AB8500_INT_GPIO25R              49
+#define AB8500_INT_GPIO36R              50
+#define AB8500_INT_GPIO37R              51
+#define AB8500_INT_GPIO38R              52
+#define AB8500_INT_GPIO39R              53
+#define AB8500_INT_GPIO40R              54
+#define AB8500_INT_GPIO41R              55
+#define AB8500_INT_GPIO6F               56
+#define AB8500_INT_GPIO7F               57
+#define AB8500_INT_GPIO8F               58
+#define AB8500_INT_GPIO9F               59
+#define AB8500_INT_GPIO10F              60
+#define AB8500_INT_GPIO11F              61
+#define AB8500_INT_GPIO12F              62
+#define AB8500_INT_GPIO13F              63
+#define AB8500_INT_GPIO24F              64
+#define AB8500_INT_GPIO25F              65
+#define AB8500_INT_GPIO36F              66
+#define AB8500_INT_GPIO37F              67
+#define AB8500_INT_GPIO38F              68
+#define AB8500_INT_GPIO39F              69
+#define AB8500_INT_GPIO40F              70
+#define AB8500_INT_GPIO41F              71
+#define AB8500_INT_ADP_SOURCE_ERROR     72
+#define AB8500_INT_ADP_SINK_ERROR       73
+#define AB8500_INT_ADP_PROBE_PLUG       74
+#define AB8500_INT_ADP_PROBE_UNPLUG     75
+#define AB8500_INT_ADP_SENSE_OFF        76
+#define AB8500_INT_USB_PHY_POWER_ERR    78
+#define AB8500_INT_USB_LINK_STATUS      79
+#define AB8500_INT_BTEMP_LOW            80
+#define AB8500_INT_BTEMP_LOW_MEDIUM     81
+#define AB8500_INT_BTEMP_MEDIUM_HIGH    82
+#define AB8500_INT_BTEMP_HIGH           83
+#define AB8500_INT_USB_CHARGER_NOT_OK   89
+#define AB8500_INT_ID_WAKEUP_R          90
+#define AB8500_INT_ID_DET_R1R           92
+#define AB8500_INT_ID_DET_R2R           93
+#define AB8500_INT_ID_DET_R3R           94
+#define AB8500_INT_ID_DET_R4R           95
+#define AB8500_INT_ID_WAKEUP_F          96
+#define AB8500_INT_ID_DET_R1F           98
+#define AB8500_INT_ID_DET_R2F           99
+#define AB8500_INT_ID_DET_R3F           100
+#define AB8500_INT_ID_DET_R4F           101
+#define AB8500_INT_USB_CHG_DET_DONE     102
+#define AB8500_INT_USB_CH_TH_PROT_F     104
+#define AB8500_INT_USB_CH_TH_PROT_R    105
+#define AB8500_INT_MAIN_CH_TH_PROT_F   106
+#define AB8500_INT_MAIN_CH_TH_PROT_R    107
+#define AB8500_INT_USB_CHARGER_NOT_OKF  111
 
-#define AB8500_NUM_REGULATORS   15
+#define AB8500_NR_IRQS                  112
+#define AB8500_NUM_IRQ_REGS             14
 
 /**
  * struct ab8500 - ab8500 internal structure
  * @dev: parent device
  * @lock: read/write operations lock
  * @irq_lock: genirq bus lock
- * @revision: chip revision
  * @irq: irq line
+ * @chip_id: chip revision id
  * @write: register write
  * @read: register read
  * @rx_buf: rx buf for SPI
@@ -96,9 +163,10 @@ struct ab8500 {
         struct device   *dev;
         struct mutex    lock;
         struct mutex    irq_lock;
-        int             revision;
+
         int             irq_base;
         int             irq;
+        u8              chip_id;
 
         int (*write) (struct ab8500 *a8500, u16 addr, u8 data);
         int (*read) (struct ab8500 *a8500, u16 addr);
@@ -110,24 +178,29 @@ struct ab8500 {
         u8 oldmask[AB8500_NUM_IRQ_REGS];
 };
 
+struct regulator_reg_init;
 struct regulator_init_data;
+struct ab8500_gpio_platform_data;
 
 /**
  * struct ab8500_platform_data - AB8500 platform data
  * @irq_base: start of AB8500 IRQs, AB8500_NR_IRQS will be used
  * @init: board-specific initialization after detection of ab8500
+ * @num_regulator_reg_init: number of regulator init registers
+ * @regulator_reg_init: regulator init registers
+ * @num_regulator: number of regulators
  * @regulator: machine-specific constraints for regulators
  */
 struct ab8500_platform_data {
         int irq_base;
         void (*init) (struct ab8500 *);
-        struct regulator_init_data *regulator[AB8500_NUM_REGULATORS];
+        int num_regulator_reg_init;
+        struct ab8500_regulator_reg_init *regulator_reg_init;
+        int num_regulator;
+        struct regulator_init_data *regulator;
+        struct ab8500_gpio_platform_data *gpio;
 };
 
-extern int ab8500_write(struct ab8500 *a8500, u16 addr, u8 data);
-extern int ab8500_read(struct ab8500 *a8500, u16 addr);
-extern int ab8500_set_bits(struct ab8500 *a8500, u16 addr, u8 mask, u8 data);
-
 extern int __devinit ab8500_init(struct ab8500 *ab8500);
 extern int __devexit ab8500_exit(struct ab8500 *ab8500);
 
diff --git a/include/linux/mfd/ab8500/gpadc.h b/include/linux/mfd/ab8500/gpadc.h
new file mode 100644
index 000000000000..46b954011f16
--- /dev/null
+++ b/include/linux/mfd/ab8500/gpadc.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2010 ST-Ericsson SA
+ * Licensed under GPLv2.
+ *
+ * Author: Arun R Murthy <arun.murthy@stericsson.com>
+ * Author: Daniel Willerud <daniel.willerud@stericsson.com>
+ */
+
+#ifndef _AB8500_GPADC_H
+#define _AB8500_GPADC_H
+
+/* GPADC source: From datasheet(ADCSwSel[4:0] in GPADCCtrl2) */
+#define BAT_CTRL        0x01
+#define BTEMP_BALL      0x02
+#define MAIN_CHARGER_V  0x03
+#define ACC_DETECT1     0x04
+#define ACC_DETECT2     0x05
+#define ADC_AUX1        0x06
+#define ADC_AUX2        0x07
+#define MAIN_BAT_V      0x08
+#define VBUS_V          0x09
+#define MAIN_CHARGER_C  0x0A
+#define USB_CHARGER_C   0x0B
+#define BK_BAT_V        0x0C
+#define DIE_TEMP        0x0D
+
+struct ab8500_gpadc;
+
+struct ab8500_gpadc *ab8500_gpadc_get(char *name);
+int ab8500_gpadc_convert(struct ab8500_gpadc *gpadc, u8 input);
+
+#endif /* _AB8500_GPADC_H */
diff --git a/include/linux/mfd/ab8500/gpio.h b/include/linux/mfd/ab8500/gpio.h
new file mode 100644
index 000000000000..488a8c920a29
--- /dev/null
+++ b/include/linux/mfd/ab8500/gpio.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright ST-Ericsson 2010.
+ *
+ * Author: Bibek Basu <bibek.basu@stericsson.com>
+ * Licensed under GPLv2.
+ */
+
+#ifndef _AB8500_GPIO_H
+#define _AB8500_GPIO_H
+
+/*
+ * Platform data to register a block: only the initial gpio/irq number.
+ */
+
+struct ab8500_gpio_platform_data {
+        int gpio_base;
+        u32 irq_base;
+        u8  config_reg[7];
+};
+
+#endif /* _AB8500_GPIO_H */
diff --git a/include/linux/mfd/ab8500/sysctrl.h b/include/linux/mfd/ab8500/sysctrl.h
new file mode 100644
index 000000000000..10da0291f8f8
--- /dev/null
+++ b/include/linux/mfd/ab8500/sysctrl.h
@@ -0,0 +1,254 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> for ST Ericsson.
+ * License terms: GNU General Public License (GPL) version 2
+ */
+#ifndef __AB8500_SYSCTRL_H
+#define __AB8500_SYSCTRL_H
+
+#include <linux/bitops.h>
+
+#ifdef CONFIG_AB8500_CORE
+
+int ab8500_sysctrl_read(u16 reg, u8 *value);
+int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value);
+
+#else
+
+static inline int ab8500_sysctrl_read(u16 reg, u8 *value)
+{
+        return 0;
+}
+
+static inline int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value)
+{
+        return 0;
+}
+
+#endif /* CONFIG_AB8500_CORE */
+
+static inline int ab8500_sysctrl_set(u16 reg, u8 bits)
+{
+        return ab8500_sysctrl_write(reg, bits, bits);
+}
+
+static inline int ab8500_sysctrl_clear(u16 reg, u8 bits)
+{
+        return ab8500_sysctrl_write(reg, bits, 0);
+}
+
+/* Registers */
+#define AB8500_TURNONSTATUS             0x100
+#define AB8500_RESETSTATUS              0x101
+#define AB8500_PONKEY1PRESSSTATUS       0x102
+#define AB8500_SYSCLKREQSTATUS          0x142
+#define AB8500_STW4500CTRL1             0x180
+#define AB8500_STW4500CTRL2             0x181
+#define AB8500_STW4500CTRL3             0x200
+#define AB8500_MAINWDOGCTRL             0x201
+#define AB8500_MAINWDOGTIMER            0x202
+#define AB8500_LOWBAT                   0x203
+#define AB8500_BATTOK                   0x204
+#define AB8500_SYSCLKTIMER              0x205
+#define AB8500_SMPSCLKCTRL              0x206
+#define AB8500_SMPSCLKSEL1              0x207
+#define AB8500_SMPSCLKSEL2              0x208
+#define AB8500_SMPSCLKSEL3              0x209
+#define AB8500_SYSULPCLKCONF            0x20A
+#define AB8500_SYSULPCLKCTRL1           0x20B
+#define AB8500_SYSCLKCTRL               0x20C
+#define AB8500_SYSCLKREQ1VALID          0x20D
+#define AB8500_SYSTEMCTRLSUP            0x20F
+#define AB8500_SYSCLKREQ1RFCLKBUF       0x210
+#define AB8500_SYSCLKREQ2RFCLKBUF       0x211
+#define AB8500_SYSCLKREQ3RFCLKBUF       0x212
+#define AB8500_SYSCLKREQ4RFCLKBUF       0x213
+#define AB8500_SYSCLKREQ5RFCLKBUF       0x214
+#define AB8500_SYSCLKREQ6RFCLKBUF       0x215
+#define AB8500_SYSCLKREQ7RFCLKBUF       0x216
+#define AB8500_SYSCLKREQ8RFCLKBUF       0x217
+#define AB8500_DITHERCLKCTRL            0x220
+#define AB8500_SWATCTRL                 0x230
+#define AB8500_HIQCLKCTRL               0x232
+#define AB8500_VSIMSYSCLKCTRL           0x233
+
+/* Bits */
+#define AB8500_TURNONSTATUS_PORNVBAT BIT(0)
+#define AB8500_TURNONSTATUS_PONKEY1DBF BIT(1)
+#define AB8500_TURNONSTATUS_PONKEY2DBF BIT(2)
+#define AB8500_TURNONSTATUS_RTCALARM BIT(3)
+#define AB8500_TURNONSTATUS_MAINCHDET BIT(4)
+#define AB8500_TURNONSTATUS_VBUSDET BIT(5)
+#define AB8500_TURNONSTATUS_USBIDDETECT BIT(6)
+
+#define AB8500_RESETSTATUS_RESETN4500NSTATUS BIT(0)
+#define AB8500_RESETSTATUS_SWRESETN4500NSTATUS BIT(2)
+
+#define AB8500_PONKEY1PRESSSTATUS_PONKEY1PRESSTIME_MASK 0x7F
+#define AB8500_PONKEY1PRESSSTATUS_PONKEY1PRESSTIME_SHIFT 0
+
+#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ1STATUS BIT(0)
+#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ2STATUS BIT(1)
+#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ3STATUS BIT(2)
+#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ4STATUS BIT(3)
+#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ5STATUS BIT(4)
+#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ6STATUS BIT(5)
+#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ7STATUS BIT(6)
+#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ8STATUS BIT(7)
+
+#define AB8500_STW4500CTRL1_SWOFF BIT(0)
+#define AB8500_STW4500CTRL1_SWRESET4500N BIT(1)
+#define AB8500_STW4500CTRL1_THDB8500SWOFF BIT(2)
+
+#define AB8500_STW4500CTRL2_RESETNVAUX1VALID BIT(0)
+#define AB8500_STW4500CTRL2_RESETNVAUX2VALID BIT(1)
+#define AB8500_STW4500CTRL2_RESETNVAUX3VALID BIT(2)
+#define AB8500_STW4500CTRL2_RESETNVMODVALID BIT(3)
+#define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY1VALID BIT(4)
+#define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY2VALID BIT(5)
+#define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY3VALID BIT(6)
+#define AB8500_STW4500CTRL2_RESETNVSMPS1VALID BIT(7)
+
+#define AB8500_STW4500CTRL3_CLK32KOUT2DIS BIT(0)
+#define AB8500_STW4500CTRL3_RESETAUDN BIT(1)
+#define AB8500_STW4500CTRL3_RESETDENCN BIT(2)
+#define AB8500_STW4500CTRL3_THSDENA BIT(3)
+
+#define AB8500_MAINWDOGCTRL_MAINWDOGENA BIT(0)
+#define AB8500_MAINWDOGCTRL_MAINWDOGKICK BIT(1)
+#define AB8500_MAINWDOGCTRL_WDEXPTURNONVALID BIT(4)
+
+#define AB8500_MAINWDOGTIMER_MAINWDOGTIMER_MASK 0x7F
+#define AB8500_MAINWDOGTIMER_MAINWDOGTIMER_SHIFT 0
+
+#define AB8500_LOWBAT_LOWBATENA BIT(0)
+#define AB8500_LOWBAT_LOWBAT_MASK 0x7E
+#define AB8500_LOWBAT_LOWBAT_SHIFT 1
+
+#define AB8500_BATTOK_BATTOKSEL0THF_MASK 0x0F
+#define AB8500_BATTOK_BATTOKSEL0THF_SHIFT 0
+#define AB8500_BATTOK_BATTOKSEL1THF_MASK 0xF0
+#define AB8500_BATTOK_BATTOKSEL1THF_SHIFT 4
+
+#define AB8500_SYSCLKTIMER_SYSCLKTIMER_MASK 0x0F
+#define AB8500_SYSCLKTIMER_SYSCLKTIMER_SHIFT 0
+#define AB8500_SYSCLKTIMER_SYSCLKTIMERADJ_MASK 0xF0
+#define AB8500_SYSCLKTIMER_SYSCLKTIMERADJ_SHIFT 4
+
+#define AB8500_SMPSCLKCTRL_SMPSCLKINTSEL_MASK 0x03
+#define AB8500_SMPSCLKCTRL_SMPSCLKINTSEL_SHIFT 0
+#define AB8500_SMPSCLKCTRL_3M2CLKINTENA BIT(2)
+
+#define AB8500_SMPSCLKSEL1_VARMCLKSEL_MASK 0x07
+#define AB8500_SMPSCLKSEL1_VARMCLKSEL_SHIFT 0
+#define AB8500_SMPSCLKSEL1_VAPECLKSEL_MASK 0x38
+#define AB8500_SMPSCLKSEL1_VAPECLKSEL_SHIFT 3
+
+#define AB8500_SMPSCLKSEL2_VMODCLKSEL_MASK 0x07
+#define AB8500_SMPSCLKSEL2_VMODCLKSEL_SHIFT 0
+#define AB8500_SMPSCLKSEL2_VSMPS1CLKSEL_MASK 0x38
+#define AB8500_SMPSCLKSEL2_VSMPS1CLKSEL_SHIFT 3
+
+#define AB8500_SMPSCLKSEL3_VSMPS2CLKSEL_MASK 0x07
+#define AB8500_SMPSCLKSEL3_VSMPS2CLKSEL_SHIFT 0
+#define AB8500_SMPSCLKSEL3_VSMPS3CLKSEL_MASK 0x38
+#define AB8500_SMPSCLKSEL3_VSMPS3CLKSEL_SHIFT 3
+
+#define AB8500_SYSULPCLKCONF_ULPCLKCONF_MASK 0x03
+#define AB8500_SYSULPCLKCONF_ULPCLKCONF_SHIFT 0
+#define AB8500_SYSULPCLKCONF_CLK27MHZSTRE BIT(2)
+#define AB8500_SYSULPCLKCONF_TVOUTCLKDELN BIT(3)
+#define AB8500_SYSULPCLKCONF_TVOUTCLKINV BIT(4)
+#define AB8500_SYSULPCLKCONF_ULPCLKSTRE BIT(5)
+#define AB8500_SYSULPCLKCONF_CLK27MHZBUFENA BIT(6)
+#define AB8500_SYSULPCLKCONF_CLK27MHZPDENA BIT(7)
+
+#define AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_MASK 0x03
+#define AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_SHIFT 0
+#define AB8500_SYSULPCLKCTRL1_ULPCLKREQ BIT(2)
+#define AB8500_SYSULPCLKCTRL1_4500SYSCLKREQ BIT(3)
+#define AB8500_SYSULPCLKCTRL1_AUDIOCLKENA BIT(4)
+#define AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ BIT(5)
+#define AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ BIT(6)
+#define AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ BIT(7)
+
+#define AB8500_SYSCLKCTRL_TVOUTPLLENA BIT(0)
+#define AB8500_SYSCLKCTRL_TVOUTCLKENA BIT(1)
+#define AB8500_SYSCLKCTRL_USBCLKENA BIT(2)
+
+#define AB8500_SYSCLKREQ1VALID_SYSCLKREQ1VALID BIT(0)
+#define AB8500_SYSCLKREQ1VALID_ULPCLKREQ1VALID BIT(1)
+#define AB8500_SYSCLKREQ1VALID_USBSYSCLKREQ1VALID BIT(2)
+
+#define AB8500_SYSTEMCTRLSUP_EXTSUP12LPNCLKSEL_MASK 0x03
+#define AB8500_SYSTEMCTRLSUP_EXTSUP12LPNCLKSEL_SHIFT 0
+#define AB8500_SYSTEMCTRLSUP_EXTSUP3LPNCLKSEL_MASK 0x0C
+#define AB8500_SYSTEMCTRLSUP_EXTSUP3LPNCLKSEL_SHIFT 2
+#define AB8500_SYSTEMCTRLSUP_INTDB8500NOD BIT(4)
+
+#define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF2 BIT(2)
+#define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF3 BIT(3)
+#define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF4 BIT(4)
+
+#define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF2 BIT(2)
+#define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF3 BIT(3)
+#define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF4 BIT(4)
+
+#define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF2 BIT(2)
+#define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF3 BIT(3)
+#define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF4 BIT(4)
+
+#define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF2 BIT(2)
+#define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF3 BIT(3)
+#define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF4 BIT(4)
+
+#define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF2 BIT(2)
+#define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF3 BIT(3)
+#define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF4 BIT(4)
+
+#define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF2 BIT(2)
+#define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF3 BIT(3)
+#define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF4 BIT(4)
+
+#define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF2 BIT(2)
+#define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF3 BIT(3)
+#define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF4 BIT(4)
+
+#define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF2 BIT(2)
+#define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF3 BIT(3)
+#define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF4 BIT(4)
+
+#define AB8500_DITHERCLKCTRL_VARMDITHERENA BIT(0)
+#define AB8500_DITHERCLKCTRL_VSMPS3DITHERENA BIT(1)
+#define AB8500_DITHERCLKCTRL_VSMPS1DITHERENA BIT(2)
+#define AB8500_DITHERCLKCTRL_VSMPS2DITHERENA BIT(3)
+#define AB8500_DITHERCLKCTRL_VMODDITHERENA BIT(4)
+#define AB8500_DITHERCLKCTRL_VAPEDITHERENA BIT(5)
+#define AB8500_DITHERCLKCTRL_DITHERDEL_MASK 0xC0
+#define AB8500_DITHERCLKCTRL_DITHERDEL_SHIFT 6
+
+#define AB8500_SWATCTRL_UPDATERF BIT(0)
+#define AB8500_SWATCTRL_SWATENABLE BIT(1)
+#define AB8500_SWATCTRL_RFOFFTIMER_MASK 0x1C
+#define AB8500_SWATCTRL_RFOFFTIMER_SHIFT 2
+#define AB8500_SWATCTRL_SWATBIT5 BIT(6)
+
+#define AB8500_HIQCLKCTRL_SYSCLKREQ1HIQENAVALID BIT(0)
+#define AB8500_HIQCLKCTRL_SYSCLKREQ2HIQENAVALID BIT(1)
+#define AB8500_HIQCLKCTRL_SYSCLKREQ3HIQENAVALID BIT(2)
+#define AB8500_HIQCLKCTRL_SYSCLKREQ4HIQENAVALID BIT(3)
+#define AB8500_HIQCLKCTRL_SYSCLKREQ5HIQENAVALID BIT(4)
+#define AB8500_HIQCLKCTRL_SYSCLKREQ6HIQENAVALID BIT(5)
+#define AB8500_HIQCLKCTRL_SYSCLKREQ7HIQENAVALID BIT(6)
+#define AB8500_HIQCLKCTRL_SYSCLKREQ8HIQENAVALID BIT(7)
+
+#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ1VALID BIT(0)
+#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ2VALID BIT(1)
+#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ3VALID BIT(2)
+#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ4VALID BIT(3)
+#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ5VALID BIT(4)
+#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ6VALID BIT(5)
+#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ7VALID BIT(6)
+#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ8VALID BIT(7)
+
+#endif /* __AB8500_SYSCTRL_H */
diff --git a/include/linux/mfd/abx500.h b/include/linux/mfd/abx500.h
index 390726fcbcb1..896b5e47f16e 100644
--- a/include/linux/mfd/abx500.h
+++ b/include/linux/mfd/abx500.h
@@ -6,8 +6,7 @@
  *
  * ABX500 core access functions.
  * The abx500 interface is used for the Analog Baseband chip
- * ab3100, ab3550, ab5500 and possibly comming. It is not used for
- * ab4500 and ab8500 since they are another family of chip.
+ * ab3100, ab3550, ab5500, and ab8500.
  *
  * Author: Mattias Wallin <mattias.wallin@stericsson.com>
  * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
@@ -35,6 +34,13 @@
 #define AB5500_2_0      0x21
 #define AB5500_2_1      0x22
 
+/* AB8500 CIDs*/
+#define AB8500_CUTEARLY 0x00
+#define AB8500_CUT1P0   0x10
+#define AB8500_CUT1P1   0x11
+#define AB8500_CUT2P0   0x20
+#define AB8500_CUT3P0   0x30
+
 /*
  * AB3100, EVENTA1, A2 and A3 event register flags
  * these are catenated into a single 32-bit flag in the code
@@ -230,4 +236,5 @@ struct abx500_ops {
 };
 
 int abx500_register_ops(struct device *core_dev, struct abx500_ops *ops);
+void abx500_remove_ops(struct device *dev);
 #endif
diff --git a/include/linux/mfd/asic3.h b/include/linux/mfd/asic3.h
index de3c4ad19afb..ed793b77a1c5 100644
--- a/include/linux/mfd/asic3.h
+++ b/include/linux/mfd/asic3.h
@@ -16,6 +16,13 @@
 
 #include <linux/types.h>
 
+struct led_classdev;
+struct asic3_led {
+        const char      *name;
+        const char      *default_trigger;
+        struct led_classdev *cdev;
+};
+
 struct asic3_platform_data {
         u16 *gpio_config;
         unsigned int gpio_config_num;
@@ -23,6 +30,8 @@ struct asic3_platform_data {
         unsigned int irq_base;
 
         unsigned int gpio_base;
+
+        struct asic3_led *leds;
 };
 
 #define ASIC3_NUM_GPIO_BANKS    4
@@ -111,9 +120,9 @@ struct asic3_platform_data {
 #define ASIC3_GPIOA11_PWM0              ASIC3_CONFIG_GPIO(11, 1, 1, 0)
 #define ASIC3_GPIOA12_PWM1              ASIC3_CONFIG_GPIO(12, 1, 1, 0)
 #define ASIC3_GPIOA15_CONTROL_CX        ASIC3_CONFIG_GPIO(15, 1, 1, 0)
-#define ASIC3_GPIOC0_LED0               ASIC3_CONFIG_GPIO(32, 1, 1, 0)
-#define ASIC3_GPIOC1_LED1               ASIC3_CONFIG_GPIO(33, 1, 1, 0)
-#define ASIC3_GPIOC2_LED2               ASIC3_CONFIG_GPIO(34, 1, 1, 0)
+#define ASIC3_GPIOC0_LED0               ASIC3_CONFIG_GPIO(32, 1, 0, 0)
+#define ASIC3_GPIOC1_LED1               ASIC3_CONFIG_GPIO(33, 1, 0, 0)
+#define ASIC3_GPIOC2_LED2               ASIC3_CONFIG_GPIO(34, 1, 0, 0)
 #define ASIC3_GPIOC3_SPI_RXD            ASIC3_CONFIG_GPIO(35, 1, 0, 0)
 #define ASIC3_GPIOC4_CF_nCD             ASIC3_CONFIG_GPIO(36, 1, 0, 0)
 #define ASIC3_GPIOC4_SPI_TXD            ASIC3_CONFIG_GPIO(36, 1, 1, 0)
@@ -152,6 +161,7 @@ struct asic3_platform_data {
 #define PWM_TIMEBASE_VALUE(x)    ((x)&0xf)   /* Low 4 bits sets time base */
 #define PWM_TIMEBASE_ENABLE     (1 << 4)   /* Enable clock */
 
+#define ASIC3_NUM_LEDS                  3
 #define ASIC3_LED_0_Base                0x0700
 #define ASIC3_LED_1_Base                0x0800
 #define ASIC3_LED_2_Base                      0x0900
@@ -287,10 +297,17 @@ struct asic3_platform_data {
  *
  *****************************************************************************/
 #define ASIC3_SD_CONFIG_BASE    0x0400 /* Assumes 32 bit addressing */
+#define ASIC3_SD_CONFIG_SIZE    0x0200 /* Assumes 32 bit addressing */
 #define ASIC3_SD_CTRL_BASE      0x1000
 #define ASIC3_SDIO_CTRL_BASE    0x1200
 
 #define ASIC3_MAP_SIZE_32BIT    0x2000
 #define ASIC3_MAP_SIZE_16BIT    0x1000
 
+/* Functions needed by leds-asic3 */
+
+struct asic3;
+extern void asic3_write_register(struct asic3 *asic, unsigned int reg, u32 val);
+extern u32 asic3_read_register(struct asic3 *asic, unsigned int reg);
+
 #endif /* __ASIC3_H__ */
diff --git a/include/linux/mfd/core.h b/include/linux/mfd/core.h
index 11d740b8831d..4e76163dd862 100644
--- a/include/linux/mfd/core.h
+++ b/include/linux/mfd/core.h
@@ -25,29 +25,73 @@ struct mfd_cell {
         const char              *name;
         int                     id;
 
+        /* refcounting for multiple drivers to use a single cell */
+        atomic_t                *usage_count;
         int                     (*enable)(struct platform_device *dev);
         int                     (*disable)(struct platform_device *dev);
+
         int                     (*suspend)(struct platform_device *dev);
         int                     (*resume)(struct platform_device *dev);
 
-        /* driver-specific data for MFD-aware "cell" drivers */
-        void                    *driver_data;
-
-        /* platform_data can be used to either pass data to "generic"
-           driver or as a hook to mfd_cell for the "cell" drivers */
+        /* platform data passed to the sub devices drivers */
         void                    *platform_data;
-        size_t                  data_size;
+        size_t                  pdata_size;
 
         /*
-         * This resources can be specified relatievly to the parent device.
-         * For accessing device you should use resources from device
+         * These resources can be specified relative to the parent device.
+         * For accessing hardware you should use resources from the platform dev
          */
         int                     num_resources;
         const struct resource   *resources;
+
+        /* don't check for resource conflicts */
+        bool                    ignore_resource_conflicts;
+
+        /*
+         * Disable runtime PM callbacks for this subdevice - see
+         * pm_runtime_no_callbacks().
+         */
+        bool                    pm_runtime_no_callbacks;
 };
 
+/*
+ * Convenience functions for clients using shared cells.  Refcounting
+ * happens automatically, with the cell's enable/disable callbacks
+ * being called only when a device is first being enabled or no other
+ * clients are making use of it.
+ */
+extern int mfd_cell_enable(struct platform_device *pdev);
+extern int mfd_cell_disable(struct platform_device *pdev);
+
+/*
+ * "Clone" multiple platform devices for a single cell. This is to be used
+ * for devices that have multiple users of a cell.  For example, if an mfd
+ * driver wants the cell "foo" to be used by a GPIO driver, an MTD driver,
+ * and a platform driver, the following bit of code would be use after first
+ * calling mfd_add_devices():
+ *
+ * const char *fclones[] = { "foo-gpio", "foo-mtd" };
+ * err = mfd_clone_cells("foo", fclones, ARRAY_SIZE(fclones));
+ *
+ * Each driver (MTD, GPIO, and platform driver) would then register
+ * platform_drivers for "foo-mtd", "foo-gpio", and "foo", respectively.
+ * The cell's .enable/.disable hooks should be used to deal with hardware
+ * resource contention.
+ */
+extern int mfd_clone_cell(const char *cell, const char **clones,
+                size_t n_clones);
+
+/*
+ * Given a platform device that's been created by mfd_add_devices(), fetch
+ * the mfd_cell that created it.
+ */
+static inline const struct mfd_cell *mfd_get_cell(struct platform_device *pdev)
+{
+        return pdev->mfd_cell;
+}
+
 extern int mfd_add_devices(struct device *parent, int id,
-                           const struct mfd_cell *cells, int n_devs,
+                           struct mfd_cell *cells, int n_devs,
                            struct resource *mem_base,
                            int irq_base);
 
diff --git a/include/linux/mfd/db5500-prcmu.h b/include/linux/mfd/db5500-prcmu.h
new file mode 100644
index 000000000000..f0977986402c
--- /dev/null
+++ b/include/linux/mfd/db5500-prcmu.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License v2
+ *
+ * U5500 PRCMU API.
+ */
+#ifndef __MACH_PRCMU_U5500_H
+#define __MACH_PRCMU_U5500_H
+
+#ifdef CONFIG_UX500_SOC_DB5500
+
+void db5500_prcmu_early_init(void);
+
+int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
+int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
+
+#else /* !CONFIG_UX500_SOC_DB5500 */
+
+static inline void db5500_prcmu_early_init(void)
+{
+}
+
+static inline int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
+{
+        return -ENOSYS;
+}
+
+static inline int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
+{
+        return -ENOSYS;
+}
+
+#endif /* CONFIG_UX500_SOC_DB5500 */
+
+static inline int db5500_prcmu_config_abb_event_readout(u32 abb_events)
+{
+#ifdef CONFIG_MACH_U5500_SIMULATOR
+        return 0;
+#else
+        return -1;
+#endif
+}
+
+#endif /* __MACH_PRCMU_U5500_H */
diff --git a/include/linux/mfd/db8500-prcmu.h b/include/linux/mfd/db8500-prcmu.h
new file mode 100644
index 000000000000..917dbcab701c
--- /dev/null
+++ b/include/linux/mfd/db8500-prcmu.h
@@ -0,0 +1,978 @@
+/*
+ * Copyright (C) STMicroelectronics 2009
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License v2
+ * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
+ *
+ * PRCMU f/w APIs
+ */
+#ifndef __MFD_DB8500_PRCMU_H
+#define __MFD_DB8500_PRCMU_H
+
+#include <linux/interrupt.h>
+#include <linux/notifier.h>
+
+/* This portion previously known as <mach/prcmu-fw-defs_v1.h> */
+
+/**
+ * enum state - ON/OFF state definition
+ * @OFF: State is ON
+ * @ON: State is OFF
+ *
+ */
+enum state {
+        OFF = 0x0,
+        ON  = 0x1,
+};
+
+/**
+ * enum ret_state - general purpose On/Off/Retention states
+ *
+ */
+enum ret_state {
+        OFFST = 0,
+        ONST  = 1,
+        RETST = 2
+};
+
+/**
+ * enum clk_arm - ARM Cortex A9 clock schemes
+ * @A9_OFF:
+ * @A9_BOOT:
+ * @A9_OPPT1:
+ * @A9_OPPT2:
+ * @A9_EXTCLK:
+ */
+enum clk_arm {
+        A9_OFF,
+        A9_BOOT,
+        A9_OPPT1,
+        A9_OPPT2,
+        A9_EXTCLK
+};
+
+/**
+ * enum clk_gen - GEN#0/GEN#1 clock schemes
+ * @GEN_OFF:
+ * @GEN_BOOT:
+ * @GEN_OPPT1:
+ */
+enum clk_gen {
+        GEN_OFF,
+        GEN_BOOT,
+        GEN_OPPT1,
+};
+
+/* some information between arm and xp70 */
+
+/**
+ * enum romcode_write - Romcode message written by A9 AND read by XP70
+ * @RDY_2_DS: Value set when ApDeepSleep state can be executed by XP70
+ * @RDY_2_XP70_RST: Value set when 0x0F has been successfully polled by the
+ *                 romcode. The xp70 will go into self-reset
+ */
+enum romcode_write {
+        RDY_2_DS = 0x09,
+        RDY_2_XP70_RST = 0x10
+};
+
+/**
+ * enum romcode_read - Romcode message written by XP70 and read by A9
+ * @INIT: Init value when romcode field is not used
+ * @FS_2_DS: Value set when power state is going from ApExecute to
+ *          ApDeepSleep
+ * @END_DS: Value set when ApDeepSleep power state is reached coming from
+ *         ApExecute state
+ * @DS_TO_FS: Value set when power state is going from ApDeepSleep to
+ *           ApExecute
+ * @END_FS: Value set when ApExecute power state is reached coming from
+ *         ApDeepSleep state
+ * @SWR: Value set when power state is going to ApReset
+ * @END_SWR: Value set when the xp70 finished executing ApReset actions and
+ *          waits for romcode acknowledgment to go to self-reset
+ */
+enum romcode_read {
+        INIT = 0x00,
+        FS_2_DS = 0x0A,
+        END_DS = 0x0B,
+        DS_TO_FS = 0x0C,
+        END_FS = 0x0D,
+        SWR = 0x0E,
+        END_SWR = 0x0F
+};
+
+/**
+ * enum ap_pwrst - current power states defined in PRCMU firmware
+ * @NO_PWRST: Current power state init
+ * @AP_BOOT: Current power state is apBoot
+ * @AP_EXECUTE: Current power state is apExecute
+ * @AP_DEEP_SLEEP: Current power state is apDeepSleep
+ * @AP_SLEEP: Current power state is apSleep
+ * @AP_IDLE: Current power state is apIdle
+ * @AP_RESET: Current power state is apReset
+ */
+enum ap_pwrst {
+        NO_PWRST = 0x00,
+        AP_BOOT = 0x01,
+        AP_EXECUTE = 0x02,
+        AP_DEEP_SLEEP = 0x03,
+        AP_SLEEP = 0x04,
+        AP_IDLE = 0x05,
+        AP_RESET = 0x06
+};
+
+/**
+ * enum ap_pwrst_trans - Transition states defined in PRCMU firmware
+ * @NO_TRANSITION: No power state transition
+ * @APEXECUTE_TO_APSLEEP: Power state transition from ApExecute to ApSleep
+ * @APIDLE_TO_APSLEEP: Power state transition from ApIdle to ApSleep
+ * @APBOOT_TO_APEXECUTE: Power state transition from ApBoot to ApExecute
+ * @APEXECUTE_TO_APDEEPSLEEP: Power state transition from ApExecute to
+ *                          ApDeepSleep
+ * @APEXECUTE_TO_APIDLE: Power state transition from ApExecute to ApIdle
+ */
+enum ap_pwrst_trans {
+        NO_TRANSITION                   = 0x00,
+        APEXECUTE_TO_APSLEEP            = 0x01,
+        APIDLE_TO_APSLEEP               = 0x02, /* To be removed */
+        PRCMU_AP_SLEEP                  = 0x01,
+        APBOOT_TO_APEXECUTE             = 0x03,
+        APEXECUTE_TO_APDEEPSLEEP        = 0x04, /* To be removed */
+        PRCMU_AP_DEEP_SLEEP             = 0x04,
+        APEXECUTE_TO_APIDLE             = 0x05, /* To be removed */
+        PRCMU_AP_IDLE                   = 0x05,
+        PRCMU_AP_DEEP_IDLE              = 0x07,
+};
+
+/**
+ * enum ddr_pwrst - DDR power states definition
+ * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
+ * @DDR_PWR_STATE_ON:
+ * @DDR_PWR_STATE_OFFLOWLAT:
+ * @DDR_PWR_STATE_OFFHIGHLAT:
+ */
+enum ddr_pwrst {
+        DDR_PWR_STATE_UNCHANGED     = 0x00,
+        DDR_PWR_STATE_ON            = 0x01,
+        DDR_PWR_STATE_OFFLOWLAT     = 0x02,
+        DDR_PWR_STATE_OFFHIGHLAT    = 0x03
+};
+
+/**
+ * enum arm_opp - ARM OPP states definition
+ * @ARM_OPP_INIT:
+ * @ARM_NO_CHANGE: The ARM operating point is unchanged
+ * @ARM_100_OPP: The new ARM operating point is arm100opp
+ * @ARM_50_OPP: The new ARM operating point is arm50opp
+ * @ARM_MAX_OPP: Operating point is "max" (more than 100)
+ * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
+ * @ARM_EXTCLK: The new ARM operating point is armExtClk
+ */
+enum arm_opp {
+        ARM_OPP_INIT = 0x00,
+        ARM_NO_CHANGE = 0x01,
+        ARM_100_OPP = 0x02,
+        ARM_50_OPP = 0x03,
+        ARM_MAX_OPP = 0x04,
+        ARM_MAX_FREQ100OPP = 0x05,
+        ARM_EXTCLK = 0x07
+};
+
+/**
+ * enum ape_opp - APE OPP states definition
+ * @APE_OPP_INIT:
+ * @APE_NO_CHANGE: The APE operating point is unchanged
+ * @APE_100_OPP: The new APE operating point is ape100opp
+ * @APE_50_OPP: 50%
+ */
+enum ape_opp {
+        APE_OPP_INIT = 0x00,
+        APE_NO_CHANGE = 0x01,
+        APE_100_OPP = 0x02,
+        APE_50_OPP = 0x03
+};
+
+/**
+ * enum hw_acc_state - State definition for hardware accelerator
+ * @HW_NO_CHANGE: The hardware accelerator state must remain unchanged
+ * @HW_OFF: The hardware accelerator must be switched off
+ * @HW_OFF_RAMRET: The hardware accelerator must be switched off with its
+ *               internal RAM in retention
+ * @HW_ON: The hwa hardware accelerator hwa must be switched on
+ *
+ * NOTE! Deprecated, to be removed when all users switched over to use the
+ * regulator API.
+ */
+enum hw_acc_state {
+        HW_NO_CHANGE = 0x00,
+        HW_OFF = 0x01,
+        HW_OFF_RAMRET = 0x02,
+        HW_ON = 0x04
+};
+
+/**
+ * enum  mbox_2_arm_stat - Status messages definition for mbox_arm
+ * @BOOT_TO_EXECUTEOK: The apBoot to apExecute state transition has been
+ *                    completed
+ * @DEEPSLEEPOK: The apExecute to apDeepSleep state transition has been
+ *              completed
+ * @SLEEPOK: The apExecute to apSleep state transition has been completed
+ * @IDLEOK: The apExecute to apIdle state transition has been completed
+ * @SOFTRESETOK: The A9 watchdog/ SoftReset state has been completed
+ * @SOFTRESETGO : The A9 watchdog/SoftReset state is on going
+ * @BOOT_TO_EXECUTE: The apBoot to apExecute state transition is on going
+ * @EXECUTE_TO_DEEPSLEEP: The apExecute to apDeepSleep state transition is on
+ *                       going
+ * @DEEPSLEEP_TO_EXECUTE: The apDeepSleep to apExecute state transition is on
+ *                       going
+ * @DEEPSLEEP_TO_EXECUTEOK: The apDeepSleep to apExecute state transition has
+ *                         been completed
+ * @EXECUTE_TO_SLEEP: The apExecute to apSleep state transition is on going
+ * @SLEEP_TO_EXECUTE: The apSleep to apExecute state transition is on going
+ * @SLEEP_TO_EXECUTEOK: The apSleep to apExecute state transition has been
+ *                     completed
+ * @EXECUTE_TO_IDLE: The apExecute to apIdle state transition is on going
+ * @IDLE_TO_EXECUTE: The apIdle to apExecute state transition is on going
+ * @IDLE_TO_EXECUTEOK: The apIdle to apExecute state transition has been
+ *                    completed
+ * @INIT_STATUS: Status init
+ */
+enum ap_pwrsttr_status {
+        BOOT_TO_EXECUTEOK = 0xFF,
+        DEEPSLEEPOK = 0xFE,
+        SLEEPOK = 0xFD,
+        IDLEOK = 0xFC,
+        SOFTRESETOK = 0xFB,
+        SOFTRESETGO = 0xFA,
+        BOOT_TO_EXECUTE = 0xF9,
+        EXECUTE_TO_DEEPSLEEP = 0xF8,
+        DEEPSLEEP_TO_EXECUTE = 0xF7,
+        DEEPSLEEP_TO_EXECUTEOK = 0xF6,
+        EXECUTE_TO_SLEEP = 0xF5,
+        SLEEP_TO_EXECUTE = 0xF4,
+        SLEEP_TO_EXECUTEOK = 0xF3,
+        EXECUTE_TO_IDLE = 0xF2,
+        IDLE_TO_EXECUTE = 0xF1,
+        IDLE_TO_EXECUTEOK = 0xF0,
+        RDYTODS_RETURNTOEXE    = 0xEF,
+        NORDYTODS_RETURNTOEXE  = 0xEE,
+        EXETOSLEEP_RETURNTOEXE = 0xED,
+        EXETOIDLE_RETURNTOEXE  = 0xEC,
+        INIT_STATUS = 0xEB,
+
+        /*error messages */
+        INITERROR                     = 0x00,
+        PLLARMLOCKP_ER                = 0x01,
+        PLLDDRLOCKP_ER                = 0x02,
+        PLLSOCLOCKP_ER                = 0x03,
+        PLLSOCK1LOCKP_ER              = 0x04,
+        ARMWFI_ER                     = 0x05,
+        SYSCLKOK_ER                   = 0x06,
+        I2C_NACK_DATA_ER              = 0x07,
+        BOOT_ER                       = 0x08,
+        I2C_STATUS_ALWAYS_1           = 0x0A,
+        I2C_NACK_REG_ADDR_ER          = 0x0B,
+        I2C_NACK_DATA0123_ER          = 0x1B,
+        I2C_NACK_ADDR_ER              = 0x1F,
+        CURAPPWRSTISNOT_BOOT          = 0x20,
+        CURAPPWRSTISNOT_EXECUTE       = 0x21,
+        CURAPPWRSTISNOT_SLEEPMODE     = 0x22,
+        CURAPPWRSTISNOT_CORRECTFORIT10 = 0x23,
+        FIFO4500WUISNOT_WUPEVENT      = 0x24,
+        PLL32KLOCKP_ER                = 0x29,
+        DDRDEEPSLEEPOK_ER             = 0x2A,
+        ROMCODEREADY_ER               = 0x50,
+        WUPBEFOREDS                   = 0x51,
+        DDRCONFIG_ER                  = 0x52,
+        WUPBEFORESLEEP                = 0x53,
+        WUPBEFOREIDLE                 = 0x54
+};  /* earlier called as  mbox_2_arm_stat */
+
+/**
+ * enum dvfs_stat - DVFS status messages definition
+ * @DVFS_GO: A state transition DVFS is on going
+ * @DVFS_ARM100OPPOK: The state transition DVFS has been completed for 100OPP
+ * @DVFS_ARM50OPPOK: The state transition DVFS has been completed for 50OPP
+ * @DVFS_ARMEXTCLKOK: The state transition DVFS has been completed for EXTCLK
+ * @DVFS_NOCHGTCLKOK: The state transition DVFS has been completed for
+ *                   NOCHGCLK
+ * @DVFS_INITSTATUS: Value init
+ */
+enum dvfs_stat {
+        DVFS_GO = 0xFF,
+        DVFS_ARM100OPPOK = 0xFE,
+        DVFS_ARM50OPPOK = 0xFD,
+        DVFS_ARMEXTCLKOK = 0xFC,
+        DVFS_NOCHGTCLKOK = 0xFB,
+        DVFS_INITSTATUS = 0x00
+};
+
+/**
+ * enum sva_mmdsp_stat - SVA MMDSP status messages
+ * @SVA_MMDSP_GO: SVAMMDSP interrupt has happened
+ * @SVA_MMDSP_INIT: Status init
+ */
+enum sva_mmdsp_stat {
+        SVA_MMDSP_GO = 0xFF,
+        SVA_MMDSP_INIT = 0x00
+};
+
+/**
+ * enum sia_mmdsp_stat - SIA MMDSP status messages
+ * @SIA_MMDSP_GO: SIAMMDSP interrupt has happened
+ * @SIA_MMDSP_INIT: Status init
+ */
+enum sia_mmdsp_stat {
+        SIA_MMDSP_GO = 0xFF,
+        SIA_MMDSP_INIT = 0x00
+};
+
+/**
+ * enum  mbox_to_arm_err - Error messages definition
+ * @INIT_ERR: Init value
+ * @PLLARMLOCKP_ERR: PLLARM has not been correctly locked in given time
+ * @PLLDDRLOCKP_ERR: PLLDDR has not been correctly locked in the given time
+ * @PLLSOC0LOCKP_ERR: PLLSOC0 has not been correctly locked in the given time
+ * @PLLSOC1LOCKP_ERR: PLLSOC1 has not been correctly locked in the given time
+ * @ARMWFI_ERR: The ARM WFI has not been correctly executed in the given time
+ * @SYSCLKOK_ERR: The SYSCLK is not available in the given time
+ * @BOOT_ERR: Romcode has not validated the XP70 self reset in the given time
+ * @ROMCODESAVECONTEXT: The Romcode didn.t correctly save it secure context
+ * @VARMHIGHSPEEDVALTO_ERR: The ARM high speed supply value transfered
+ *          through I2C has not been correctly executed in the given time
+ * @VARMHIGHSPEEDACCESS_ERR: The command value of VarmHighSpeedVal transfered
+ *             through I2C has not been correctly executed in the given time
+ * @VARMLOWSPEEDVALTO_ERR:The ARM low speed supply value transfered through
+ *                     I2C has not been correctly executed in the given time
+ * @VARMLOWSPEEDACCESS_ERR: The command value of VarmLowSpeedVal transfered
+ *             through I2C has not been correctly executed in the given time
+ * @VARMRETENTIONVALTO_ERR: The ARM retention supply value transfered through
+ *                     I2C has not been correctly executed in the given time
+ * @VARMRETENTIONACCESS_ERR: The command value of VarmRetentionVal transfered
+ *             through I2C has not been correctly executed in the given time
+ * @VAPEHIGHSPEEDVALTO_ERR: The APE highspeed supply value transfered through
+ *                     I2C has not been correctly executed in the given time
+ * @VSAFEHPVALTO_ERR: The SAFE high power supply value transfered through I2C
+ *                         has not been correctly executed in the given time
+ * @VMODSEL1VALTO_ERR: The MODEM sel1 supply value transfered through I2C has
+ *                             not been correctly executed in the given time
+ * @VMODSEL2VALTO_ERR: The MODEM sel2 supply value transfered through I2C has
+ *                             not been correctly executed in the given time
+ * @VARMOFFACCESS_ERR: The command value of Varm ON/OFF transfered through
+ *                     I2C has not been correctly executed in the given time
+ * @VAPEOFFACCESS_ERR: The command value of Vape ON/OFF transfered through
+ *                     I2C has not been correctly executed in the given time
+ * @VARMRETACCES_ERR: The command value of Varm retention ON/OFF transfered
+ *             through I2C has not been correctly executed in the given time
+ * @CURAPPWRSTISNOTBOOT:Generated when Arm want to do power state transition
+ *             ApBoot to ApExecute but the power current state is not Apboot
+ * @CURAPPWRSTISNOTEXECUTE: Generated when Arm want to do power state
+ *              transition from ApExecute to others power state but the
+ *              power current state is not ApExecute
+ * @CURAPPWRSTISNOTSLEEPMODE: Generated when wake up events are transmitted
+ *             but the power current state is not ApDeepSleep/ApSleep/ApIdle
+ * @CURAPPWRSTISNOTCORRECTDBG:  Generated when wake up events are transmitted
+ *              but the power current state is not correct
+ * @ARMREGU1VALTO_ERR:The ArmRegu1 value transferred through I2C has not
+ *                    been correctly executed in the given time
+ * @ARMREGU2VALTO_ERR: The ArmRegu2 value transferred through I2C has not
+ *                    been correctly executed in the given time
+ * @VAPEREGUVALTO_ERR: The VApeRegu value transfered through I2C has not
+ *                    been correctly executed in the given time
+ * @VSMPS3REGUVALTO_ERR: The VSmps3Regu value transfered through I2C has not
+ *                      been correctly executed in the given time
+ * @VMODREGUVALTO_ERR: The VModemRegu value transfered through I2C has not
+ *                    been correctly executed in the given time
+ */
+enum mbox_to_arm_err {
+        INIT_ERR = 0x00,
+        PLLARMLOCKP_ERR = 0x01,
+        PLLDDRLOCKP_ERR = 0x02,
+        PLLSOC0LOCKP_ERR = 0x03,
+        PLLSOC1LOCKP_ERR = 0x04,
+        ARMWFI_ERR = 0x05,
+        SYSCLKOK_ERR = 0x06,
+        BOOT_ERR = 0x07,
+        ROMCODESAVECONTEXT = 0x08,
+        VARMHIGHSPEEDVALTO_ERR = 0x10,
+        VARMHIGHSPEEDACCESS_ERR = 0x11,
+        VARMLOWSPEEDVALTO_ERR = 0x12,
+        VARMLOWSPEEDACCESS_ERR = 0x13,
+        VARMRETENTIONVALTO_ERR = 0x14,
+        VARMRETENTIONACCESS_ERR = 0x15,
+        VAPEHIGHSPEEDVALTO_ERR = 0x16,
+        VSAFEHPVALTO_ERR = 0x17,
+        VMODSEL1VALTO_ERR = 0x18,
+        VMODSEL2VALTO_ERR = 0x19,
+        VARMOFFACCESS_ERR = 0x1A,
+        VAPEOFFACCESS_ERR = 0x1B,
+        VARMRETACCES_ERR = 0x1C,
+        CURAPPWRSTISNOTBOOT = 0x20,
+        CURAPPWRSTISNOTEXECUTE = 0x21,
+        CURAPPWRSTISNOTSLEEPMODE = 0x22,
+        CURAPPWRSTISNOTCORRECTDBG = 0x23,
+        ARMREGU1VALTO_ERR = 0x24,
+        ARMREGU2VALTO_ERR = 0x25,
+        VAPEREGUVALTO_ERR = 0x26,
+        VSMPS3REGUVALTO_ERR = 0x27,
+        VMODREGUVALTO_ERR = 0x28
+};
+
+enum hw_acc {
+        SVAMMDSP = 0,
+        SVAPIPE = 1,
+        SIAMMDSP = 2,
+        SIAPIPE = 3,
+        SGA = 4,
+        B2R2MCDE = 5,
+        ESRAM12 = 6,
+        ESRAM34 = 7,
+};
+
+enum cs_pwrmgt {
+        PWRDNCS0  = 0,
+        WKUPCS0   = 1,
+        PWRDNCS1  = 2,
+        WKUPCS1   = 3
+};
+
+/* Defs related to autonomous power management */
+
+/**
+ * enum sia_sva_pwr_policy - Power policy
+ * @NO_CHGT:    No change
+ * @DSPOFF_HWPOFF:
+ * @DSPOFFRAMRET_HWPOFF:
+ * @DSPCLKOFF_HWPOFF:
+ * @DSPCLKOFF_HWPCLKOFF:
+ *
+ */
+enum sia_sva_pwr_policy {
+        NO_CHGT                 = 0x0,
+        DSPOFF_HWPOFF           = 0x1,
+        DSPOFFRAMRET_HWPOFF     = 0x2,
+        DSPCLKOFF_HWPOFF        = 0x3,
+        DSPCLKOFF_HWPCLKOFF     = 0x4,
+};
+
+/**
+ * enum auto_enable - Auto Power enable
+ * @AUTO_OFF:
+ * @AUTO_ON:
+ *
+ */
+enum auto_enable {
+        AUTO_OFF        = 0x0,
+        AUTO_ON         = 0x1,
+};
+
+/* End of file previously known as prcmu-fw-defs_v1.h */
+
+/* PRCMU Wakeup defines */
+enum prcmu_wakeup_index {
+        PRCMU_WAKEUP_INDEX_RTC,
+        PRCMU_WAKEUP_INDEX_RTT0,
+        PRCMU_WAKEUP_INDEX_RTT1,
+        PRCMU_WAKEUP_INDEX_HSI0,
+        PRCMU_WAKEUP_INDEX_HSI1,
+        PRCMU_WAKEUP_INDEX_USB,
+        PRCMU_WAKEUP_INDEX_ABB,
+        PRCMU_WAKEUP_INDEX_ABB_FIFO,
+        PRCMU_WAKEUP_INDEX_ARM,
+        NUM_PRCMU_WAKEUP_INDICES
+};
+#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
+
+/* PRCMU QoS APE OPP class */
+#define PRCMU_QOS_APE_OPP 1
+#define PRCMU_QOS_DDR_OPP 2
+#define PRCMU_QOS_DEFAULT_VALUE -1
+
+/**
+ * enum hw_acc_dev - enum for hw accelerators
+ * @HW_ACC_SVAMMDSP: for SVAMMDSP
+ * @HW_ACC_SVAPIPE:  for SVAPIPE
+ * @HW_ACC_SIAMMDSP: for SIAMMDSP
+ * @HW_ACC_SIAPIPE: for SIAPIPE
+ * @HW_ACC_SGA: for SGA
+ * @HW_ACC_B2R2: for B2R2
+ * @HW_ACC_MCDE: for MCDE
+ * @HW_ACC_ESRAM1: for ESRAM1
+ * @HW_ACC_ESRAM2: for ESRAM2
+ * @HW_ACC_ESRAM3: for ESRAM3
+ * @HW_ACC_ESRAM4: for ESRAM4
+ * @NUM_HW_ACC: number of hardware accelerators
+ *
+ * Different hw accelerators which can be turned ON/
+ * OFF or put into retention (MMDSPs and ESRAMs).
+ * Used with EPOD API.
+ *
+ * NOTE! Deprecated, to be removed when all users switched over to use the
+ * regulator API.
+ */
+enum hw_acc_dev {
+        HW_ACC_SVAMMDSP,
+        HW_ACC_SVAPIPE,
+        HW_ACC_SIAMMDSP,
+        HW_ACC_SIAPIPE,
+        HW_ACC_SGA,
+        HW_ACC_B2R2,
+        HW_ACC_MCDE,
+        HW_ACC_ESRAM1,
+        HW_ACC_ESRAM2,
+        HW_ACC_ESRAM3,
+        HW_ACC_ESRAM4,
+        NUM_HW_ACC
+};
+
+/*
+ * Ids for all EPODs (power domains)
+ * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
+ * - EPOD_ID_SVAPIPE: power domain for SVA pipe
+ * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
+ * - EPOD_ID_SIAPIPE: power domain for SIA pipe
+ * - EPOD_ID_SGA: power domain for SGA
+ * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
+ * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
+ * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
+ * - NUM_EPOD_ID: number of power domains
+ */
+#define EPOD_ID_SVAMMDSP        0
+#define EPOD_ID_SVAPIPE         1
+#define EPOD_ID_SIAMMDSP        2
+#define EPOD_ID_SIAPIPE         3
+#define EPOD_ID_SGA             4
+#define EPOD_ID_B2R2_MCDE       5
+#define EPOD_ID_ESRAM12         6
+#define EPOD_ID_ESRAM34         7
+#define NUM_EPOD_ID             8
+
+/*
+ * state definition for EPOD (power domain)
+ * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
+ * - EPOD_STATE_OFF: The EPOD is switched off
+ * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
+ *                         retention
+ * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
+ * - EPOD_STATE_ON: Same as above, but with clock enabled
+ */
+#define EPOD_STATE_NO_CHANGE    0x00
+#define EPOD_STATE_OFF          0x01
+#define EPOD_STATE_RAMRET       0x02
+#define EPOD_STATE_ON_CLK_OFF   0x03
+#define EPOD_STATE_ON           0x04
+
+/*
+ * CLKOUT sources
+ */
+#define PRCMU_CLKSRC_CLK38M             0x00
+#define PRCMU_CLKSRC_ACLK               0x01
+#define PRCMU_CLKSRC_SYSCLK             0x02
+#define PRCMU_CLKSRC_LCDCLK             0x03
+#define PRCMU_CLKSRC_SDMMCCLK           0x04
+#define PRCMU_CLKSRC_TVCLK              0x05
+#define PRCMU_CLKSRC_TIMCLK             0x06
+#define PRCMU_CLKSRC_CLK009             0x07
+/* These are only valid for CLKOUT1: */
+#define PRCMU_CLKSRC_SIAMMDSPCLK        0x40
+#define PRCMU_CLKSRC_I2CCLK             0x41
+#define PRCMU_CLKSRC_MSP02CLK           0x42
+#define PRCMU_CLKSRC_ARMPLL_OBSCLK      0x43
+#define PRCMU_CLKSRC_HSIRXCLK           0x44
+#define PRCMU_CLKSRC_HSITXCLK           0x45
+#define PRCMU_CLKSRC_ARMCLKFIX          0x46
+#define PRCMU_CLKSRC_HDMICLK            0x47
+
+/*
+ * Definitions for autonomous power management configuration.
+ */
+
+#define PRCMU_AUTO_PM_OFF 0
+#define PRCMU_AUTO_PM_ON 1
+
+#define PRCMU_AUTO_PM_POWER_ON_HSEM BIT(0)
+#define PRCMU_AUTO_PM_POWER_ON_ABB_FIFO_IT BIT(1)
+
+enum prcmu_auto_pm_policy {
+        PRCMU_AUTO_PM_POLICY_NO_CHANGE,
+        PRCMU_AUTO_PM_POLICY_DSP_OFF_HWP_OFF,
+        PRCMU_AUTO_PM_POLICY_DSP_OFF_RAMRET_HWP_OFF,
+        PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_OFF,
+        PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_CLK_OFF,
+};
+
+/**
+ * struct prcmu_auto_pm_config - Autonomous power management configuration.
+ * @sia_auto_pm_enable: SIA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON})
+ * @sia_power_on:       SIA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask)
+ * @sia_policy:         SIA power policy. (enum prcmu_auto_pm_policy)
+ * @sva_auto_pm_enable: SVA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON})
+ * @sva_power_on:       SVA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask)
+ * @sva_policy:         SVA power policy. (enum prcmu_auto_pm_policy)
+ */
+struct prcmu_auto_pm_config {
+        u8 sia_auto_pm_enable;
+        u8 sia_power_on;
+        u8 sia_policy;
+        u8 sva_auto_pm_enable;
+        u8 sva_power_on;
+        u8 sva_policy;
+};
+
+/**
+ * enum ddr_opp - DDR OPP states definition
+ * @DDR_100_OPP: The new DDR operating point is ddr100opp
+ * @DDR_50_OPP: The new DDR operating point is ddr50opp
+ * @DDR_25_OPP: The new DDR operating point is ddr25opp
+ */
+enum ddr_opp {
+        DDR_100_OPP = 0x00,
+        DDR_50_OPP = 0x01,
+        DDR_25_OPP = 0x02,
+};
+
+/*
+ * Clock identifiers.
+ */
+enum prcmu_clock {
+        PRCMU_SGACLK,
+        PRCMU_UARTCLK,
+        PRCMU_MSP02CLK,
+        PRCMU_MSP1CLK,
+        PRCMU_I2CCLK,
+        PRCMU_SDMMCCLK,
+        PRCMU_SLIMCLK,
+        PRCMU_PER1CLK,
+        PRCMU_PER2CLK,
+        PRCMU_PER3CLK,
+        PRCMU_PER5CLK,
+        PRCMU_PER6CLK,
+        PRCMU_PER7CLK,
+        PRCMU_LCDCLK,
+        PRCMU_BMLCLK,
+        PRCMU_HSITXCLK,
+        PRCMU_HSIRXCLK,
+        PRCMU_HDMICLK,
+        PRCMU_APEATCLK,
+        PRCMU_APETRACECLK,
+        PRCMU_MCDECLK,
+        PRCMU_IPI2CCLK,
+        PRCMU_DSIALTCLK,
+        PRCMU_DMACLK,
+        PRCMU_B2R2CLK,
+        PRCMU_TVCLK,
+        PRCMU_SSPCLK,
+        PRCMU_RNGCLK,
+        PRCMU_UICCCLK,
+        PRCMU_NUM_REG_CLOCKS,
+        PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
+        PRCMU_TIMCLK,
+};
+
+/*
+ * Definitions for controlling ESRAM0 in deep sleep.
+ */
+#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
+#define ESRAM0_DEEP_SLEEP_STATE_RET 2
+
+#ifdef CONFIG_MFD_DB8500_PRCMU
+void __init prcmu_early_init(void);
+int prcmu_set_display_clocks(void);
+int prcmu_disable_dsipll(void);
+int prcmu_enable_dsipll(void);
+#else
+static inline void __init prcmu_early_init(void) {}
+#endif
+
+#ifdef CONFIG_MFD_DB8500_PRCMU
+
+int prcmu_set_rc_a2p(enum romcode_write);
+enum romcode_read prcmu_get_rc_p2a(void);
+enum ap_pwrst prcmu_get_xp70_current_state(void);
+int prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
+
+void prcmu_enable_wakeups(u32 wakeups);
+static inline void prcmu_disable_wakeups(void)
+{
+        prcmu_enable_wakeups(0);
+}
+
+void prcmu_config_abb_event_readout(u32 abb_events);
+void prcmu_get_abb_event_buffer(void __iomem **buf);
+int prcmu_set_arm_opp(u8 opp);
+int prcmu_get_arm_opp(void);
+bool prcmu_has_arm_maxopp(void);
+bool prcmu_is_u8400(void);
+int prcmu_set_ape_opp(u8 opp);
+int prcmu_get_ape_opp(void);
+int prcmu_request_ape_opp_100_voltage(bool enable);
+int prcmu_release_usb_wakeup_state(void);
+int prcmu_set_ddr_opp(u8 opp);
+int prcmu_get_ddr_opp(void);
+unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
+void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
+/* NOTE! Use regulator framework instead */
+int prcmu_set_hwacc(u16 hw_acc_dev, u8 state);
+int prcmu_set_epod(u16 epod_id, u8 epod_state);
+void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
+        struct prcmu_auto_pm_config *idle);
+bool prcmu_is_auto_pm_enabled(void);
+
+int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
+int prcmu_request_clock(u8 clock, bool enable);
+int prcmu_set_clock_divider(u8 clock, u8 divider);
+int prcmu_config_esram0_deep_sleep(u8 state);
+int prcmu_config_hotdog(u8 threshold);
+int prcmu_config_hotmon(u8 low, u8 high);
+int prcmu_start_temp_sense(u16 cycles32k);
+int prcmu_stop_temp_sense(void);
+int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
+int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
+
+void prcmu_ac_wake_req(void);
+void prcmu_ac_sleep_req(void);
+void prcmu_system_reset(u16 reset_code);
+void prcmu_modem_reset(void);
+bool prcmu_is_ac_wake_requested(void);
+void prcmu_enable_spi2(void);
+void prcmu_disable_spi2(void);
+
+#else /* !CONFIG_MFD_DB8500_PRCMU */
+
+static inline int prcmu_set_rc_a2p(enum romcode_write code)
+{
+        return 0;
+}
+
+static inline enum romcode_read prcmu_get_rc_p2a(void)
+{
+        return INIT;
+}
+
+static inline enum ap_pwrst prcmu_get_xp70_current_state(void)
+{
+        return AP_EXECUTE;
+}
+
+static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
+        bool keep_ap_pll)
+{
+        return 0;
+}
+
+static inline void prcmu_enable_wakeups(u32 wakeups) {}
+
+static inline void prcmu_disable_wakeups(void) {}
+
+static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
+
+static inline int prcmu_set_arm_opp(u8 opp)
+{
+        return 0;
+}
+
+static inline int prcmu_get_arm_opp(void)
+{
+        return ARM_100_OPP;
+}
+
+static bool prcmu_has_arm_maxopp(void)
+{
+        return false;
+}
+
+static bool prcmu_is_u8400(void)
+{
+        return false;
+}
+
+static inline int prcmu_set_ape_opp(u8 opp)
+{
+        return 0;
+}
+
+static inline int prcmu_get_ape_opp(void)
+{
+        return APE_100_OPP;
+}
+
+static inline int prcmu_request_ape_opp_100_voltage(bool enable)
+{
+        return 0;
+}
+
+static inline int prcmu_release_usb_wakeup_state(void)
+{
+        return 0;
+}
+
+static inline int prcmu_set_ddr_opp(u8 opp)
+{
+        return 0;
+}
+
+static inline int prcmu_get_ddr_opp(void)
+{
+        return DDR_100_OPP;
+}
+
+static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
+{
+        return 0;
+}
+
+static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}
+
+static inline int prcmu_set_hwacc(u16 hw_acc_dev, u8 state)
+{
+        return 0;
+}
+
+static inline void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
+        struct prcmu_auto_pm_config *idle)
+{
+}
+
+static inline bool prcmu_is_auto_pm_enabled(void)
+{
+        return false;
+}
+
+static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
+{
+        return 0;
+}
+
+static inline int prcmu_request_clock(u8 clock, bool enable)
+{
+        return 0;
+}
+
+static inline int prcmu_set_clock_divider(u8 clock, u8 divider)
+{
+        return 0;
+}
+
+int prcmu_config_esram0_deep_sleep(u8 state)
+{
+        return 0;
+}
+
+static inline int prcmu_config_hotdog(u8 threshold)
+{
+        return 0;
+}
+
+static inline int prcmu_config_hotmon(u8 low, u8 high)
+{
+        return 0;
+}
+
+static inline int prcmu_start_temp_sense(u16 cycles32k)
+{
+        return 0;
+}
+
+static inline int prcmu_stop_temp_sense(void)
+{
+        return 0;
+}
+
+static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
+{
+        return -ENOSYS;
+}
+
+static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
+{
+        return -ENOSYS;
+}
+
+static inline void prcmu_ac_wake_req(void) {}
+
+static inline void prcmu_ac_sleep_req(void) {}
+
+static inline void prcmu_system_reset(u16 reset_code) {}
+
+static inline void prcmu_modem_reset(void) {}
+
+static inline bool prcmu_is_ac_wake_requested(void)
+{
+        return false;
+}
+
+#ifndef CONFIG_UX500_SOC_DB5500
+static inline int prcmu_set_display_clocks(void)
+{
+        return 0;
+}
+
+static inline int prcmu_disable_dsipll(void)
+{
+        return 0;
+}
+
+static inline int prcmu_enable_dsipll(void)
+{
+        return 0;
+}
+#endif
+
+static inline int prcmu_enable_spi2(void)
+{
+        return 0;
+}
+
+static inline int prcmu_disable_spi2(void)
+{
+        return 0;
+}
+
+#endif /* !CONFIG_MFD_DB8500_PRCMU */
+
+#ifdef CONFIG_UX500_PRCMU_QOS_POWER
+int prcmu_qos_requirement(int pm_qos_class);
+int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value);
+int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
+void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
+int prcmu_qos_add_notifier(int prcmu_qos_class,
+                           struct notifier_block *notifier);
+int prcmu_qos_remove_notifier(int prcmu_qos_class,
+                              struct notifier_block *notifier);
+#else
+static inline int prcmu_qos_requirement(int prcmu_qos_class)
+{
+        return 0;
+}
+
+static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
+                                            char *name, s32 value)
+{
+        return 0;
+}
+
+static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
+                                               char *name, s32 new_value)
+{
+        return 0;
+}
+
+static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
+{
+}
+
+static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
+                                         struct notifier_block *notifier)
+{
+        return 0;
+}
+static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
+                                            struct notifier_block *notifier)
+{
+        return 0;
+}
+
+#endif
+
+#endif /* __MFD_DB8500_PRCMU_H */
diff --git a/include/linux/mfd/ds1wm.h b/include/linux/mfd/ds1wm.h
index be469a357cbb..38a372a0e285 100644
--- a/include/linux/mfd/ds1wm.h
+++ b/include/linux/mfd/ds1wm.h
@@ -3,4 +3,11 @@
 struct ds1wm_driver_data {
         int active_high;
         int clock_rate;
+        /* in milliseconds, the amount of time to */
+        /* sleep following a reset pulse. Zero    */
+        /* should work if your bus devices recover*/
+        /* time respects the 1-wire spec since the*/
+        /* ds1wm implements the precise timings of*/
+        /* a reset pulse/presence detect sequence.*/
+        unsigned int reset_recover_delay;
 };
diff --git a/include/linux/mfd/max8997-private.h b/include/linux/mfd/max8997-private.h
new file mode 100644
index 000000000000..5ff2400ad46c
--- /dev/null
+++ b/include/linux/mfd/max8997-private.h
@@ -0,0 +1,364 @@
+/*
+ * max8997.h - Voltage regulator driver for the Maxim 8997
+ *
+ *  Copyright (C) 2010 Samsung Electrnoics
+ *  MyungJoo Ham <myungjoo.ham@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __LINUX_MFD_MAX8997_PRIV_H
+#define __LINUX_MFD_MAX8997_PRIV_H
+
+#include <linux/i2c.h>
+
+#define MAX8997_REG_INVALID     (0xff)
+
+enum max8997_pmic_reg {
+        MAX8997_REG_PMIC_ID0    = 0x00,
+        MAX8997_REG_PMIC_ID1    = 0x01,
+        MAX8997_REG_INTSRC      = 0x02,
+        MAX8997_REG_INT1        = 0x03,
+        MAX8997_REG_INT2        = 0x04,
+        MAX8997_REG_INT3        = 0x05,
+        MAX8997_REG_INT4        = 0x06,
+
+        MAX8997_REG_INT1MSK     = 0x08,
+        MAX8997_REG_INT2MSK     = 0x09,
+        MAX8997_REG_INT3MSK     = 0x0a,
+        MAX8997_REG_INT4MSK     = 0x0b,
+
+        MAX8997_REG_STATUS1     = 0x0d,
+        MAX8997_REG_STATUS2     = 0x0e,
+        MAX8997_REG_STATUS3     = 0x0f,
+        MAX8997_REG_STATUS4     = 0x10,
+
+        MAX8997_REG_MAINCON1    = 0x13,
+        MAX8997_REG_MAINCON2    = 0x14,
+        MAX8997_REG_BUCKRAMP    = 0x15,
+
+        MAX8997_REG_BUCK1CTRL   = 0x18,
+        MAX8997_REG_BUCK1DVS1   = 0x19,
+        MAX8997_REG_BUCK1DVS2   = 0x1a,
+        MAX8997_REG_BUCK1DVS3   = 0x1b,
+        MAX8997_REG_BUCK1DVS4   = 0x1c,
+        MAX8997_REG_BUCK1DVS5   = 0x1d,
+        MAX8997_REG_BUCK1DVS6   = 0x1e,
+        MAX8997_REG_BUCK1DVS7   = 0x1f,
+        MAX8997_REG_BUCK1DVS8   = 0x20,
+        MAX8997_REG_BUCK2CTRL   = 0x21,
+        MAX8997_REG_BUCK2DVS1   = 0x22,
+        MAX8997_REG_BUCK2DVS2   = 0x23,
+        MAX8997_REG_BUCK2DVS3   = 0x24,
+        MAX8997_REG_BUCK2DVS4   = 0x25,
+        MAX8997_REG_BUCK2DVS5   = 0x26,
+        MAX8997_REG_BUCK2DVS6   = 0x27,
+        MAX8997_REG_BUCK2DVS7   = 0x28,
+        MAX8997_REG_BUCK2DVS8   = 0x29,
+        MAX8997_REG_BUCK3CTRL   = 0x2a,
+        MAX8997_REG_BUCK3DVS    = 0x2b,
+        MAX8997_REG_BUCK4CTRL   = 0x2c,
+        MAX8997_REG_BUCK4DVS    = 0x2d,
+        MAX8997_REG_BUCK5CTRL   = 0x2e,
+        MAX8997_REG_BUCK5DVS1   = 0x2f,
+        MAX8997_REG_BUCK5DVS2   = 0x30,
+        MAX8997_REG_BUCK5DVS3   = 0x31,
+        MAX8997_REG_BUCK5DVS4   = 0x32,
+        MAX8997_REG_BUCK5DVS5   = 0x33,
+        MAX8997_REG_BUCK5DVS6   = 0x34,
+        MAX8997_REG_BUCK5DVS7   = 0x35,
+        MAX8997_REG_BUCK5DVS8   = 0x36,
+        MAX8997_REG_BUCK6CTRL   = 0x37,
+        MAX8997_REG_BUCK6BPSKIPCTRL     = 0x38,
+        MAX8997_REG_BUCK7CTRL   = 0x39,
+        MAX8997_REG_BUCK7DVS    = 0x3a,
+        MAX8997_REG_LDO1CTRL    = 0x3b,
+        MAX8997_REG_LDO2CTRL    = 0x3c,
+        MAX8997_REG_LDO3CTRL    = 0x3d,
+        MAX8997_REG_LDO4CTRL    = 0x3e,
+        MAX8997_REG_LDO5CTRL    = 0x3f,
+        MAX8997_REG_LDO6CTRL    = 0x40,
+        MAX8997_REG_LDO7CTRL    = 0x41,
+        MAX8997_REG_LDO8CTRL    = 0x42,
+        MAX8997_REG_LDO9CTRL    = 0x43,
+        MAX8997_REG_LDO10CTRL   = 0x44,
+        MAX8997_REG_LDO11CTRL   = 0x45,
+        MAX8997_REG_LDO12CTRL   = 0x46,
+        MAX8997_REG_LDO13CTRL   = 0x47,
+        MAX8997_REG_LDO14CTRL   = 0x48,
+        MAX8997_REG_LDO15CTRL   = 0x49,
+        MAX8997_REG_LDO16CTRL   = 0x4a,
+        MAX8997_REG_LDO17CTRL   = 0x4b,
+        MAX8997_REG_LDO18CTRL   = 0x4c,
+        MAX8997_REG_LDO21CTRL   = 0x4d,
+
+        MAX8997_REG_MBCCTRL1    = 0x50,
+        MAX8997_REG_MBCCTRL2    = 0x51,
+        MAX8997_REG_MBCCTRL3    = 0x52,
+        MAX8997_REG_MBCCTRL4    = 0x53,
+        MAX8997_REG_MBCCTRL5    = 0x54,
+        MAX8997_REG_MBCCTRL6    = 0x55,
+        MAX8997_REG_OTPCGHCVS   = 0x56,
+
+        MAX8997_REG_SAFEOUTCTRL = 0x5a,
+
+        MAX8997_REG_LBCNFG1     = 0x5e,
+        MAX8997_REG_LBCNFG2     = 0x5f,
+        MAX8997_REG_BBCCTRL     = 0x60,
+
+        MAX8997_REG_FLASH1_CUR  = 0x63, /* 0x63 ~ 0x6e for FLASH */
+        MAX8997_REG_FLASH2_CUR  = 0x64,
+        MAX8997_REG_MOVIE_CUR   = 0x65,
+        MAX8997_REG_GSMB_CUR    = 0x66,
+        MAX8997_REG_BOOST_CNTL  = 0x67,
+        MAX8997_REG_LEN_CNTL    = 0x68,
+        MAX8997_REG_FLASH_CNTL  = 0x69,
+        MAX8997_REG_WDT_CNTL    = 0x6a,
+        MAX8997_REG_MAXFLASH1   = 0x6b,
+        MAX8997_REG_MAXFLASH2   = 0x6c,
+        MAX8997_REG_FLASHSTATUS = 0x6d,
+        MAX8997_REG_FLASHSTATUSMASK     = 0x6e,
+
+        MAX8997_REG_GPIOCNTL1   = 0x70,
+        MAX8997_REG_GPIOCNTL2   = 0x71,
+        MAX8997_REG_GPIOCNTL3   = 0x72,
+        MAX8997_REG_GPIOCNTL4   = 0x73,
+        MAX8997_REG_GPIOCNTL5   = 0x74,
+        MAX8997_REG_GPIOCNTL6   = 0x75,
+        MAX8997_REG_GPIOCNTL7   = 0x76,
+        MAX8997_REG_GPIOCNTL8   = 0x77,
+        MAX8997_REG_GPIOCNTL9   = 0x78,
+        MAX8997_REG_GPIOCNTL10  = 0x79,
+        MAX8997_REG_GPIOCNTL11  = 0x7a,
+        MAX8997_REG_GPIOCNTL12  = 0x7b,
+
+        MAX8997_REG_LDO1CONFIG  = 0x80,
+        MAX8997_REG_LDO2CONFIG  = 0x81,
+        MAX8997_REG_LDO3CONFIG  = 0x82,
+        MAX8997_REG_LDO4CONFIG  = 0x83,
+        MAX8997_REG_LDO5CONFIG  = 0x84,
+        MAX8997_REG_LDO6CONFIG  = 0x85,
+        MAX8997_REG_LDO7CONFIG  = 0x86,
+        MAX8997_REG_LDO8CONFIG  = 0x87,
+        MAX8997_REG_LDO9CONFIG  = 0x88,
+        MAX8997_REG_LDO10CONFIG = 0x89,
+        MAX8997_REG_LDO11CONFIG = 0x8a,
+        MAX8997_REG_LDO12CONFIG = 0x8b,
+        MAX8997_REG_LDO13CONFIG = 0x8c,
+        MAX8997_REG_LDO14CONFIG = 0x8d,
+        MAX8997_REG_LDO15CONFIG = 0x8e,
+        MAX8997_REG_LDO16CONFIG = 0x8f,
+        MAX8997_REG_LDO17CONFIG = 0x90,
+        MAX8997_REG_LDO18CONFIG = 0x91,
+        MAX8997_REG_LDO21CONFIG = 0x92,
+
+        MAX8997_REG_DVSOKTIMER1 = 0x97,
+        MAX8997_REG_DVSOKTIMER2 = 0x98,
+        MAX8997_REG_DVSOKTIMER4 = 0x99,
+        MAX8997_REG_DVSOKTIMER5 = 0x9a,
+
+        MAX8997_REG_PMIC_END    = 0x9b,
+};
+
+enum max8997_muic_reg {
+        MAX8997_MUIC_REG_ID             = 0x0,
+        MAX8997_MUIC_REG_INT1           = 0x1,
+        MAX8997_MUIC_REG_INT2           = 0x2,
+        MAX8997_MUIC_REG_INT3           = 0x3,
+        MAX8997_MUIC_REG_STATUS1        = 0x4,
+        MAX8997_MUIC_REG_STATUS2        = 0x5,
+        MAX8997_MUIC_REG_STATUS3        = 0x6,
+        MAX8997_MUIC_REG_INTMASK1       = 0x7,
+        MAX8997_MUIC_REG_INTMASK2       = 0x8,
+        MAX8997_MUIC_REG_INTMASK3       = 0x9,
+        MAX8997_MUIC_REG_CDETCTRL       = 0xa,
+
+        MAX8997_MUIC_REG_CONTROL1       = 0xc,
+        MAX8997_MUIC_REG_CONTROL2       = 0xd,
+        MAX8997_MUIC_REG_CONTROL3       = 0xe,
+
+        MAX8997_MUIC_REG_END            = 0xf,
+};
+
+enum max8997_haptic_reg {
+        MAX8997_HAPTIC_REG_GENERAL      = 0x00,
+        MAX8997_HAPTIC_REG_CONF1        = 0x01,
+        MAX8997_HAPTIC_REG_CONF2        = 0x02,
+        MAX8997_HAPTIC_REG_DRVCONF      = 0x03,
+        MAX8997_HAPTIC_REG_CYCLECONF1   = 0x04,
+        MAX8997_HAPTIC_REG_CYCLECONF2   = 0x05,
+        MAX8997_HAPTIC_REG_SIGCONF1     = 0x06,
+        MAX8997_HAPTIC_REG_SIGCONF2     = 0x07,
+        MAX8997_HAPTIC_REG_SIGCONF3     = 0x08,
+        MAX8997_HAPTIC_REG_SIGCONF4     = 0x09,
+        MAX8997_HAPTIC_REG_SIGDC1       = 0x0a,
+        MAX8997_HAPTIC_REG_SIGDC2       = 0x0b,
+        MAX8997_HAPTIC_REG_SIGPWMDC1    = 0x0c,
+        MAX8997_HAPTIC_REG_SIGPWMDC2    = 0x0d,
+        MAX8997_HAPTIC_REG_SIGPWMDC3    = 0x0e,
+        MAX8997_HAPTIC_REG_SIGPWMDC4    = 0x0f,
+        MAX8997_HAPTIC_REG_MTR_REV      = 0x10,
+
+        MAX8997_HAPTIC_REG_END          = 0x11,
+};
+
+/* slave addr = 0x0c: using "2nd part" of rev4 datasheet */
+enum max8997_rtc_reg {
+        MAX8997_RTC_CTRLMASK            = 0x02,
+        MAX8997_RTC_CTRL                = 0x03,
+        MAX8997_RTC_UPDATE1             = 0x04,
+        MAX8997_RTC_UPDATE2             = 0x05,
+        MAX8997_RTC_WTSR_SMPL           = 0x06,
+
+        MAX8997_RTC_SEC                 = 0x10,
+        MAX8997_RTC_MIN                 = 0x11,
+        MAX8997_RTC_HOUR                = 0x12,
+        MAX8997_RTC_DAY_OF_WEEK         = 0x13,
+        MAX8997_RTC_MONTH               = 0x14,
+        MAX8997_RTC_YEAR                = 0x15,
+        MAX8997_RTC_DAY_OF_MONTH        = 0x16,
+        MAX8997_RTC_ALARM1_SEC          = 0x17,
+        MAX8997_RTC_ALARM1_MIN          = 0x18,
+        MAX8997_RTC_ALARM1_HOUR         = 0x19,
+        MAX8997_RTC_ALARM1_DAY_OF_WEEK  = 0x1a,
+        MAX8997_RTC_ALARM1_MONTH        = 0x1b,
+        MAX8997_RTC_ALARM1_YEAR         = 0x1c,
+        MAX8997_RTC_ALARM1_DAY_OF_MONTH = 0x1d,
+        MAX8997_RTC_ALARM2_SEC          = 0x1e,
+        MAX8997_RTC_ALARM2_MIN          = 0x1f,
+        MAX8997_RTC_ALARM2_HOUR         = 0x20,
+        MAX8997_RTC_ALARM2_DAY_OF_WEEK  = 0x21,
+        MAX8997_RTC_ALARM2_MONTH        = 0x22,
+        MAX8997_RTC_ALARM2_YEAR         = 0x23,
+        MAX8997_RTC_ALARM2_DAY_OF_MONTH = 0x24,
+};
+
+enum max8997_irq_source {
+        PMIC_INT1 = 0,
+        PMIC_INT2,
+        PMIC_INT3,
+        PMIC_INT4,
+
+        FUEL_GAUGE, /* Ignored (MAX17042 driver handles) */
+
+        MUIC_INT1,
+        MUIC_INT2,
+        MUIC_INT3,
+
+        GPIO_LOW, /* Not implemented */
+        GPIO_HI, /* Not implemented */
+
+        FLASH_STATUS, /* Not implemented */
+
+        MAX8997_IRQ_GROUP_NR,
+};
+
+enum max8997_irq {
+        MAX8997_PMICIRQ_PWRONR,
+        MAX8997_PMICIRQ_PWRONF,
+        MAX8997_PMICIRQ_PWRON1SEC,
+        MAX8997_PMICIRQ_JIGONR,
+        MAX8997_PMICIRQ_JIGONF,
+        MAX8997_PMICIRQ_LOWBAT2,
+        MAX8997_PMICIRQ_LOWBAT1,
+
+        MAX8997_PMICIRQ_JIGR,
+        MAX8997_PMICIRQ_JIGF,
+        MAX8997_PMICIRQ_MR,
+        MAX8997_PMICIRQ_DVS1OK,
+        MAX8997_PMICIRQ_DVS2OK,
+        MAX8997_PMICIRQ_DVS3OK,
+        MAX8997_PMICIRQ_DVS4OK,
+
+        MAX8997_PMICIRQ_CHGINS,
+        MAX8997_PMICIRQ_CHGRM,
+        MAX8997_PMICIRQ_DCINOVP,
+        MAX8997_PMICIRQ_TOPOFFR,
+        MAX8997_PMICIRQ_CHGRSTF,
+        MAX8997_PMICIRQ_MBCHGTMEXPD,
+
+        MAX8997_PMICIRQ_RTC60S,
+        MAX8997_PMICIRQ_RTCA1,
+        MAX8997_PMICIRQ_RTCA2,
+        MAX8997_PMICIRQ_SMPL_INT,
+        MAX8997_PMICIRQ_RTC1S,
+        MAX8997_PMICIRQ_WTSR,
+
+        MAX8997_MUICIRQ_ADCError,
+        MAX8997_MUICIRQ_ADCLow,
+        MAX8997_MUICIRQ_ADC,
+
+        MAX8997_MUICIRQ_VBVolt,
+        MAX8997_MUICIRQ_DBChg,
+        MAX8997_MUICIRQ_DCDTmr,
+        MAX8997_MUICIRQ_ChgDetRun,
+        MAX8997_MUICIRQ_ChgTyp,
+
+        MAX8997_MUICIRQ_OVP,
+
+        MAX8997_IRQ_NR,
+};
+
+#define MAX8997_NUM_GPIO        12
+struct max8997_dev {
+        struct device *dev;
+        struct i2c_client *i2c; /* 0xcc / PMIC, Battery Control, and FLASH */
+        struct i2c_client *rtc; /* slave addr 0x0c */
+        struct i2c_client *haptic; /* slave addr 0x90 */
+        struct i2c_client *muic; /* slave addr 0x4a */
+        struct mutex iolock;
+
+        int type;
+        struct platform_device *battery; /* battery control (not fuel gauge) */
+
+        int irq;
+        int ono;
+        int irq_base;
+        bool wakeup;
+        struct mutex irqlock;
+        int irq_masks_cur[MAX8997_IRQ_GROUP_NR];
+        int irq_masks_cache[MAX8997_IRQ_GROUP_NR];
+
+        /* For hibernation */
+        u8 reg_dump[MAX8997_REG_PMIC_END + MAX8997_MUIC_REG_END +
+                MAX8997_HAPTIC_REG_END];
+
+        bool gpio_status[MAX8997_NUM_GPIO];
+};
+
+enum max8997_types {
+        TYPE_MAX8997,
+        TYPE_MAX8966,
+};
+
+extern int max8997_irq_init(struct max8997_dev *max8997);
+extern void max8997_irq_exit(struct max8997_dev *max8997);
+extern int max8997_irq_resume(struct max8997_dev *max8997);
+
+extern int max8997_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest);
+extern int max8997_bulk_read(struct i2c_client *i2c, u8 reg, int count,
+                                u8 *buf);
+extern int max8997_write_reg(struct i2c_client *i2c, u8 reg, u8 value);
+extern int max8997_bulk_write(struct i2c_client *i2c, u8 reg, int count,
+                                u8 *buf);
+extern int max8997_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask);
+
+#define MAX8997_GPIO_INT_BOTH   (0x3 << 4)
+#define MAX8997_GPIO_INT_RISE   (0x2 << 4)
+#define MAX8997_GPIO_INT_FALL   (0x1 << 4)
+
+#define MAX8997_GPIO_INT_MASK   (0x3 << 4)
+#define MAX8997_GPIO_DATA_MASK  (0x1 << 2)
+#endif /*  __LINUX_MFD_MAX8997_PRIV_H */
diff --git a/include/linux/mfd/max8997.h b/include/linux/mfd/max8997.h
new file mode 100644
index 000000000000..60931d089422
--- /dev/null
+++ b/include/linux/mfd/max8997.h
@@ -0,0 +1,117 @@
+/*
+ * max8997.h - Driver for the Maxim 8997/8966
+ *
+ *  Copyright (C) 2009-2010 Samsung Electrnoics
+ *  MyungJoo Ham <myungjoo.ham@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ * This driver is based on max8998.h
+ *
+ * MAX8997 has PMIC, MUIC, HAPTIC, RTC, FLASH, and Fuel Gauge devices.
+ * Except Fuel Gauge, every device shares the same I2C bus and included in
+ * this mfd driver. Although the fuel gauge is included in the chip, it is
+ * excluded from the driver because a) it has a different I2C bus from
+ * others and b) it can be enabled simply by using MAX17042 driver.
+ */
+
+#ifndef __LINUX_MFD_MAX8998_H
+#define __LINUX_MFD_MAX8998_H
+
+#include <linux/regulator/consumer.h>
+
+/* MAX8997/8966 regulator IDs */
+enum max8998_regulators {
+        MAX8997_LDO1 = 0,
+        MAX8997_LDO2,
+        MAX8997_LDO3,
+        MAX8997_LDO4,
+        MAX8997_LDO5,
+        MAX8997_LDO6,
+        MAX8997_LDO7,
+        MAX8997_LDO8,
+        MAX8997_LDO9,
+        MAX8997_LDO10,
+        MAX8997_LDO11,
+        MAX8997_LDO12,
+        MAX8997_LDO13,
+        MAX8997_LDO14,
+        MAX8997_LDO15,
+        MAX8997_LDO16,
+        MAX8997_LDO17,
+        MAX8997_LDO18,
+        MAX8997_LDO21,
+        MAX8997_BUCK1,
+        MAX8997_BUCK2,
+        MAX8997_BUCK3,
+        MAX8997_BUCK4,
+        MAX8997_BUCK5,
+        MAX8997_BUCK6,
+        MAX8997_BUCK7,
+        MAX8997_EN32KHZ_AP,
+        MAX8997_EN32KHZ_CP,
+        MAX8997_ENVICHG,
+        MAX8997_ESAFEOUT1,
+        MAX8997_ESAFEOUT2,
+        MAX8997_CHARGER_CV, /* control MBCCV of MBCCTRL3 */
+        MAX8997_CHARGER, /* charger current, MBCCTRL4 */
+        MAX8997_CHARGER_TOPOFF, /* MBCCTRL5 */
+
+        MAX8997_REG_MAX,
+};
+
+struct max8997_regulator_data {
+        int id;
+        struct regulator_init_data *initdata;
+};
+
+struct max8997_platform_data {
+        /* IRQ */
+        int irq_base;
+        int ono;
+        int wakeup;
+
+        /* ---- PMIC ---- */
+        struct max8997_regulator_data *regulators;
+        int num_regulators;
+
+        /*
+         * SET1~3 DVS GPIOs control Buck1, 2, and 5 simultaneously. Therefore,
+         * With buckx_gpiodvs enabled, the buckx cannot be controlled
+         * independently. To control buckx (of 1, 2, and 5) independently,
+         * disable buckx_gpiodvs and control with BUCKxDVS1 register.
+         *
+         * When buckx_gpiodvs and bucky_gpiodvs are both enabled, set_voltage
+         * on buckx will change the voltage of bucky at the same time.
+         *
+         */
+        bool ignore_gpiodvs_side_effect;
+        int buck125_gpios[3]; /* GPIO of [0]SET1, [1]SET2, [2]SET3 */
+        int buck125_default_idx; /* Default value of SET1, 2, 3 */
+        unsigned int buck1_voltage[8]; /* buckx_voltage in uV */
+        bool buck1_gpiodvs;
+        unsigned int buck2_voltage[8];
+        bool buck2_gpiodvs;
+        unsigned int buck5_voltage[8];
+        bool buck5_gpiodvs;
+
+        /* MUIC: Not implemented */
+        /* HAPTIC: Not implemented */
+        /* RTC: Not implemented */
+        /* Flash: Not implemented */
+        /* Charger control: Not implemented */
+};
+
+#endif /* __LINUX_MFD_MAX8998_H */
diff --git a/include/linux/mfd/max8998-private.h b/include/linux/mfd/max8998-private.h
index 6dc75b3e2d33..effa5d3b96ae 100644
--- a/include/linux/mfd/max8998-private.h
+++ b/include/linux/mfd/max8998-private.h
@@ -1,5 +1,5 @@
 /*
- * max8698.h - Voltage regulator driver for the Maxim 8998
+ * max8998.h - Voltage regulator driver for the Maxim 8998
  *
  *  Copyright (C) 2009-2010 Samsung Electrnoics
  *  Kyungmin Park <kyungmin.park@samsung.com>
@@ -23,6 +23,8 @@
 #ifndef __LINUX_MFD_MAX8998_PRIV_H
 #define __LINUX_MFD_MAX8998_PRIV_H
 
+#define MAX8998_NUM_IRQ_REGS    4
+
 /* MAX 8998 registers */
 enum {
         MAX8998_REG_IRQ1,
@@ -46,12 +48,12 @@ enum {
         MAX8998_REG_ONOFF2,
         MAX8998_REG_ONOFF3,
         MAX8998_REG_ONOFF4,
-        MAX8998_REG_BUCK1_DVSARM1,
-        MAX8998_REG_BUCK1_DVSARM2,
-        MAX8998_REG_BUCK1_DVSARM3,
-        MAX8998_REG_BUCK1_DVSARM4,
-        MAX8998_REG_BUCK2_DVSINT1,
-        MAX8998_REG_BUCK2_DVSINT2,
+        MAX8998_REG_BUCK1_VOLTAGE1,
+        MAX8998_REG_BUCK1_VOLTAGE2,
+        MAX8998_REG_BUCK1_VOLTAGE3,
+        MAX8998_REG_BUCK1_VOLTAGE4,
+        MAX8998_REG_BUCK2_VOLTAGE1,
+        MAX8998_REG_BUCK2_VOLTAGE2,
         MAX8998_REG_BUCK3,
         MAX8998_REG_BUCK4,
         MAX8998_REG_LDO2_LDO3,
@@ -72,41 +74,104 @@ enum {
         MAX8998_REG_LBCNFG2,
 };
 
+/* IRQ definitions */
+enum {
+        MAX8998_IRQ_DCINF,
+        MAX8998_IRQ_DCINR,
+        MAX8998_IRQ_JIGF,
+        MAX8998_IRQ_JIGR,
+        MAX8998_IRQ_PWRONF,
+        MAX8998_IRQ_PWRONR,
+
+        MAX8998_IRQ_WTSREVNT,
+        MAX8998_IRQ_SMPLEVNT,
+        MAX8998_IRQ_ALARM1,
+        MAX8998_IRQ_ALARM0,
+
+        MAX8998_IRQ_ONKEY1S,
+        MAX8998_IRQ_TOPOFFR,
+        MAX8998_IRQ_DCINOVPR,
+        MAX8998_IRQ_CHGRSTF,
+        MAX8998_IRQ_DONER,
+        MAX8998_IRQ_CHGFAULT,
+
+        MAX8998_IRQ_LOBAT1,
+        MAX8998_IRQ_LOBAT2,
+
+        MAX8998_IRQ_NR,
+};
+
+/* MAX8998 various variants */
+enum {
+        TYPE_MAX8998 = 0, /* Default */
+        TYPE_LP3974,    /* National version of MAX8998 */
+        TYPE_LP3979,    /* Added AVS */
+};
+
+#define MAX8998_IRQ_DCINF_MASK          (1 << 2)
+#define MAX8998_IRQ_DCINR_MASK          (1 << 3)
+#define MAX8998_IRQ_JIGF_MASK           (1 << 4)
+#define MAX8998_IRQ_JIGR_MASK           (1 << 5)
+#define MAX8998_IRQ_PWRONF_MASK         (1 << 6)
+#define MAX8998_IRQ_PWRONR_MASK         (1 << 7)
+
+#define MAX8998_IRQ_WTSREVNT_MASK       (1 << 0)
+#define MAX8998_IRQ_SMPLEVNT_MASK       (1 << 1)
+#define MAX8998_IRQ_ALARM1_MASK         (1 << 2)
+#define MAX8998_IRQ_ALARM0_MASK         (1 << 3)
+
+#define MAX8998_IRQ_ONKEY1S_MASK        (1 << 0)
+#define MAX8998_IRQ_TOPOFFR_MASK        (1 << 2)
+#define MAX8998_IRQ_DCINOVPR_MASK       (1 << 3)
+#define MAX8998_IRQ_CHGRSTF_MASK        (1 << 4)
+#define MAX8998_IRQ_DONER_MASK          (1 << 5)
+#define MAX8998_IRQ_CHGFAULT_MASK       (1 << 7)
+
+#define MAX8998_IRQ_LOBAT1_MASK         (1 << 0)
+#define MAX8998_IRQ_LOBAT2_MASK         (1 << 1)
+
+#define MAX8998_ENRAMP                  (1 << 4)
+
 /**
  * struct max8998_dev - max8998 master device for sub-drivers
  * @dev: master device of the chip (can be used to access platform data)
- * @i2c_client: i2c client private data
- * @dev_read(): chip register read function
- * @dev_write(): chip register write function
- * @dev_update(): chip register update function
+ * @i2c: i2c client private data for regulator
+ * @rtc: i2c client private data for rtc
  * @iolock: mutex for serializing io access
+ * @irqlock: mutex for buslock
+ * @irq_base: base IRQ number for max8998, required for IRQs
+ * @irq: generic IRQ number for max8998
+ * @ono: power onoff IRQ number for max8998
+ * @irq_masks_cur: currently active value
+ * @irq_masks_cache: cached hardware value
+ * @type: indicate which max8998 "variant" is used
  */
-
 struct max8998_dev {
         struct device *dev;
-        struct i2c_client *i2c_client;
-        int (*dev_read)(struct max8998_dev *max8998, u8 reg, u8 *dest);
-        int (*dev_write)(struct max8998_dev *max8998, u8 reg, u8 val);
-        int (*dev_update)(struct max8998_dev *max8998, u8 reg, u8 val, u8 mask);
+        struct i2c_client *i2c;
+        struct i2c_client *rtc;
         struct mutex iolock;
+        struct mutex irqlock;
+
+        int irq_base;
+        int irq;
+        int ono;
+        u8 irq_masks_cur[MAX8998_NUM_IRQ_REGS];
+        u8 irq_masks_cache[MAX8998_NUM_IRQ_REGS];
+        int type;
+        bool wakeup;
 };
 
-static inline int max8998_read_reg(struct max8998_dev *max8998, u8 reg,
-                                   u8 *value)
-{
-        return max8998->dev_read(max8998, reg, value);
-}
-
-static inline int max8998_write_reg(struct max8998_dev *max8998, u8 reg,
-                                    u8 value)
-{
-        return max8998->dev_write(max8998, reg, value);
-}
-
-static inline int max8998_update_reg(struct max8998_dev *max8998, u8 reg,
-                                     u8 value, u8 mask)
-{
-        return max8998->dev_update(max8998, reg, value, mask);
-}
+int max8998_irq_init(struct max8998_dev *max8998);
+void max8998_irq_exit(struct max8998_dev *max8998);
+int max8998_irq_resume(struct max8998_dev *max8998);
+
+extern int max8998_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest);
+extern int max8998_bulk_read(struct i2c_client *i2c, u8 reg, int count,
+                u8 *buf);
+extern int max8998_write_reg(struct i2c_client *i2c, u8 reg, u8 value);
+extern int max8998_bulk_write(struct i2c_client *i2c, u8 reg, int count,
+                u8 *buf);
+extern int max8998_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask);
 
 #endif /*  __LINUX_MFD_MAX8998_PRIV_H */
diff --git a/include/linux/mfd/max8998.h b/include/linux/mfd/max8998.h
index 1d3601a2d853..61daa167b576 100644
--- a/include/linux/mfd/max8998.h
+++ b/include/linux/mfd/max8998.h
@@ -1,5 +1,5 @@
 /*
- * max8698.h - Voltage regulator driver for the Maxim 8998
+ * max8998.h - Voltage regulator driver for the Maxim 8998
  *
  *  Copyright (C) 2009-2010 Samsung Electrnoics
  *  Kyungmin Park <kyungmin.park@samsung.com>
@@ -66,13 +66,47 @@ struct max8998_regulator_data {
 
 /**
  * struct max8998_board - packages regulator init data
- * @num_regulators: number of regultors used
  * @regulators: array of defined regulators
+ * @num_regulators: number of regultors used
+ * @irq_base: base IRQ number for max8998, required for IRQs
+ * @ono: power onoff IRQ number for max8998
+ * @buck_voltage_lock: Do NOT change the values of the following six
+ *   registers set by buck?_voltage?. The voltage of BUCK1/2 cannot
+ *   be other than the preset values.
+ * @buck1_voltage1: BUCK1 DVS mode 1 voltage register
+ * @buck1_voltage2: BUCK1 DVS mode 2 voltage register
+ * @buck1_voltage3: BUCK1 DVS mode 3 voltage register
+ * @buck1_voltage4: BUCK1 DVS mode 4 voltage register
+ * @buck2_voltage1: BUCK2 DVS mode 1 voltage register
+ * @buck2_voltage2: BUCK2 DVS mode 2 voltage register
+ * @buck1_set1: BUCK1 gpio pin 1 to set output voltage
+ * @buck1_set2: BUCK1 gpio pin 2 to set output voltage
+ * @buck1_default_idx: Default for BUCK1 gpio pin 1, 2
+ * @buck2_set3: BUCK2 gpio pin to set output voltage
+ * @buck2_default_idx: Default for BUCK2 gpio pin.
+ * @wakeup: Allow to wake up from suspend
+ * @rtc_delay: LP3974 RTC chip bug that requires delay after a register
+ * write before reading it.
  */
-
 struct max8998_platform_data {
-        int                             num_regulators;
         struct max8998_regulator_data   *regulators;
+        int                             num_regulators;
+        int                             irq_base;
+        int                             ono;
+        bool                            buck_voltage_lock;
+        int                             buck1_voltage1;
+        int                             buck1_voltage2;
+        int                             buck1_voltage3;
+        int                             buck1_voltage4;
+        int                             buck2_voltage1;
+        int                             buck2_voltage2;
+        int                             buck1_set1;
+        int                             buck1_set2;
+        int                             buck1_default_idx;
+        int                             buck2_set3;
+        int                             buck2_default_idx;
+        bool                            wakeup;
+        bool                            rtc_delay;
 };
 
 #endif /*  __LINUX_MFD_MAX8998_H */
diff --git a/include/linux/mfd/mc13783.h b/include/linux/mfd/mc13783.h
index 0fa44fb8dd26..7d0f3d6a0002 100644
--- a/include/linux/mfd/mc13783.h
+++ b/include/linux/mfd/mc13783.h
@@ -1,5 +1,6 @@
 /*
- * Copyright 2009 Pengutronix
+ * Copyright 2010 Yong Shen <yong.shen@linaro.org>
+ * Copyright 2009-2010 Pengutronix
  * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
  *
  * This program is free software; you can redistribute it and/or modify it under
@@ -9,48 +10,83 @@
 #ifndef __LINUX_MFD_MC13783_H
 #define __LINUX_MFD_MC13783_H
 
-#include <linux/interrupt.h>
+#include <linux/mfd/mc13xxx.h>
 
 struct mc13783;
 
-void mc13783_lock(struct mc13783 *mc13783);
-void mc13783_unlock(struct mc13783 *mc13783);
+struct mc13xxx *mc13783_to_mc13xxx(struct mc13783 *mc13783);
 
-int mc13783_reg_read(struct mc13783 *mc13783, unsigned int offset, u32 *val);
-int mc13783_reg_write(struct mc13783 *mc13783, unsigned int offset, u32 val);
-int mc13783_reg_rmw(struct mc13783 *mc13783, unsigned int offset,
-                u32 mask, u32 val);
+static inline void mc13783_lock(struct mc13783 *mc13783)
+{
+        mc13xxx_lock(mc13783_to_mc13xxx(mc13783));
+}
+
+static inline void mc13783_unlock(struct mc13783 *mc13783)
+{
+        mc13xxx_unlock(mc13783_to_mc13xxx(mc13783));
+}
+
+static inline int mc13783_reg_read(struct mc13783 *mc13783,
+                unsigned int offset, u32 *val)
+{
+        return mc13xxx_reg_read(mc13783_to_mc13xxx(mc13783), offset, val);
+}
+
+static inline int mc13783_reg_write(struct mc13783 *mc13783,
+                unsigned int offset, u32 val)
+{
+        return mc13xxx_reg_write(mc13783_to_mc13xxx(mc13783), offset, val);
+}
+
+static inline int mc13783_reg_rmw(struct mc13783 *mc13783,
+                unsigned int offset, u32 mask, u32 val)
+{
+        return mc13xxx_reg_rmw(mc13783_to_mc13xxx(mc13783), offset, mask, val);
+}
 
-int mc13783_get_flags(struct mc13783 *mc13783);
+static inline int mc13783_get_flags(struct mc13783 *mc13783)
+{
+        return mc13xxx_get_flags(mc13783_to_mc13xxx(mc13783));
+}
 
-int mc13783_irq_request(struct mc13783 *mc13783, int irq,
-                irq_handler_t handler, const char *name, void *dev);
-int mc13783_irq_request_nounmask(struct mc13783 *mc13783, int irq,
-                irq_handler_t handler, const char *name, void *dev);
-int mc13783_irq_free(struct mc13783 *mc13783, int irq, void *dev);
+static inline int mc13783_irq_request(struct mc13783 *mc13783, int irq,
+                irq_handler_t handler, const char *name, void *dev)
+{
+        return mc13xxx_irq_request(mc13783_to_mc13xxx(mc13783), irq,
+                        handler, name, dev);
+}
 
-int mc13783_irq_mask(struct mc13783 *mc13783, int irq);
-int mc13783_irq_unmask(struct mc13783 *mc13783, int irq);
-int mc13783_irq_status(struct mc13783 *mc13783, int irq,
-                int *enabled, int *pending);
-int mc13783_irq_ack(struct mc13783 *mc13783, int irq);
+static inline int mc13783_irq_request_nounmask(struct mc13783 *mc13783, int irq,
+                irq_handler_t handler, const char *name, void *dev)
+{
+        return mc13xxx_irq_request_nounmask(mc13783_to_mc13xxx(mc13783), irq,
+                        handler, name, dev);
+}
 
-static inline int mc13783_mask(struct mc13783 *mc13783, int irq) __deprecated;
-static inline int mc13783_mask(struct mc13783 *mc13783, int irq)
+static inline int mc13783_irq_free(struct mc13783 *mc13783, int irq, void *dev)
 {
-        return mc13783_irq_mask(mc13783, irq);
+        return mc13xxx_irq_free(mc13783_to_mc13xxx(mc13783), irq, dev);
 }
 
-static inline int mc13783_unmask(struct mc13783 *mc13783, int irq) __deprecated;
-static inline int mc13783_unmask(struct mc13783 *mc13783, int irq)
+static inline int mc13783_irq_mask(struct mc13783 *mc13783, int irq)
 {
-        return mc13783_irq_unmask(mc13783, irq);
+        return mc13xxx_irq_mask(mc13783_to_mc13xxx(mc13783), irq);
 }
 
-static inline int mc13783_ackirq(struct mc13783 *mc13783, int irq) __deprecated;
-static inline int mc13783_ackirq(struct mc13783 *mc13783, int irq)
+static inline int mc13783_irq_unmask(struct mc13783 *mc13783, int irq)
 {
-        return mc13783_irq_ack(mc13783, irq);
+        return mc13xxx_irq_unmask(mc13783_to_mc13xxx(mc13783), irq);
+}
+static inline int mc13783_irq_status(struct mc13783 *mc13783, int irq,
+                int *enabled, int *pending)
+{
+        return mc13xxx_irq_status(mc13783_to_mc13xxx(mc13783),
+                        irq, enabled, pending);
+}
+
+static inline int mc13783_irq_ack(struct mc13783 *mc13783, int irq)
+{
+        return mc13xxx_irq_ack(mc13783_to_mc13xxx(mc13783), irq);
 }
 
 #define MC13783_ADC0            43
@@ -66,96 +102,18 @@ static inline int mc13783_ackirq(struct mc13783 *mc13783, int irq)
                                         MC13783_ADC0_TSMOD1 | \
                                         MC13783_ADC0_TSMOD2)
 
-struct mc13783_led_platform_data {
-#define MC13783_LED_MD          0
-#define MC13783_LED_AD          1
-#define MC13783_LED_KP          2
-#define MC13783_LED_R1          3
-#define MC13783_LED_G1          4
-#define MC13783_LED_B1          5
-#define MC13783_LED_R2          6
-#define MC13783_LED_G2          7
-#define MC13783_LED_B2          8
-#define MC13783_LED_R3          9
-#define MC13783_LED_G3          10
-#define MC13783_LED_B3          11
-#define MC13783_LED_MAX MC13783_LED_B3
-        int id;
-        const char *name;
-        const char *default_trigger;
-
-/* Three or two bits current selection depending on the led */
-        char max_current;
-};
-
-struct mc13783_leds_platform_data {
-        int num_leds;
-        struct mc13783_led_platform_data *led;
-
-#define MC13783_LED_TRIODE_MD   (1 << 0)
-#define MC13783_LED_TRIODE_AD   (1 << 1)
-#define MC13783_LED_TRIODE_KP   (1 << 2)
-#define MC13783_LED_BOOST_EN    (1 << 3)
-#define MC13783_LED_TC1HALF     (1 << 4)
-#define MC13783_LED_SLEWLIMTC   (1 << 5)
-#define MC13783_LED_SLEWLIMBL   (1 << 6)
-#define MC13783_LED_TRIODE_TC1  (1 << 7)
-#define MC13783_LED_TRIODE_TC2  (1 << 8)
-#define MC13783_LED_TRIODE_TC3  (1 << 9)
-        int flags;
-
-#define MC13783_LED_AB_DISABLED         0
-#define MC13783_LED_AB_MD1              1
-#define MC13783_LED_AB_MD12             2
-#define MC13783_LED_AB_MD123            3
-#define MC13783_LED_AB_MD1234           4
-#define MC13783_LED_AB_MD1234_AD1       5
-#define MC13783_LED_AB_MD1234_AD12      6
-#define MC13783_LED_AB_MD1_AD           7
-        char abmode;
-
-#define MC13783_LED_ABREF_200MV 0
-#define MC13783_LED_ABREF_400MV 1
-#define MC13783_LED_ABREF_600MV 2
-#define MC13783_LED_ABREF_800MV 3
-        char abref;
-
-#define MC13783_LED_PERIOD_10MS         0
-#define MC13783_LED_PERIOD_100MS        1
-#define MC13783_LED_PERIOD_500MS        2
-#define MC13783_LED_PERIOD_2S           3
-        char bl_period;
-        char tc1_period;
-        char tc2_period;
-        char tc3_period;
-};
-
-/* to be cleaned up */
-struct regulator_init_data;
-
-struct mc13783_regulator_init_data {
-        int id;
-        struct regulator_init_data *init_data;
-};
-
-struct mc13783_regulator_platform_data {
-        int num_regulators;
-        struct mc13783_regulator_init_data *regulators;
-};
-
-struct mc13783_platform_data {
-        int num_regulators;
-        struct mc13783_regulator_init_data *regulators;
-        struct mc13783_leds_platform_data *leds;
-
-#define MC13783_USE_TOUCHSCREEN (1 << 0)
-#define MC13783_USE_CODEC       (1 << 1)
-#define MC13783_USE_ADC         (1 << 2)
-#define MC13783_USE_RTC         (1 << 3)
-#define MC13783_USE_REGULATOR   (1 << 4)
-#define MC13783_USE_LED         (1 << 5)
-        unsigned int flags;
-};
+#define mc13783_regulator_init_data mc13xxx_regulator_init_data
+#define mc13783_regulator_platform_data mc13xxx_regulator_platform_data
+#define mc13783_led_platform_data mc13xxx_led_platform_data
+#define mc13783_leds_platform_data mc13xxx_leds_platform_data
+
+#define mc13783_platform_data mc13xxx_platform_data
+#define MC13783_USE_TOUCHSCREEN MC13XXX_USE_TOUCHSCREEN
+#define MC13783_USE_CODEC       MC13XXX_USE_CODEC
+#define MC13783_USE_ADC         MC13XXX_USE_ADC
+#define MC13783_USE_RTC         MC13XXX_USE_RTC
+#define MC13783_USE_REGULATOR   MC13XXX_USE_REGULATOR
+#define MC13783_USE_LED         MC13XXX_USE_LED
 
 #define MC13783_ADC_MODE_TS             1
 #define MC13783_ADC_MODE_SINGLE_CHAN    2
@@ -165,80 +123,80 @@ int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode,
                 unsigned int channel, unsigned int *sample);
 
 
-#define MC13783_SW_SW1A         0
-#define MC13783_SW_SW1B         1
-#define MC13783_SW_SW2A         2
-#define MC13783_SW_SW2B         3
-#define MC13783_SW_SW3          4
-#define MC13783_SW_PLL          5
-#define MC13783_REGU_VAUDIO     6
-#define MC13783_REGU_VIOHI      7
-#define MC13783_REGU_VIOLO      8
-#define MC13783_REGU_VDIG       9
-#define MC13783_REGU_VGEN       10
-#define MC13783_REGU_VRFDIG     11
-#define MC13783_REGU_VRFREF     12
-#define MC13783_REGU_VRFCP      13
-#define MC13783_REGU_VSIM       14
-#define MC13783_REGU_VESIM      15
-#define MC13783_REGU_VCAM       16
-#define MC13783_REGU_VRFBG      17
-#define MC13783_REGU_VVIB       18
-#define MC13783_REGU_VRF1       19
-#define MC13783_REGU_VRF2       20
-#define MC13783_REGU_VMMC1      21
-#define MC13783_REGU_VMMC2      22
-#define MC13783_REGU_GPO1       23
-#define MC13783_REGU_GPO2       24
-#define MC13783_REGU_GPO3       25
-#define MC13783_REGU_GPO4       26
-#define MC13783_REGU_V1         27
-#define MC13783_REGU_V2         28
-#define MC13783_REGU_V3         29
-#define MC13783_REGU_V4         30
-#define MC13783_REGU_PWGT1SPI   31
-#define MC13783_REGU_PWGT2SPI   32
-
-#define MC13783_IRQ_ADCDONE     0
-#define MC13783_IRQ_ADCBISDONE  1
-#define MC13783_IRQ_TS          2
+#define MC13783_REG_SW1A                0
+#define MC13783_REG_SW1B                1
+#define MC13783_REG_SW2A                2
+#define MC13783_REG_SW2B                3
+#define MC13783_REG_SW3         4
+#define MC13783_REG_PLL         5
+#define MC13783_REG_VAUDIO      6
+#define MC13783_REG_VIOHI       7
+#define MC13783_REG_VIOLO       8
+#define MC13783_REG_VDIG        9
+#define MC13783_REG_VGEN        10
+#define MC13783_REG_VRFDIG      11
+#define MC13783_REG_VRFREF      12
+#define MC13783_REG_VRFCP       13
+#define MC13783_REG_VSIM        14
+#define MC13783_REG_VESIM       15
+#define MC13783_REG_VCAM        16
+#define MC13783_REG_VRFBG       17
+#define MC13783_REG_VVIB        18
+#define MC13783_REG_VRF1        19
+#define MC13783_REG_VRF2        20
+#define MC13783_REG_VMMC1       21
+#define MC13783_REG_VMMC2       22
+#define MC13783_REG_GPO1        23
+#define MC13783_REG_GPO2        24
+#define MC13783_REG_GPO3        25
+#define MC13783_REG_GPO4        26
+#define MC13783_REG_V1          27
+#define MC13783_REG_V2          28
+#define MC13783_REG_V3          29
+#define MC13783_REG_V4          30
+#define MC13783_REG_PWGT1SPI    31
+#define MC13783_REG_PWGT2SPI    32
+
+#define MC13783_IRQ_ADCDONE     MC13XXX_IRQ_ADCDONE
+#define MC13783_IRQ_ADCBISDONE  MC13XXX_IRQ_ADCBISDONE
+#define MC13783_IRQ_TS          MC13XXX_IRQ_TS
 #define MC13783_IRQ_WHIGH       3
 #define MC13783_IRQ_WLOW        4
-#define MC13783_IRQ_CHGDET      6
+#define MC13783_IRQ_CHGDET      MC13XXX_IRQ_CHGDET
 #define MC13783_IRQ_CHGOV       7
-#define MC13783_IRQ_CHGREV      8
-#define MC13783_IRQ_CHGSHORT    9
-#define MC13783_IRQ_CCCV        10
-#define MC13783_IRQ_CHGCURR     11
-#define MC13783_IRQ_BPON        12
-#define MC13783_IRQ_LOBATL      13
-#define MC13783_IRQ_LOBATH      14
+#define MC13783_IRQ_CHGREV      MC13XXX_IRQ_CHGREV
+#define MC13783_IRQ_CHGSHORT    MC13XXX_IRQ_CHGSHORT
+#define MC13783_IRQ_CCCV        MC13XXX_IRQ_CCCV
+#define MC13783_IRQ_CHGCURR     MC13XXX_IRQ_CHGCURR
+#define MC13783_IRQ_BPON        MC13XXX_IRQ_BPON
+#define MC13783_IRQ_LOBATL      MC13XXX_IRQ_LOBATL
+#define MC13783_IRQ_LOBATH      MC13XXX_IRQ_LOBATH
 #define MC13783_IRQ_UDP         15
 #define MC13783_IRQ_USB         16
 #define MC13783_IRQ_ID          19
 #define MC13783_IRQ_SE1         21
 #define MC13783_IRQ_CKDET       22
 #define MC13783_IRQ_UDM         23
-#define MC13783_IRQ_1HZ         24
-#define MC13783_IRQ_TODA        25
+#define MC13783_IRQ_1HZ         MC13XXX_IRQ_1HZ
+#define MC13783_IRQ_TODA        MC13XXX_IRQ_TODA
 #define MC13783_IRQ_ONOFD1      27
 #define MC13783_IRQ_ONOFD2      28
 #define MC13783_IRQ_ONOFD3      29
-#define MC13783_IRQ_SYSRST      30
-#define MC13783_IRQ_RTCRST      31
-#define MC13783_IRQ_PC          32
-#define MC13783_IRQ_WARM        33
-#define MC13783_IRQ_MEMHLD      34
+#define MC13783_IRQ_SYSRST      MC13XXX_IRQ_SYSRST
+#define MC13783_IRQ_RTCRST      MC13XXX_IRQ_RTCRST
+#define MC13783_IRQ_PC          MC13XXX_IRQ_PC
+#define MC13783_IRQ_WARM        MC13XXX_IRQ_WARM
+#define MC13783_IRQ_MEMHLD      MC13XXX_IRQ_MEMHLD
 #define MC13783_IRQ_PWRRDY      35
-#define MC13783_IRQ_THWARNL     36
-#define MC13783_IRQ_THWARNH     37
-#define MC13783_IRQ_CLK         38
+#define MC13783_IRQ_THWARNL     MC13XXX_IRQ_THWARNL
+#define MC13783_IRQ_THWARNH     MC13XXX_IRQ_THWARNH
+#define MC13783_IRQ_CLK         MC13XXX_IRQ_CLK
 #define MC13783_IRQ_SEMAF       39
 #define MC13783_IRQ_MC2B        41
 #define MC13783_IRQ_HSDET       42
 #define MC13783_IRQ_HSL         43
 #define MC13783_IRQ_ALSPTH      44
 #define MC13783_IRQ_AHSSHORT    45
-#define MC13783_NUM_IRQ         46
+#define MC13783_NUM_IRQ         MC13XXX_NUM_IRQ
 
-#endif /* __LINUX_MFD_MC13783_H */
+#endif /* ifndef __LINUX_MFD_MC13783_H */
diff --git a/include/linux/mfd/mc13892.h b/include/linux/mfd/mc13892.h
new file mode 100644
index 000000000000..a00f2bec178c
--- /dev/null
+++ b/include/linux/mfd/mc13892.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2010 Yong Shen <yong.shen@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+
+#ifndef __LINUX_MFD_MC13892_H
+#define __LINUX_MFD_MC13892_H
+
+#include <linux/mfd/mc13xxx.h>
+
+#define MC13892_SW1             0
+#define MC13892_SW2             1
+#define MC13892_SW3             2
+#define MC13892_SW4             3
+#define MC13892_SWBST   4
+#define MC13892_VIOHI   5
+#define MC13892_VPLL    6
+#define MC13892_VDIG    7
+#define MC13892_VSD     8
+#define MC13892_VUSB2   9
+#define MC13892_VVIDEO  10
+#define MC13892_VAUDIO  11
+#define MC13892_VCAM    12
+#define MC13892_VGEN1   13
+#define MC13892_VGEN2   14
+#define MC13892_VGEN3   15
+#define MC13892_VUSB    16
+#define MC13892_GPO1    17
+#define MC13892_GPO2    18
+#define MC13892_GPO3    19
+#define MC13892_GPO4    20
+#define MC13892_PWGT1SPI        21
+#define MC13892_PWGT2SPI        22
+#define MC13892_VCOINCELL       23
+
+#endif
diff --git a/include/linux/mfd/mc13xxx.h b/include/linux/mfd/mc13xxx.h
new file mode 100644
index 000000000000..c064beaaccb7
--- /dev/null
+++ b/include/linux/mfd/mc13xxx.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright 2009-2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#ifndef __LINUX_MFD_MC13XXX_H
+#define __LINUX_MFD_MC13XXX_H
+
+#include <linux/interrupt.h>
+
+struct mc13xxx;
+
+void mc13xxx_lock(struct mc13xxx *mc13xxx);
+void mc13xxx_unlock(struct mc13xxx *mc13xxx);
+
+int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val);
+int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val);
+int mc13xxx_reg_rmw(struct mc13xxx *mc13xxx, unsigned int offset,
+                u32 mask, u32 val);
+
+int mc13xxx_get_flags(struct mc13xxx *mc13xxx);
+
+int mc13xxx_irq_request(struct mc13xxx *mc13xxx, int irq,
+                irq_handler_t handler, const char *name, void *dev);
+int mc13xxx_irq_request_nounmask(struct mc13xxx *mc13xxx, int irq,
+                irq_handler_t handler, const char *name, void *dev);
+int mc13xxx_irq_free(struct mc13xxx *mc13xxx, int irq, void *dev);
+
+int mc13xxx_irq_mask(struct mc13xxx *mc13xxx, int irq);
+int mc13xxx_irq_unmask(struct mc13xxx *mc13xxx, int irq);
+int mc13xxx_irq_status(struct mc13xxx *mc13xxx, int irq,
+                int *enabled, int *pending);
+int mc13xxx_irq_ack(struct mc13xxx *mc13xxx, int irq);
+
+int mc13xxx_get_flags(struct mc13xxx *mc13xxx);
+
+#define MC13XXX_IRQ_ADCDONE     0
+#define MC13XXX_IRQ_ADCBISDONE  1
+#define MC13XXX_IRQ_TS          2
+#define MC13XXX_IRQ_CHGDET      6
+#define MC13XXX_IRQ_CHGREV      8
+#define MC13XXX_IRQ_CHGSHORT    9
+#define MC13XXX_IRQ_CCCV        10
+#define MC13XXX_IRQ_CHGCURR     11
+#define MC13XXX_IRQ_BPON        12
+#define MC13XXX_IRQ_LOBATL      13
+#define MC13XXX_IRQ_LOBATH      14
+#define MC13XXX_IRQ_1HZ         24
+#define MC13XXX_IRQ_TODA        25
+#define MC13XXX_IRQ_SYSRST      30
+#define MC13XXX_IRQ_RTCRST      31
+#define MC13XXX_IRQ_PC          32
+#define MC13XXX_IRQ_WARM        33
+#define MC13XXX_IRQ_MEMHLD      34
+#define MC13XXX_IRQ_THWARNL     36
+#define MC13XXX_IRQ_THWARNH     37
+#define MC13XXX_IRQ_CLK         38
+
+#define MC13XXX_NUM_IRQ         46
+
+struct regulator_init_data;
+
+struct mc13xxx_regulator_init_data {
+        int id;
+        struct regulator_init_data *init_data;
+};
+
+struct mc13xxx_regulator_platform_data {
+        int num_regulators;
+        struct mc13xxx_regulator_init_data *regulators;
+};
+
+struct mc13xxx_led_platform_data {
+#define MC13783_LED_MD          0
+#define MC13783_LED_AD          1
+#define MC13783_LED_KP          2
+#define MC13783_LED_R1          3
+#define MC13783_LED_G1          4
+#define MC13783_LED_B1          5
+#define MC13783_LED_R2          6
+#define MC13783_LED_G2          7
+#define MC13783_LED_B2          8
+#define MC13783_LED_R3          9
+#define MC13783_LED_G3          10
+#define MC13783_LED_B3          11
+#define MC13783_LED_MAX MC13783_LED_B3
+        int id;
+        const char *name;
+        const char *default_trigger;
+
+/* Three or two bits current selection depending on the led */
+        char max_current;
+};
+
+struct mc13xxx_leds_platform_data {
+        int num_leds;
+        struct mc13xxx_led_platform_data *led;
+
+#define MC13783_LED_TRIODE_MD   (1 << 0)
+#define MC13783_LED_TRIODE_AD   (1 << 1)
+#define MC13783_LED_TRIODE_KP   (1 << 2)
+#define MC13783_LED_BOOST_EN    (1 << 3)
+#define MC13783_LED_TC1HALF     (1 << 4)
+#define MC13783_LED_SLEWLIMTC   (1 << 5)
+#define MC13783_LED_SLEWLIMBL   (1 << 6)
+#define MC13783_LED_TRIODE_TC1  (1 << 7)
+#define MC13783_LED_TRIODE_TC2  (1 << 8)
+#define MC13783_LED_TRIODE_TC3  (1 << 9)
+        int flags;
+
+#define MC13783_LED_AB_DISABLED         0
+#define MC13783_LED_AB_MD1              1
+#define MC13783_LED_AB_MD12             2
+#define MC13783_LED_AB_MD123            3
+#define MC13783_LED_AB_MD1234           4
+#define MC13783_LED_AB_MD1234_AD1       5
+#define MC13783_LED_AB_MD1234_AD12      6
+#define MC13783_LED_AB_MD1_AD           7
+        char abmode;
+
+#define MC13783_LED_ABREF_200MV 0
+#define MC13783_LED_ABREF_400MV 1
+#define MC13783_LED_ABREF_600MV 2
+#define MC13783_LED_ABREF_800MV 3
+        char abref;
+
+#define MC13783_LED_PERIOD_10MS         0
+#define MC13783_LED_PERIOD_100MS        1
+#define MC13783_LED_PERIOD_500MS        2
+#define MC13783_LED_PERIOD_2S           3
+        char bl_period;
+        char tc1_period;
+        char tc2_period;
+        char tc3_period;
+};
+
+struct mc13xxx_platform_data {
+#define MC13XXX_USE_TOUCHSCREEN (1 << 0)
+#define MC13XXX_USE_CODEC       (1 << 1)
+#define MC13XXX_USE_ADC         (1 << 2)
+#define MC13XXX_USE_RTC         (1 << 3)
+#define MC13XXX_USE_REGULATOR   (1 << 4)
+#define MC13XXX_USE_LED         (1 << 5)
+        unsigned int flags;
+
+        struct mc13xxx_regulator_platform_data regulators;
+        struct mc13xxx_leds_platform_data *leds;
+};
+
+#endif /* ifndef __LINUX_MFD_MC13XXX_H */
diff --git a/include/linux/mfd/pcf50633/core.h b/include/linux/mfd/pcf50633/core.h
index ad411a78870c..50d4a047118d 100644
--- a/include/linux/mfd/pcf50633/core.h
+++ b/include/linux/mfd/pcf50633/core.h
@@ -227,4 +227,11 @@ static inline struct pcf50633 *dev_to_pcf50633(struct device *dev)
         return dev_get_drvdata(dev);
 }
 
+int pcf50633_irq_init(struct pcf50633 *pcf, int irq);
+void pcf50633_irq_free(struct pcf50633 *pcf);
+#ifdef CONFIG_PM
+int pcf50633_irq_suspend(struct pcf50633 *pcf);
+int pcf50633_irq_resume(struct pcf50633 *pcf);
+#endif
+
 #endif
diff --git a/include/linux/mfd/pm8xxx/core.h b/include/linux/mfd/pm8xxx/core.h
new file mode 100644
index 000000000000..bd2f4f64e931
--- /dev/null
+++ b/include/linux/mfd/pm8xxx/core.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/*
+ * Qualcomm PMIC 8xxx driver header file
+ *
+ */
+
+#ifndef __MFD_PM8XXX_CORE_H
+#define __MFD_PM8XXX_CORE_H
+
+#include <linux/mfd/core.h>
+
+struct pm8xxx_drvdata {
+        int     (*pmic_readb) (const struct device *dev, u16 addr, u8 *val);
+        int     (*pmic_writeb) (const struct device *dev, u16 addr, u8 val);
+        int     (*pmic_read_buf) (const struct device *dev, u16 addr, u8 *buf,
+                                                                        int n);
+        int     (*pmic_write_buf) (const struct device *dev, u16 addr, u8 *buf,
+                                                                        int n);
+        int     (*pmic_read_irq_stat) (const struct device *dev, int irq);
+        void    *pm_chip_data;
+};
+
+static inline int pm8xxx_readb(const struct device *dev, u16 addr, u8 *val)
+{
+        struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
+
+        if (!dd)
+                return -EINVAL;
+        return dd->pmic_readb(dev, addr, val);
+}
+
+static inline int pm8xxx_writeb(const struct device *dev, u16 addr, u8 val)
+{
+        struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
+
+        if (!dd)
+                return -EINVAL;
+        return dd->pmic_writeb(dev, addr, val);
+}
+
+static inline int pm8xxx_read_buf(const struct device *dev, u16 addr, u8 *buf,
+                                                                        int n)
+{
+        struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
+
+        if (!dd)
+                return -EINVAL;
+        return dd->pmic_read_buf(dev, addr, buf, n);
+}
+
+static inline int pm8xxx_write_buf(const struct device *dev, u16 addr, u8 *buf,
+                                                                        int n)
+{
+        struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
+
+        if (!dd)
+                return -EINVAL;
+        return dd->pmic_write_buf(dev, addr, buf, n);
+}
+
+static inline int pm8xxx_read_irq_stat(const struct device *dev, int irq)
+{
+        struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
+
+        if (!dd)
+                return -EINVAL;
+        return dd->pmic_read_irq_stat(dev, irq);
+}
+
+#endif
diff --git a/include/linux/mfd/pm8xxx/irq.h b/include/linux/mfd/pm8xxx/irq.h
new file mode 100644
index 000000000000..4b21769f4483
--- /dev/null
+++ b/include/linux/mfd/pm8xxx/irq.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/*
+ * Qualcomm PMIC irq 8xxx driver header file
+ *
+ */
+
+#ifndef __MFD_PM8XXX_IRQ_H
+#define __MFD_PM8XXX_IRQ_H
+
+#include <linux/errno.h>
+#include <linux/err.h>
+
+struct pm8xxx_irq_core_data {
+        u32             rev;
+        int             nirqs;
+};
+
+struct pm8xxx_irq_platform_data {
+        int                             irq_base;
+        struct pm8xxx_irq_core_data     irq_cdata;
+        int                             devirq;
+        int                             irq_trigger_flag;
+};
+
+struct pm_irq_chip;
+
+#ifdef CONFIG_MFD_PM8XXX_IRQ
+int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq);
+struct pm_irq_chip * __devinit pm8xxx_irq_init(struct device *dev,
+                                const struct pm8xxx_irq_platform_data *pdata);
+int __devexit pm8xxx_irq_exit(struct pm_irq_chip *chip);
+#else
+static inline int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq)
+{
+        return -ENXIO;
+}
+static inline struct pm_irq_chip * __devinit pm8xxx_irq_init(
+                                const struct device *dev,
+                                const struct pm8xxx_irq_platform_data *pdata)
+{
+        return ERR_PTR(-ENXIO);
+}
+static inline int __devexit pm8xxx_irq_exit(struct pm_irq_chip *chip)
+{
+        return -ENXIO;
+}
+#endif /* CONFIG_MFD_PM8XXX_IRQ */
+#endif /* __MFD_PM8XXX_IRQ_H */
diff --git a/include/linux/mfd/pm8xxx/pm8921.h b/include/linux/mfd/pm8xxx/pm8921.h
new file mode 100644
index 000000000000..d5517fd32d1b
--- /dev/null
+++ b/include/linux/mfd/pm8xxx/pm8921.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/*
+ * Qualcomm PMIC 8921 driver header file
+ *
+ */
+
+#ifndef __MFD_PM8921_H
+#define __MFD_PM8921_H
+
+#include <linux/device.h>
+#include <linux/mfd/pm8xxx/irq.h>
+
+#define PM8921_NR_IRQS          256
+
+struct pm8921_platform_data {
+        int                                     irq_base;
+        struct pm8xxx_irq_platform_data         *irq_pdata;
+};
+
+#endif
diff --git a/include/linux/mfd/sh_mobile_sdhi.h b/include/linux/mfd/sh_mobile_sdhi.h
deleted file mode 100644
index 49067802a6d7..000000000000
--- a/include/linux/mfd/sh_mobile_sdhi.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef __SH_MOBILE_SDHI_H__
-#define __SH_MOBILE_SDHI_H__
-
-#include <linux/types.h>
-
-struct sh_mobile_sdhi_info {
-        int dma_slave_tx;
-        int dma_slave_rx;
-        unsigned long tmio_flags;
-        u32 tmio_ocr_mask;      /* available MMC voltages */
-        void (*set_pwr)(struct platform_device *pdev, int state);
-};
-
-#endif /* __SH_MOBILE_SDHI_H__ */
diff --git a/include/linux/mfd/stmpe.h b/include/linux/mfd/stmpe.h
index 39ca7588659b..e762c270d8d4 100644
--- a/include/linux/mfd/stmpe.h
+++ b/include/linux/mfd/stmpe.h
@@ -112,13 +112,19 @@ struct stmpe_keypad_platform_data {
         bool no_autorepeat;
 };
 
+#define STMPE_GPIO_NOREQ_811_TOUCH      (0xf0)
+
 /**
  * struct stmpe_gpio_platform_data - STMPE GPIO platform data
  * @gpio_base: first gpio number assigned.  A maximum of
  *             %STMPE_NR_GPIOS GPIOs will be allocated.
+ * @norequest_mask: bitmask specifying which GPIOs should _not_ be
+ *                  requestable due to different usage (e.g. touch, keypad)
+ *                  STMPE_GPIO_NOREQ_* macros can be used here.
  */
 struct stmpe_gpio_platform_data {
         int gpio_base;
+        unsigned norequest_mask;
         void (*setup)(struct stmpe *stmpe, unsigned gpio_base);
         void (*remove)(struct stmpe *stmpe, unsigned gpio_base);
 };
diff --git a/include/linux/mfd/tc35892.h b/include/linux/mfd/tc35892.h
deleted file mode 100644
index e47f770d3068..000000000000
--- a/include/linux/mfd/tc35892.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License Terms: GNU General Public License, version 2
- */
-
-#ifndef __LINUX_MFD_TC35892_H
-#define __LINUX_MFD_TC35892_H
-
-#include <linux/device.h>
-
-#define TC35892_RSTCTRL_IRQRST  (1 << 4)
-#define TC35892_RSTCTRL_TIMRST  (1 << 3)
-#define TC35892_RSTCTRL_ROTRST  (1 << 2)
-#define TC35892_RSTCTRL_KBDRST  (1 << 1)
-#define TC35892_RSTCTRL_GPIRST  (1 << 0)
-
-#define TC35892_IRQST           0x91
-
-#define TC35892_MANFCODE_MAGIC  0x03
-#define TC35892_MANFCODE        0x80
-#define TC35892_VERSION         0x81
-#define TC35892_IOCFG           0xA7
-
-#define TC35892_CLKMODE         0x88
-#define TC35892_CLKCFG          0x89
-#define TC35892_CLKEN           0x8A
-
-#define TC35892_RSTCTRL         0x82
-#define TC35892_EXTRSTN         0x83
-#define TC35892_RSTINTCLR       0x84
-
-#define TC35892_GPIOIS0         0xC9
-#define TC35892_GPIOIS1         0xCA
-#define TC35892_GPIOIS2         0xCB
-#define TC35892_GPIOIBE0        0xCC
-#define TC35892_GPIOIBE1        0xCD
-#define TC35892_GPIOIBE2        0xCE
-#define TC35892_GPIOIEV0        0xCF
-#define TC35892_GPIOIEV1        0xD0
-#define TC35892_GPIOIEV2        0xD1
-#define TC35892_GPIOIE0         0xD2
-#define TC35892_GPIOIE1         0xD3
-#define TC35892_GPIOIE2         0xD4
-#define TC35892_GPIORIS0        0xD6
-#define TC35892_GPIORIS1        0xD7
-#define TC35892_GPIORIS2        0xD8
-#define TC35892_GPIOMIS0        0xD9
-#define TC35892_GPIOMIS1        0xDA
-#define TC35892_GPIOMIS2        0xDB
-#define TC35892_GPIOIC0         0xDC
-#define TC35892_GPIOIC1         0xDD
-#define TC35892_GPIOIC2         0xDE
-
-#define TC35892_GPIODATA0       0xC0
-#define TC35892_GPIOMASK0       0xc1
-#define TC35892_GPIODATA1       0xC2
-#define TC35892_GPIOMASK1       0xc3
-#define TC35892_GPIODATA2       0xC4
-#define TC35892_GPIOMASK2       0xC5
-
-#define TC35892_GPIODIR0        0xC6
-#define TC35892_GPIODIR1        0xC7
-#define TC35892_GPIODIR2        0xC8
-
-#define TC35892_GPIOSYNC0       0xE6
-#define TC35892_GPIOSYNC1       0xE7
-#define TC35892_GPIOSYNC2       0xE8
-
-#define TC35892_GPIOWAKE0       0xE9
-#define TC35892_GPIOWAKE1       0xEA
-#define TC35892_GPIOWAKE2       0xEB
-
-#define TC35892_GPIOODM0        0xE0
-#define TC35892_GPIOODE0        0xE1
-#define TC35892_GPIOODM1        0xE2
-#define TC35892_GPIOODE1        0xE3
-#define TC35892_GPIOODM2        0xE4
-#define TC35892_GPIOODE2        0xE5
-
-#define TC35892_INT_GPIIRQ      0
-#define TC35892_INT_TI0IRQ      1
-#define TC35892_INT_TI1IRQ      2
-#define TC35892_INT_TI2IRQ      3
-#define TC35892_INT_ROTIRQ      5
-#define TC35892_INT_KBDIRQ      6
-#define TC35892_INT_PORIRQ      7
-
-#define TC35892_NR_INTERNAL_IRQS        8
-#define TC35892_INT_GPIO(x)     (TC35892_NR_INTERNAL_IRQS + (x))
-
-struct tc35892 {
-        struct mutex lock;
-        struct device *dev;
-        struct i2c_client *i2c;
-
-        int irq_base;
-        int num_gpio;
-        struct tc35892_platform_data *pdata;
-};
-
-extern int tc35892_reg_write(struct tc35892 *tc35892, u8 reg, u8 data);
-extern int tc35892_reg_read(struct tc35892 *tc35892, u8 reg);
-extern int tc35892_block_read(struct tc35892 *tc35892, u8 reg, u8 length,
-                              u8 *values);
-extern int tc35892_block_write(struct tc35892 *tc35892, u8 reg, u8 length,
-                               const u8 *values);
-extern int tc35892_set_bits(struct tc35892 *tc35892, u8 reg, u8 mask, u8 val);
-
-/**
- * struct tc35892_gpio_platform_data - TC35892 GPIO platform data
- * @gpio_base: first gpio number assigned to TC35892.  A maximum of
- *             %TC35892_NR_GPIOS GPIOs will be allocated.
- */
-struct tc35892_gpio_platform_data {
-        int gpio_base;
-};
-
-/**
- * struct tc35892_platform_data - TC35892 platform data
- * @irq_base: base IRQ number.  %TC35892_NR_IRQS irqs will be used.
- * @gpio: GPIO-specific platform data
- */
-struct tc35892_platform_data {
-        int irq_base;
-        struct tc35892_gpio_platform_data *gpio;
-};
-
-#define TC35892_NR_GPIOS        24
-#define TC35892_NR_IRQS         TC35892_INT_GPIO(TC35892_NR_GPIOS)
-
-#endif
diff --git a/include/linux/mfd/tc3589x.h b/include/linux/mfd/tc3589x.h
new file mode 100644
index 000000000000..16c76e124f9c
--- /dev/null
+++ b/include/linux/mfd/tc3589x.h
@@ -0,0 +1,195 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License, version 2
+ */
+
+#ifndef __LINUX_MFD_TC3589x_H
+#define __LINUX_MFD_TC3589x_H
+
+#include <linux/device.h>
+
+enum tx3589x_block {
+        TC3589x_BLOCK_GPIO        = 1 << 0,
+        TC3589x_BLOCK_KEYPAD      = 1 << 1,
+};
+
+#define TC3589x_RSTCTRL_IRQRST  (1 << 4)
+#define TC3589x_RSTCTRL_TIMRST  (1 << 3)
+#define TC3589x_RSTCTRL_ROTRST  (1 << 2)
+#define TC3589x_RSTCTRL_KBDRST  (1 << 1)
+#define TC3589x_RSTCTRL_GPIRST  (1 << 0)
+
+/* Keyboard Configuration Registers */
+#define TC3589x_KBDSETTLE_REG   0x01
+#define TC3589x_KBDBOUNCE       0x02
+#define TC3589x_KBDSIZE         0x03
+#define TC3589x_KBCFG_LSB       0x04
+#define TC3589x_KBCFG_MSB       0x05
+#define TC3589x_KBDIC           0x08
+#define TC3589x_KBDMSK          0x09
+#define TC3589x_EVTCODE_FIFO    0x10
+#define TC3589x_KBDMFS          0x8F
+
+#define TC3589x_IRQST           0x91
+
+#define TC3589x_MANFCODE_MAGIC  0x03
+#define TC3589x_MANFCODE        0x80
+#define TC3589x_VERSION         0x81
+#define TC3589x_IOCFG           0xA7
+
+#define TC3589x_CLKMODE         0x88
+#define TC3589x_CLKCFG          0x89
+#define TC3589x_CLKEN           0x8A
+
+#define TC3589x_RSTCTRL         0x82
+#define TC3589x_EXTRSTN         0x83
+#define TC3589x_RSTINTCLR       0x84
+
+/* Pull up/down configuration registers */
+#define TC3589x_IOCFG           0xA7
+#define TC3589x_IOPULLCFG0_LSB  0xAA
+#define TC3589x_IOPULLCFG0_MSB  0xAB
+#define TC3589x_IOPULLCFG1_LSB  0xAC
+#define TC3589x_IOPULLCFG1_MSB  0xAD
+#define TC3589x_IOPULLCFG2_LSB  0xAE
+
+#define TC3589x_GPIOIS0         0xC9
+#define TC3589x_GPIOIS1         0xCA
+#define TC3589x_GPIOIS2         0xCB
+#define TC3589x_GPIOIBE0        0xCC
+#define TC3589x_GPIOIBE1        0xCD
+#define TC3589x_GPIOIBE2        0xCE
+#define TC3589x_GPIOIEV0        0xCF
+#define TC3589x_GPIOIEV1        0xD0
+#define TC3589x_GPIOIEV2        0xD1
+#define TC3589x_GPIOIE0         0xD2
+#define TC3589x_GPIOIE1         0xD3
+#define TC3589x_GPIOIE2         0xD4
+#define TC3589x_GPIORIS0        0xD6
+#define TC3589x_GPIORIS1        0xD7
+#define TC3589x_GPIORIS2        0xD8
+#define TC3589x_GPIOMIS0        0xD9
+#define TC3589x_GPIOMIS1        0xDA
+#define TC3589x_GPIOMIS2        0xDB
+#define TC3589x_GPIOIC0         0xDC
+#define TC3589x_GPIOIC1         0xDD
+#define TC3589x_GPIOIC2         0xDE
+
+#define TC3589x_GPIODATA0       0xC0
+#define TC3589x_GPIOMASK0       0xc1
+#define TC3589x_GPIODATA1       0xC2
+#define TC3589x_GPIOMASK1       0xc3
+#define TC3589x_GPIODATA2       0xC4
+#define TC3589x_GPIOMASK2       0xC5
+
+#define TC3589x_GPIODIR0        0xC6
+#define TC3589x_GPIODIR1        0xC7
+#define TC3589x_GPIODIR2        0xC8
+
+#define TC3589x_GPIOSYNC0       0xE6
+#define TC3589x_GPIOSYNC1       0xE7
+#define TC3589x_GPIOSYNC2       0xE8
+
+#define TC3589x_GPIOWAKE0       0xE9
+#define TC3589x_GPIOWAKE1       0xEA
+#define TC3589x_GPIOWAKE2       0xEB
+
+#define TC3589x_GPIOODM0        0xE0
+#define TC3589x_GPIOODE0        0xE1
+#define TC3589x_GPIOODM1        0xE2
+#define TC3589x_GPIOODE1        0xE3
+#define TC3589x_GPIOODM2        0xE4
+#define TC3589x_GPIOODE2        0xE5
+
+#define TC3589x_INT_GPIIRQ      0
+#define TC3589x_INT_TI0IRQ      1
+#define TC3589x_INT_TI1IRQ      2
+#define TC3589x_INT_TI2IRQ      3
+#define TC3589x_INT_ROTIRQ      5
+#define TC3589x_INT_KBDIRQ      6
+#define TC3589x_INT_PORIRQ      7
+
+#define TC3589x_NR_INTERNAL_IRQS        8
+#define TC3589x_INT_GPIO(x)     (TC3589x_NR_INTERNAL_IRQS + (x))
+
+struct tc3589x {
+        struct mutex lock;
+        struct device *dev;
+        struct i2c_client *i2c;
+
+        int irq_base;
+        int num_gpio;
+        struct tc3589x_platform_data *pdata;
+};
+
+extern int tc3589x_reg_write(struct tc3589x *tc3589x, u8 reg, u8 data);
+extern int tc3589x_reg_read(struct tc3589x *tc3589x, u8 reg);
+extern int tc3589x_block_read(struct tc3589x *tc3589x, u8 reg, u8 length,
+                              u8 *values);
+extern int tc3589x_block_write(struct tc3589x *tc3589x, u8 reg, u8 length,
+                               const u8 *values);
+extern int tc3589x_set_bits(struct tc3589x *tc3589x, u8 reg, u8 mask, u8 val);
+
+/*
+ * Keypad related platform specific constants
+ * These values may be modified for fine tuning
+ */
+#define TC_KPD_ROWS             0x8
+#define TC_KPD_COLUMNS          0x8
+#define TC_KPD_DEBOUNCE_PERIOD  0xA3
+#define TC_KPD_SETTLE_TIME      0xA3
+
+/**
+ * struct tc35893_platform_data - data structure for platform specific data
+ * @keymap_data:        matrix scan code table for keycodes
+ * @krow:               mask for available rows, value is 0xFF
+ * @kcol:               mask for available columns, value is 0xFF
+ * @debounce_period:    platform specific debounce time
+ * @settle_time:        platform specific settle down time
+ * @irqtype:            type of interrupt, falling or rising edge
+ * @enable_wakeup:      specifies if keypad event can wake up system from sleep
+ * @no_autorepeat:      flag for auto repetition
+ */
+struct tc3589x_keypad_platform_data {
+        const struct matrix_keymap_data *keymap_data;
+        u8                      krow;
+        u8                      kcol;
+        u8                      debounce_period;
+        u8                      settle_time;
+        unsigned long           irqtype;
+        bool                    enable_wakeup;
+        bool                    no_autorepeat;
+};
+
+/**
+ * struct tc3589x_gpio_platform_data - TC3589x GPIO platform data
+ * @gpio_base: first gpio number assigned to TC3589x.  A maximum of
+ *             %TC3589x_NR_GPIOS GPIOs will be allocated.
+ * @setup: callback for board-specific initialization
+ * @remove: callback for board-specific teardown
+ */
+struct tc3589x_gpio_platform_data {
+        int gpio_base;
+        void (*setup)(struct tc3589x *tc3589x, unsigned gpio_base);
+        void (*remove)(struct tc3589x *tc3589x, unsigned gpio_base);
+};
+
+/**
+ * struct tc3589x_platform_data - TC3589x platform data
+ * @block: bitmask of blocks to enable (use TC3589x_BLOCK_*)
+ * @irq_base: base IRQ number.  %TC3589x_NR_IRQS irqs will be used.
+ * @gpio: GPIO-specific platform data
+ * @keypad: keypad-specific platform data
+ */
+struct tc3589x_platform_data {
+        unsigned int block;
+        int irq_base;
+        struct tc3589x_gpio_platform_data *gpio;
+        const struct tc3589x_keypad_platform_data *keypad;
+};
+
+#define TC3589x_NR_GPIOS        24
+#define TC3589x_NR_IRQS         TC3589x_INT_GPIO(TC3589x_NR_GPIOS)
+
+#endif
diff --git a/include/linux/mfd/ti_ssp.h b/include/linux/mfd/ti_ssp.h
new file mode 100644
index 000000000000..dbb4b43bd20e
--- /dev/null
+++ b/include/linux/mfd/ti_ssp.h
@@ -0,0 +1,93 @@
+/*
+ * Sequencer Serial Port (SSP) driver for Texas Instruments' SoCs
+ *
+ * Copyright (C) 2010 Texas Instruments Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __TI_SSP_H__
+#define __TI_SSP_H__
+
+struct ti_ssp_dev_data {
+        const char      *dev_name;
+        void            *pdata;
+        size_t          pdata_size;
+};
+
+struct ti_ssp_data {
+        unsigned long           out_clock;
+        struct ti_ssp_dev_data  dev_data[2];
+};
+
+struct ti_ssp_spi_data {
+        unsigned long   iosel;
+        int             num_cs;
+        void            (*select)(int cs);
+};
+
+/*
+ * Sequencer port IO pin configuration bits.  These do not correlate 1-1 with
+ * the hardware.  The iosel field in the port data combines iosel1 and iosel2,
+ * and is therefore not a direct map to register space.  It is best to use the
+ * macros below to construct iosel values.
+ *
+ * least significant 16 bits --> iosel1
+ * most significant 16 bits  --> iosel2
+ */
+
+#define SSP_IN                  0x0000
+#define SSP_DATA                0x0001
+#define SSP_CLOCK               0x0002
+#define SSP_CHIPSEL             0x0003
+#define SSP_OUT                 0x0004
+#define SSP_PIN_SEL(pin, v)     ((v) << ((pin) * 3))
+#define SSP_PIN_MASK(pin)       SSP_PIN_SEL(pin, 0x7)
+#define SSP_INPUT_SEL(pin)      ((pin) << 16)
+
+/* Sequencer port config bits */
+#define SSP_EARLY_DIN           BIT(8)
+#define SSP_DELAY_DOUT          BIT(9)
+
+/* Sequence map definitions */
+#define SSP_CLK_HIGH            BIT(0)
+#define SSP_CLK_LOW             0
+#define SSP_DATA_HIGH           BIT(1)
+#define SSP_DATA_LOW            0
+#define SSP_CS_HIGH             BIT(2)
+#define SSP_CS_LOW              0
+#define SSP_OUT_MODE            BIT(3)
+#define SSP_IN_MODE             0
+#define SSP_DATA_REG            BIT(4)
+#define SSP_ADDR_REG            0
+
+#define SSP_OPCODE_DIRECT       ((0x0) << 5)
+#define SSP_OPCODE_TOGGLE       ((0x1) << 5)
+#define SSP_OPCODE_SHIFT        ((0x2) << 5)
+#define SSP_OPCODE_BRANCH0      ((0x4) << 5)
+#define SSP_OPCODE_BRANCH1      ((0x5) << 5)
+#define SSP_OPCODE_BRANCH       ((0x6) << 5)
+#define SSP_OPCODE_STOP         ((0x7) << 5)
+#define SSP_BRANCH(addr)        ((addr) << 8)
+#define SSP_COUNT(cycles)       ((cycles) << 8)
+
+int ti_ssp_raw_read(struct device *dev);
+int ti_ssp_raw_write(struct device *dev, u32 val);
+int ti_ssp_load(struct device *dev, int offs, u32* prog, int len);
+int ti_ssp_run(struct device *dev, u32 pc, u32 input, u32 *output);
+int ti_ssp_set_mode(struct device *dev, int mode);
+int ti_ssp_set_iosel(struct device *dev, u32 iosel);
+
+#endif /* __TI_SSP_H__ */
diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h
index f07425bc3dcd..5a90266c3a5a 100644
--- a/include/linux/mfd/tmio.h
+++ b/include/linux/mfd/tmio.h
@@ -4,6 +4,7 @@
 #include <linux/fb.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
 
 #define tmio_ioread8(addr) readb(addr)
 #define tmio_ioread16(addr) readw(addr)
@@ -52,6 +53,21 @@
 
 /* tmio MMC platform flags */
 #define TMIO_MMC_WRPROTECT_DISABLE      (1 << 0)
+/*
+ * Some controllers can support a 2-byte block size when the bus width
+ * is configured in 4-bit mode.
+ */
+#define TMIO_MMC_BLKSZ_2BYTES           (1 << 1)
+/*
+ * Some controllers can support SDIO IRQ signalling.
+ */
+#define TMIO_MMC_SDIO_IRQ               (1 << 2)
+/*
+ * Some platforms can detect card insertion events with controller powered
+ * down, in which case they have to call tmio_mmc_cd_wakeup() to power up the
+ * controller and report the event to the driver.
+ */
+#define TMIO_MMC_HAS_COLD_CD            (1 << 3)
 
 int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
 int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
@@ -61,6 +77,7 @@ void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state);
 struct tmio_mmc_dma {
         void *chan_priv_tx;
         void *chan_priv_rx;
+        int alignment_shift;
 };
 
 /*
@@ -72,10 +89,21 @@ struct tmio_mmc_data {
         unsigned long                   flags;
         u32                             ocr_mask;       /* available voltages */
         struct tmio_mmc_dma             *dma;
+        struct device                   *dev;
+        bool                            power;
         void (*set_pwr)(struct platform_device *host, int state);
         void (*set_clk_div)(struct platform_device *host, int state);
+        int (*get_cd)(struct platform_device *host);
 };
 
+static inline void tmio_mmc_cd_wakeup(struct tmio_mmc_data *pdata)
+{
+        if (pdata && !pdata->power) {
+                pdata->power = true;
+                pm_runtime_get(pdata->dev);
+        }
+}
+
 /*
  * data for the NAND controller
  */
diff --git a/include/linux/mfd/tps6105x.h b/include/linux/mfd/tps6105x.h
new file mode 100644
index 000000000000..386743dd931c
--- /dev/null
+++ b/include/linux/mfd/tps6105x.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2011 ST-Ericsson SA
+ * Written on behalf of Linaro for ST-Ericsson
+ *
+ * Author: Linus Walleij <linus.walleij@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+#ifndef MFD_TPS6105X_H
+#define MFD_TPS6105X_H
+
+#include <linux/i2c.h>
+#include <linux/regulator/machine.h>
+
+/*
+ * Register definitions to all subdrivers
+ */
+#define TPS6105X_REG_0                  0x00
+#define TPS6105X_REG0_MODE_SHIFT        6
+#define TPS6105X_REG0_MODE_MASK         (0x03<<6)
+/* These defines for both reg0 and reg1 */
+#define TPS6105X_REG0_MODE_SHUTDOWN     0x00
+#define TPS6105X_REG0_MODE_TORCH        0x01
+#define TPS6105X_REG0_MODE_TORCH_FLASH  0x02
+#define TPS6105X_REG0_MODE_VOLTAGE      0x03
+#define TPS6105X_REG0_VOLTAGE_SHIFT     4
+#define TPS6105X_REG0_VOLTAGE_MASK      (3<<4)
+#define TPS6105X_REG0_VOLTAGE_450       0
+#define TPS6105X_REG0_VOLTAGE_500       1
+#define TPS6105X_REG0_VOLTAGE_525       2
+#define TPS6105X_REG0_VOLTAGE_500_2     3
+#define TPS6105X_REG0_DIMMING_SHIFT     3
+#define TPS6105X_REG0_TORCHC_SHIFT      0
+#define TPS6105X_REG0_TORCHC_MASK       (7<<0)
+#define TPS6105X_REG0_TORCHC_0          0x00
+#define TPS6105X_REG0_TORCHC_50         0x01
+#define TPS6105X_REG0_TORCHC_75         0x02
+#define TPS6105X_REG0_TORCHC_100        0x03
+#define TPS6105X_REG0_TORCHC_150        0x04
+#define TPS6105X_REG0_TORCHC_200        0x05
+#define TPS6105X_REG0_TORCHC_250_400    0x06
+#define TPS6105X_REG0_TORCHC_250_500    0x07
+#define TPS6105X_REG_1                  0x01
+#define TPS6105X_REG1_MODE_SHIFT        6
+#define TPS6105X_REG1_MODE_MASK         (0x03<<6)
+#define TPS6105X_REG1_MODE_SHUTDOWN     0x00
+#define TPS6105X_REG1_MODE_TORCH        0x01
+#define TPS6105X_REG1_MODE_TORCH_FLASH  0x02
+#define TPS6105X_REG1_MODE_VOLTAGE      0x03
+#define TPS6105X_REG_2                  0x02
+#define TPS6105X_REG_3                  0x03
+
+/**
+ * enum tps6105x_mode - desired mode for the TPS6105x
+ * @TPS6105X_MODE_SHUTDOWN: this instance is inactive, not used for anything
+ * @TPS61905X_MODE_TORCH: this instance is used as a LED, usually a while
+ *      LED, for example as backlight or flashlight. If this is set, the
+ *      TPS6105X will register to the LED framework
+ * @TPS6105X_MODE_TORCH_FLASH: this instance is used as a flashgun, usually
+ *      in a camera
+ * @TPS6105X_MODE_VOLTAGE: this instance is used as a voltage regulator and
+ *      will register to the regulator framework
+ */
+enum tps6105x_mode {
+        TPS6105X_MODE_SHUTDOWN,
+        TPS6105X_MODE_TORCH,
+        TPS6105X_MODE_TORCH_FLASH,
+        TPS6105X_MODE_VOLTAGE,
+};
+
+/**
+ * struct tps6105x_platform_data - TPS61905x platform data
+ * @mode: what mode this instance shall be operated in,
+ *      this is not selectable at runtime
+ * @regulator_data: initialization data for the voltage
+ *      regulator if used as a voltage source
+ */
+struct tps6105x_platform_data {
+        enum tps6105x_mode mode;
+        struct regulator_init_data *regulator_data;
+};
+
+/**
+ * struct tps6105x - state holder for the TPS6105x drivers
+ * @mutex: mutex to serialize I2C accesses
+ * @i2c_client: corresponding I2C client
+ * @regulator: regulator device if used in voltage mode
+ */
+struct tps6105x {
+        struct tps6105x_platform_data *pdata;
+        struct mutex            lock;
+        struct i2c_client       *client;
+        struct regulator_dev    *regulator;
+};
+
+extern int tps6105x_set(struct tps6105x *tps6105x, u8 reg, u8 value);
+extern int tps6105x_get(struct tps6105x *tps6105x, u8 reg, u8 *buf);
+extern int tps6105x_mask_and_set(struct tps6105x *tps6105x, u8 reg,
+                                 u8 bitmask, u8 bitvalues);
+
+#endif
diff --git a/include/linux/mfd/tps6586x.h b/include/linux/mfd/tps6586x.h
index 772b3ae640af..b6bab1b04e25 100644
--- a/include/linux/mfd/tps6586x.h
+++ b/include/linux/mfd/tps6586x.h
@@ -18,6 +18,36 @@ enum {
         TPS6586X_ID_LDO_RTC,
 };
 
+enum {
+        TPS6586X_INT_PLDO_0,
+        TPS6586X_INT_PLDO_1,
+        TPS6586X_INT_PLDO_2,
+        TPS6586X_INT_PLDO_3,
+        TPS6586X_INT_PLDO_4,
+        TPS6586X_INT_PLDO_5,
+        TPS6586X_INT_PLDO_6,
+        TPS6586X_INT_PLDO_7,
+        TPS6586X_INT_COMP_DET,
+        TPS6586X_INT_ADC,
+        TPS6586X_INT_PLDO_8,
+        TPS6586X_INT_PLDO_9,
+        TPS6586X_INT_PSM_0,
+        TPS6586X_INT_PSM_1,
+        TPS6586X_INT_PSM_2,
+        TPS6586X_INT_PSM_3,
+        TPS6586X_INT_RTC_ALM1,
+        TPS6586X_INT_ACUSB_OVP,
+        TPS6586X_INT_USB_DET,
+        TPS6586X_INT_AC_DET,
+        TPS6586X_INT_BAT_DET,
+        TPS6586X_INT_CHG_STAT,
+        TPS6586X_INT_CHG_TEMP,
+        TPS6586X_INT_PP,
+        TPS6586X_INT_RESUME,
+        TPS6586X_INT_LOW_SYS,
+        TPS6586X_INT_RTC_ALM2,
+};
+
 struct tps6586x_subdev_info {
         int             id;
         const char      *name;
@@ -29,6 +59,7 @@ struct tps6586x_platform_data {
         struct tps6586x_subdev_info *subdevs;
 
         int gpio_base;
+        int irq_base;
 };
 
 /*
diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h
new file mode 100644
index 000000000000..8bb85b930c07
--- /dev/null
+++ b/include/linux/mfd/tps65910.h
@@ -0,0 +1,800 @@
+/*
+ * tps65910.h  --  TI TPS6591x
+ *
+ * Copyright 2010-2011 Texas Instruments Inc.
+ *
+ * Author: Graeme Gregory <gg@slimlogic.co.uk>
+ * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
+ * Author: Arnaud Deconinck <a-deconinck@ti.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#ifndef __LINUX_MFD_TPS65910_H
+#define __LINUX_MFD_TPS65910_H
+
+/* TPS chip id list */
+#define TPS65910                        0
+#define TPS65911                        1
+
+/* TPS regulator type list */
+#define REGULATOR_LDO                   0
+#define REGULATOR_DCDC                  1
+
+/*
+ * List of registers for component TPS65910
+ *
+ */
+
+#define TPS65910_SECONDS                                0x0
+#define TPS65910_MINUTES                                0x1
+#define TPS65910_HOURS                                  0x2
+#define TPS65910_DAYS                                   0x3
+#define TPS65910_MONTHS                                 0x4
+#define TPS65910_YEARS                                  0x5
+#define TPS65910_WEEKS                                  0x6
+#define TPS65910_ALARM_SECONDS                          0x8
+#define TPS65910_ALARM_MINUTES                          0x9
+#define TPS65910_ALARM_HOURS                            0xA
+#define TPS65910_ALARM_DAYS                             0xB
+#define TPS65910_ALARM_MONTHS                           0xC
+#define TPS65910_ALARM_YEARS                            0xD
+#define TPS65910_RTC_CTRL                               0x10
+#define TPS65910_RTC_STATUS                             0x11
+#define TPS65910_RTC_INTERRUPTS                         0x12
+#define TPS65910_RTC_COMP_LSB                           0x13
+#define TPS65910_RTC_COMP_MSB                           0x14
+#define TPS65910_RTC_RES_PROG                           0x15
+#define TPS65910_RTC_RESET_STATUS                       0x16
+#define TPS65910_BCK1                                   0x17
+#define TPS65910_BCK2                                   0x18
+#define TPS65910_BCK3                                   0x19
+#define TPS65910_BCK4                                   0x1A
+#define TPS65910_BCK5                                   0x1B
+#define TPS65910_PUADEN                                 0x1C
+#define TPS65910_REF                                    0x1D
+#define TPS65910_VRTC                                   0x1E
+#define TPS65910_VIO                                    0x20
+#define TPS65910_VDD1                                   0x21
+#define TPS65910_VDD1_OP                                0x22
+#define TPS65910_VDD1_SR                                0x23
+#define TPS65910_VDD2                                   0x24
+#define TPS65910_VDD2_OP                                0x25
+#define TPS65910_VDD2_SR                                0x26
+#define TPS65910_VDD3                                   0x27
+#define TPS65910_VDIG1                                  0x30
+#define TPS65910_VDIG2                                  0x31
+#define TPS65910_VAUX1                                  0x32
+#define TPS65910_VAUX2                                  0x33
+#define TPS65910_VAUX33                                 0x34
+#define TPS65910_VMMC                                   0x35
+#define TPS65910_VPLL                                   0x36
+#define TPS65910_VDAC                                   0x37
+#define TPS65910_THERM                                  0x38
+#define TPS65910_BBCH                                   0x39
+#define TPS65910_DCDCCTRL                               0x3E
+#define TPS65910_DEVCTRL                                0x3F
+#define TPS65910_DEVCTRL2                               0x40
+#define TPS65910_SLEEP_KEEP_LDO_ON                      0x41
+#define TPS65910_SLEEP_KEEP_RES_ON                      0x42
+#define TPS65910_SLEEP_SET_LDO_OFF                      0x43
+#define TPS65910_SLEEP_SET_RES_OFF                      0x44
+#define TPS65910_EN1_LDO_ASS                            0x45
+#define TPS65910_EN1_SMPS_ASS                           0x46
+#define TPS65910_EN2_LDO_ASS                            0x47
+#define TPS65910_EN2_SMPS_ASS                           0x48
+#define TPS65910_EN3_LDO_ASS                            0x49
+#define TPS65910_SPARE                                  0x4A
+#define TPS65910_INT_STS                                0x50
+#define TPS65910_INT_MSK                                0x51
+#define TPS65910_INT_STS2                               0x52
+#define TPS65910_INT_MSK2                               0x53
+#define TPS65910_INT_STS3                               0x54
+#define TPS65910_INT_MSK3                               0x55
+#define TPS65910_GPIO0                                  0x60
+#define TPS65910_GPIO1                                  0x61
+#define TPS65910_GPIO2                                  0x62
+#define TPS65910_GPIO3                                  0x63
+#define TPS65910_GPIO4                                  0x64
+#define TPS65910_GPIO5                                  0x65
+#define TPS65910_GPIO6                                  0x66
+#define TPS65910_GPIO7                                  0x67
+#define TPS65910_GPIO8                                  0x68
+#define TPS65910_JTAGVERNUM                             0x80
+#define TPS65910_MAX_REGISTER                           0x80
+
+/*
+ * List of registers specific to TPS65911
+ */
+#define TPS65911_VDDCTRL                                0x27
+#define TPS65911_VDDCTRL_OP                             0x28
+#define TPS65911_VDDCTRL_SR                             0x29
+#define TPS65911_LDO1                                   0x30
+#define TPS65911_LDO2                                   0x31
+#define TPS65911_LDO5                                   0x32
+#define TPS65911_LDO8                                   0x33
+#define TPS65911_LDO7                                   0x34
+#define TPS65911_LDO6                                   0x35
+#define TPS65911_LDO4                                   0x36
+#define TPS65911_LDO3                                   0x37
+#define TPS65911_VMBCH                                  0x6A
+#define TPS65911_VMBCH2                                 0x6B
+
+/*
+ * List of register bitfields for component TPS65910
+ *
+ */
+
+
+/*Register BCK1  (0x80) register.RegisterDescription */
+#define BCK1_BCKUP_MASK                                 0xFF
+#define BCK1_BCKUP_SHIFT                                0
+
+
+/*Register BCK2  (0x80) register.RegisterDescription */
+#define BCK2_BCKUP_MASK                                 0xFF
+#define BCK2_BCKUP_SHIFT                                0
+
+
+/*Register BCK3  (0x80) register.RegisterDescription */
+#define BCK3_BCKUP_MASK                                 0xFF
+#define BCK3_BCKUP_SHIFT                                0
+
+
+/*Register BCK4  (0x80) register.RegisterDescription */
+#define BCK4_BCKUP_MASK                                 0xFF
+#define BCK4_BCKUP_SHIFT                                0
+
+
+/*Register BCK5  (0x80) register.RegisterDescription */
+#define BCK5_BCKUP_MASK                                 0xFF
+#define BCK5_BCKUP_SHIFT                                0
+
+
+/*Register PUADEN  (0x80) register.RegisterDescription */
+#define PUADEN_EN3P_MASK                                0x80
+#define PUADEN_EN3P_SHIFT                               7
+#define PUADEN_I2CCTLP_MASK                             0x40
+#define PUADEN_I2CCTLP_SHIFT                            6
+#define PUADEN_I2CSRP_MASK                              0x20
+#define PUADEN_I2CSRP_SHIFT                             5
+#define PUADEN_PWRONP_MASK                              0x10
+#define PUADEN_PWRONP_SHIFT                             4
+#define PUADEN_SLEEPP_MASK                              0x08
+#define PUADEN_SLEEPP_SHIFT                             3
+#define PUADEN_PWRHOLDP_MASK                            0x04
+#define PUADEN_PWRHOLDP_SHIFT                           2
+#define PUADEN_BOOT1P_MASK                              0x02
+#define PUADEN_BOOT1P_SHIFT                             1
+#define PUADEN_BOOT0P_MASK                              0x01
+#define PUADEN_BOOT0P_SHIFT                             0
+
+
+/*Register REF  (0x80) register.RegisterDescription */
+#define REF_VMBCH_SEL_MASK                              0x0C
+#define REF_VMBCH_SEL_SHIFT                             2
+#define REF_ST_MASK                                     0x03
+#define REF_ST_SHIFT                                    0
+
+
+/*Register VRTC  (0x80) register.RegisterDescription */
+#define VRTC_VRTC_OFFMASK_MASK                          0x08
+#define VRTC_VRTC_OFFMASK_SHIFT                         3
+#define VRTC_ST_MASK                                    0x03
+#define VRTC_ST_SHIFT                                   0
+
+
+/*Register VIO  (0x80) register.RegisterDescription */
+#define VIO_ILMAX_MASK                                  0xC0
+#define VIO_ILMAX_SHIFT                                 6
+#define VIO_SEL_MASK                                    0x0C
+#define VIO_SEL_SHIFT                                   2
+#define VIO_ST_MASK                                     0x03
+#define VIO_ST_SHIFT                                    0
+
+
+/*Register VDD1  (0x80) register.RegisterDescription */
+#define VDD1_VGAIN_SEL_MASK                             0xC0
+#define VDD1_VGAIN_SEL_SHIFT                            6
+#define VDD1_ILMAX_MASK                                 0x20
+#define VDD1_ILMAX_SHIFT                                5
+#define VDD1_TSTEP_MASK                                 0x1C
+#define VDD1_TSTEP_SHIFT                                2
+#define VDD1_ST_MASK                                    0x03
+#define VDD1_ST_SHIFT                                   0
+
+
+/*Register VDD1_OP  (0x80) register.RegisterDescription */
+#define VDD1_OP_CMD_MASK                                0x80
+#define VDD1_OP_CMD_SHIFT                               7
+#define VDD1_OP_SEL_MASK                                0x7F
+#define VDD1_OP_SEL_SHIFT                               0
+
+
+/*Register VDD1_SR  (0x80) register.RegisterDescription */
+#define VDD1_SR_SEL_MASK                                0x7F
+#define VDD1_SR_SEL_SHIFT                               0
+
+
+/*Register VDD2  (0x80) register.RegisterDescription */
+#define VDD2_VGAIN_SEL_MASK                             0xC0
+#define VDD2_VGAIN_SEL_SHIFT                            6
+#define VDD2_ILMAX_MASK                                 0x20
+#define VDD2_ILMAX_SHIFT                                5
+#define VDD2_TSTEP_MASK                                 0x1C
+#define VDD2_TSTEP_SHIFT                                2
+#define VDD2_ST_MASK                                    0x03
+#define VDD2_ST_SHIFT                                   0
+
+
+/*Register VDD2_OP  (0x80) register.RegisterDescription */
+#define VDD2_OP_CMD_MASK                                0x80
+#define VDD2_OP_CMD_SHIFT                               7
+#define VDD2_OP_SEL_MASK                                0x7F
+#define VDD2_OP_SEL_SHIFT                               0
+
+/*Register VDD2_SR  (0x80) register.RegisterDescription */
+#define VDD2_SR_SEL_MASK                                0x7F
+#define VDD2_SR_SEL_SHIFT                               0
+
+
+/*Registers VDD1, VDD2 voltage values definitions */
+#define VDD1_2_NUM_VOLTS                                73
+#define VDD1_2_MIN_VOLT                                 6000
+#define VDD1_2_OFFSET                                   125
+
+
+/*Register VDD3  (0x80) register.RegisterDescription */
+#define VDD3_CKINEN_MASK                                0x04
+#define VDD3_CKINEN_SHIFT                               2
+#define VDD3_ST_MASK                                    0x03
+#define VDD3_ST_SHIFT                                   0
+#define VDDCTRL_MIN_VOLT                                6000
+#define VDDCTRL_OFFSET                                  125
+
+/*Registers VDIG (0x80) to VDAC register.RegisterDescription */
+#define LDO_SEL_MASK                                    0x0C
+#define LDO_SEL_SHIFT                                   2
+#define LDO_ST_MASK                                     0x03
+#define LDO_ST_SHIFT                                    0
+#define LDO_ST_ON_BIT                                   0x01
+#define LDO_ST_MODE_BIT                                 0x02    
+
+
+/* Registers LDO1 to LDO8 in tps65910 */
+#define LDO1_SEL_MASK                                   0xFC
+#define LDO3_SEL_MASK                                   0x7C
+#define LDO_MIN_VOLT                                    1000
+#define LDO_MAX_VOLT                                    3300;
+
+
+/*Register VDIG1  (0x80) register.RegisterDescription */
+#define VDIG1_SEL_MASK                                  0x0C
+#define VDIG1_SEL_SHIFT                                 2
+#define VDIG1_ST_MASK                                   0x03
+#define VDIG1_ST_SHIFT                                  0
+
+
+/*Register VDIG2  (0x80) register.RegisterDescription */
+#define VDIG2_SEL_MASK                                  0x0C
+#define VDIG2_SEL_SHIFT                                 2
+#define VDIG2_ST_MASK                                   0x03
+#define VDIG2_ST_SHIFT                                  0
+
+
+/*Register VAUX1  (0x80) register.RegisterDescription */
+#define VAUX1_SEL_MASK                                  0x0C
+#define VAUX1_SEL_SHIFT                                 2
+#define VAUX1_ST_MASK                                   0x03
+#define VAUX1_ST_SHIFT                                  0
+
+
+/*Register VAUX2  (0x80) register.RegisterDescription */
+#define VAUX2_SEL_MASK                                  0x0C
+#define VAUX2_SEL_SHIFT                                 2
+#define VAUX2_ST_MASK                                   0x03
+#define VAUX2_ST_SHIFT                                  0
+
+
+/*Register VAUX33  (0x80) register.RegisterDescription */
+#define VAUX33_SEL_MASK                                 0x0C
+#define VAUX33_SEL_SHIFT                                2
+#define VAUX33_ST_MASK                                  0x03
+#define VAUX33_ST_SHIFT                                 0
+
+
+/*Register VMMC  (0x80) register.RegisterDescription */
+#define VMMC_SEL_MASK                                   0x0C
+#define VMMC_SEL_SHIFT                                  2
+#define VMMC_ST_MASK                                    0x03
+#define VMMC_ST_SHIFT                                   0
+
+
+/*Register VPLL  (0x80) register.RegisterDescription */
+#define VPLL_SEL_MASK                                   0x0C
+#define VPLL_SEL_SHIFT                                  2
+#define VPLL_ST_MASK                                    0x03
+#define VPLL_ST_SHIFT                                   0
+
+
+/*Register VDAC  (0x80) register.RegisterDescription */
+#define VDAC_SEL_MASK                                   0x0C
+#define VDAC_SEL_SHIFT                                  2
+#define VDAC_ST_MASK                                    0x03
+#define VDAC_ST_SHIFT                                   0
+
+
+/*Register THERM  (0x80) register.RegisterDescription */
+#define THERM_THERM_HD_MASK                             0x20
+#define THERM_THERM_HD_SHIFT                            5
+#define THERM_THERM_TS_MASK                             0x10
+#define THERM_THERM_TS_SHIFT                            4
+#define THERM_THERM_HDSEL_MASK                          0x0C
+#define THERM_THERM_HDSEL_SHIFT                         2
+#define THERM_RSVD1_MASK                                0x02
+#define THERM_RSVD1_SHIFT                               1
+#define THERM_THERM_STATE_MASK                          0x01
+#define THERM_THERM_STATE_SHIFT                         0
+
+
+/*Register BBCH  (0x80) register.RegisterDescription */
+#define BBCH_BBSEL_MASK                                 0x06
+#define BBCH_BBSEL_SHIFT                                1
+#define BBCH_BBCHEN_MASK                                0x01
+#define BBCH_BBCHEN_SHIFT                               0
+
+
+/*Register DCDCCTRL  (0x80) register.RegisterDescription */
+#define DCDCCTRL_VDD2_PSKIP_MASK                        0x20
+#define DCDCCTRL_VDD2_PSKIP_SHIFT                       5
+#define DCDCCTRL_VDD1_PSKIP_MASK                        0x10
+#define DCDCCTRL_VDD1_PSKIP_SHIFT                       4
+#define DCDCCTRL_VIO_PSKIP_MASK                         0x08
+#define DCDCCTRL_VIO_PSKIP_SHIFT                        3
+#define DCDCCTRL_DCDCCKEXT_MASK                         0x04
+#define DCDCCTRL_DCDCCKEXT_SHIFT                        2
+#define DCDCCTRL_DCDCCKSYNC_MASK                        0x03
+#define DCDCCTRL_DCDCCKSYNC_SHIFT                       0
+
+
+/*Register DEVCTRL  (0x80) register.RegisterDescription */
+#define DEVCTRL_RTC_PWDN_MASK                           0x40
+#define DEVCTRL_RTC_PWDN_SHIFT                          6
+#define DEVCTRL_CK32K_CTRL_MASK                         0x20
+#define DEVCTRL_CK32K_CTRL_SHIFT                        5
+#define DEVCTRL_SR_CTL_I2C_SEL_MASK                     0x10
+#define DEVCTRL_SR_CTL_I2C_SEL_SHIFT                    4
+#define DEVCTRL_DEV_OFF_RST_MASK                        0x08
+#define DEVCTRL_DEV_OFF_RST_SHIFT                       3
+#define DEVCTRL_DEV_ON_MASK                             0x04
+#define DEVCTRL_DEV_ON_SHIFT                            2
+#define DEVCTRL_DEV_SLP_MASK                            0x02
+#define DEVCTRL_DEV_SLP_SHIFT                           1
+#define DEVCTRL_DEV_OFF_MASK                            0x01
+#define DEVCTRL_DEV_OFF_SHIFT                           0
+
+
+/*Register DEVCTRL2  (0x80) register.RegisterDescription */
+#define DEVCTRL2_TSLOT_LENGTH_MASK                      0x30
+#define DEVCTRL2_TSLOT_LENGTH_SHIFT                     4
+#define DEVCTRL2_SLEEPSIG_POL_MASK                      0x08
+#define DEVCTRL2_SLEEPSIG_POL_SHIFT                     3
+#define DEVCTRL2_PWON_LP_OFF_MASK                       0x04
+#define DEVCTRL2_PWON_LP_OFF_SHIFT                      2
+#define DEVCTRL2_PWON_LP_RST_MASK                       0x02
+#define DEVCTRL2_PWON_LP_RST_SHIFT                      1
+#define DEVCTRL2_IT_POL_MASK                            0x01
+#define DEVCTRL2_IT_POL_SHIFT                           0
+
+
+/*Register SLEEP_KEEP_LDO_ON  (0x80) register.RegisterDescription */
+#define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_MASK              0x80
+#define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_SHIFT             7
+#define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_MASK              0x40
+#define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_SHIFT             6
+#define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_MASK            0x20
+#define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_SHIFT           5
+#define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_MASK             0x10
+#define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_SHIFT            4
+#define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_MASK             0x08
+#define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_SHIFT            3
+#define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_MASK             0x04
+#define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_SHIFT            2
+#define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_MASK             0x02
+#define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_SHIFT            1
+#define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_MASK              0x01
+#define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_SHIFT             0
+
+
+/*Register SLEEP_KEEP_RES_ON  (0x80) register.RegisterDescription */
+#define SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK             0x80
+#define SLEEP_KEEP_RES_ON_THERM_KEEPON_SHIFT            7
+#define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK         0x40
+#define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_SHIFT        6
+#define SLEEP_KEEP_RES_ON_VRTC_KEEPON_MASK              0x20
+#define SLEEP_KEEP_RES_ON_VRTC_KEEPON_SHIFT             5
+#define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK             0x10
+#define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_SHIFT            4
+#define SLEEP_KEEP_RES_ON_VDD3_KEEPON_MASK              0x08
+#define SLEEP_KEEP_RES_ON_VDD3_KEEPON_SHIFT             3
+#define SLEEP_KEEP_RES_ON_VDD2_KEEPON_MASK              0x04
+#define SLEEP_KEEP_RES_ON_VDD2_KEEPON_SHIFT             2
+#define SLEEP_KEEP_RES_ON_VDD1_KEEPON_MASK              0x02
+#define SLEEP_KEEP_RES_ON_VDD1_KEEPON_SHIFT             1
+#define SLEEP_KEEP_RES_ON_VIO_KEEPON_MASK               0x01
+#define SLEEP_KEEP_RES_ON_VIO_KEEPON_SHIFT              0
+
+
+/*Register SLEEP_SET_LDO_OFF  (0x80) register.RegisterDescription */
+#define SLEEP_SET_LDO_OFF_VDAC_SETOFF_MASK              0x80
+#define SLEEP_SET_LDO_OFF_VDAC_SETOFF_SHIFT             7
+#define SLEEP_SET_LDO_OFF_VPLL_SETOFF_MASK              0x40
+#define SLEEP_SET_LDO_OFF_VPLL_SETOFF_SHIFT             6
+#define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_MASK            0x20
+#define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_SHIFT           5
+#define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_MASK             0x10
+#define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_SHIFT            4
+#define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_MASK             0x08
+#define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_SHIFT            3
+#define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_MASK             0x04
+#define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_SHIFT            2
+#define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_MASK             0x02
+#define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_SHIFT            1
+#define SLEEP_SET_LDO_OFF_VMMC_SETOFF_MASK              0x01
+#define SLEEP_SET_LDO_OFF_VMMC_SETOFF_SHIFT             0
+
+
+/*Register SLEEP_SET_RES_OFF  (0x80) register.RegisterDescription */
+#define SLEEP_SET_RES_OFF_DEFAULT_VOLT_MASK             0x80
+#define SLEEP_SET_RES_OFF_DEFAULT_VOLT_SHIFT            7
+#define SLEEP_SET_RES_OFF_RSVD_MASK                     0x60
+#define SLEEP_SET_RES_OFF_RSVD_SHIFT                    5
+#define SLEEP_SET_RES_OFF_SPARE_SETOFF_MASK             0x10
+#define SLEEP_SET_RES_OFF_SPARE_SETOFF_SHIFT            4
+#define SLEEP_SET_RES_OFF_VDD3_SETOFF_MASK              0x08
+#define SLEEP_SET_RES_OFF_VDD3_SETOFF_SHIFT             3
+#define SLEEP_SET_RES_OFF_VDD2_SETOFF_MASK              0x04
+#define SLEEP_SET_RES_OFF_VDD2_SETOFF_SHIFT             2
+#define SLEEP_SET_RES_OFF_VDD1_SETOFF_MASK              0x02
+#define SLEEP_SET_RES_OFF_VDD1_SETOFF_SHIFT             1
+#define SLEEP_SET_RES_OFF_VIO_SETOFF_MASK               0x01
+#define SLEEP_SET_RES_OFF_VIO_SETOFF_SHIFT              0
+
+
+/*Register EN1_LDO_ASS  (0x80) register.RegisterDescription */
+#define EN1_LDO_ASS_VDAC_EN1_MASK                       0x80
+#define EN1_LDO_ASS_VDAC_EN1_SHIFT                      7
+#define EN1_LDO_ASS_VPLL_EN1_MASK                       0x40
+#define EN1_LDO_ASS_VPLL_EN1_SHIFT                      6
+#define EN1_LDO_ASS_VAUX33_EN1_MASK                     0x20
+#define EN1_LDO_ASS_VAUX33_EN1_SHIFT                    5
+#define EN1_LDO_ASS_VAUX2_EN1_MASK                      0x10
+#define EN1_LDO_ASS_VAUX2_EN1_SHIFT                     4
+#define EN1_LDO_ASS_VAUX1_EN1_MASK                      0x08
+#define EN1_LDO_ASS_VAUX1_EN1_SHIFT                     3
+#define EN1_LDO_ASS_VDIG2_EN1_MASK                      0x04
+#define EN1_LDO_ASS_VDIG2_EN1_SHIFT                     2
+#define EN1_LDO_ASS_VDIG1_EN1_MASK                      0x02
+#define EN1_LDO_ASS_VDIG1_EN1_SHIFT                     1
+#define EN1_LDO_ASS_VMMC_EN1_MASK                       0x01
+#define EN1_LDO_ASS_VMMC_EN1_SHIFT                      0
+
+
+/*Register EN1_SMPS_ASS  (0x80) register.RegisterDescription */
+#define EN1_SMPS_ASS_RSVD_MASK                          0xE0
+#define EN1_SMPS_ASS_RSVD_SHIFT                         5
+#define EN1_SMPS_ASS_SPARE_EN1_MASK                     0x10
+#define EN1_SMPS_ASS_SPARE_EN1_SHIFT                    4
+#define EN1_SMPS_ASS_VDD3_EN1_MASK                      0x08
+#define EN1_SMPS_ASS_VDD3_EN1_SHIFT                     3
+#define EN1_SMPS_ASS_VDD2_EN1_MASK                      0x04
+#define EN1_SMPS_ASS_VDD2_EN1_SHIFT                     2
+#define EN1_SMPS_ASS_VDD1_EN1_MASK                      0x02
+#define EN1_SMPS_ASS_VDD1_EN1_SHIFT                     1
+#define EN1_SMPS_ASS_VIO_EN1_MASK                       0x01
+#define EN1_SMPS_ASS_VIO_EN1_SHIFT                      0
+
+
+/*Register EN2_LDO_ASS  (0x80) register.RegisterDescription */
+#define EN2_LDO_ASS_VDAC_EN2_MASK                       0x80
+#define EN2_LDO_ASS_VDAC_EN2_SHIFT                      7
+#define EN2_LDO_ASS_VPLL_EN2_MASK                       0x40
+#define EN2_LDO_ASS_VPLL_EN2_SHIFT                      6
+#define EN2_LDO_ASS_VAUX33_EN2_MASK                     0x20
+#define EN2_LDO_ASS_VAUX33_EN2_SHIFT                    5
+#define EN2_LDO_ASS_VAUX2_EN2_MASK                      0x10
+#define EN2_LDO_ASS_VAUX2_EN2_SHIFT                     4
+#define EN2_LDO_ASS_VAUX1_EN2_MASK                      0x08
+#define EN2_LDO_ASS_VAUX1_EN2_SHIFT                     3
+#define EN2_LDO_ASS_VDIG2_EN2_MASK                      0x04
+#define EN2_LDO_ASS_VDIG2_EN2_SHIFT                     2
+#define EN2_LDO_ASS_VDIG1_EN2_MASK                      0x02
+#define EN2_LDO_ASS_VDIG1_EN2_SHIFT                     1
+#define EN2_LDO_ASS_VMMC_EN2_MASK                       0x01
+#define EN2_LDO_ASS_VMMC_EN2_SHIFT                      0
+
+
+/*Register EN2_SMPS_ASS  (0x80) register.RegisterDescription */
+#define EN2_SMPS_ASS_RSVD_MASK                          0xE0
+#define EN2_SMPS_ASS_RSVD_SHIFT                         5
+#define EN2_SMPS_ASS_SPARE_EN2_MASK                     0x10
+#define EN2_SMPS_ASS_SPARE_EN2_SHIFT                    4
+#define EN2_SMPS_ASS_VDD3_EN2_MASK                      0x08
+#define EN2_SMPS_ASS_VDD3_EN2_SHIFT                     3
+#define EN2_SMPS_ASS_VDD2_EN2_MASK                      0x04
+#define EN2_SMPS_ASS_VDD2_EN2_SHIFT                     2
+#define EN2_SMPS_ASS_VDD1_EN2_MASK                      0x02
+#define EN2_SMPS_ASS_VDD1_EN2_SHIFT                     1
+#define EN2_SMPS_ASS_VIO_EN2_MASK                       0x01
+#define EN2_SMPS_ASS_VIO_EN2_SHIFT                      0
+
+
+/*Register EN3_LDO_ASS  (0x80) register.RegisterDescription */
+#define EN3_LDO_ASS_VDAC_EN3_MASK                       0x80
+#define EN3_LDO_ASS_VDAC_EN3_SHIFT                      7
+#define EN3_LDO_ASS_VPLL_EN3_MASK                       0x40
+#define EN3_LDO_ASS_VPLL_EN3_SHIFT                      6
+#define EN3_LDO_ASS_VAUX33_EN3_MASK                     0x20
+#define EN3_LDO_ASS_VAUX33_EN3_SHIFT                    5
+#define EN3_LDO_ASS_VAUX2_EN3_MASK                      0x10
+#define EN3_LDO_ASS_VAUX2_EN3_SHIFT                     4
+#define EN3_LDO_ASS_VAUX1_EN3_MASK                      0x08
+#define EN3_LDO_ASS_VAUX1_EN3_SHIFT                     3
+#define EN3_LDO_ASS_VDIG2_EN3_MASK                      0x04
+#define EN3_LDO_ASS_VDIG2_EN3_SHIFT                     2
+#define EN3_LDO_ASS_VDIG1_EN3_MASK                      0x02
+#define EN3_LDO_ASS_VDIG1_EN3_SHIFT                     1
+#define EN3_LDO_ASS_VMMC_EN3_MASK                       0x01
+#define EN3_LDO_ASS_VMMC_EN3_SHIFT                      0
+
+
+/*Register SPARE  (0x80) register.RegisterDescription */
+#define SPARE_SPARE_MASK                                0xFF
+#define SPARE_SPARE_SHIFT                               0
+
+
+/*Register INT_STS  (0x80) register.RegisterDescription */
+#define INT_STS_RTC_PERIOD_IT_MASK                      0x80
+#define INT_STS_RTC_PERIOD_IT_SHIFT                     7
+#define INT_STS_RTC_ALARM_IT_MASK                       0x40
+#define INT_STS_RTC_ALARM_IT_SHIFT                      6
+#define INT_STS_HOTDIE_IT_MASK                          0x20
+#define INT_STS_HOTDIE_IT_SHIFT                         5
+#define INT_STS_PWRHOLD_IT_MASK                         0x10
+#define INT_STS_PWRHOLD_IT_SHIFT                        4
+#define INT_STS_PWRON_LP_IT_MASK                        0x08
+#define INT_STS_PWRON_LP_IT_SHIFT                       3
+#define INT_STS_PWRON_IT_MASK                           0x04
+#define INT_STS_PWRON_IT_SHIFT                          2
+#define INT_STS_VMBHI_IT_MASK                           0x02
+#define INT_STS_VMBHI_IT_SHIFT                          1
+#define INT_STS_VMBDCH_IT_MASK                          0x01
+#define INT_STS_VMBDCH_IT_SHIFT                         0
+
+
+/*Register INT_MSK  (0x80) register.RegisterDescription */
+#define INT_MSK_RTC_PERIOD_IT_MSK_MASK                  0x80
+#define INT_MSK_RTC_PERIOD_IT_MSK_SHIFT                 7
+#define INT_MSK_RTC_ALARM_IT_MSK_MASK                   0x40
+#define INT_MSK_RTC_ALARM_IT_MSK_SHIFT                  6
+#define INT_MSK_HOTDIE_IT_MSK_MASK                      0x20
+#define INT_MSK_HOTDIE_IT_MSK_SHIFT                     5
+#define INT_MSK_PWRHOLD_IT_MSK_MASK                     0x10
+#define INT_MSK_PWRHOLD_IT_MSK_SHIFT                    4
+#define INT_MSK_PWRON_LP_IT_MSK_MASK                    0x08
+#define INT_MSK_PWRON_LP_IT_MSK_SHIFT                   3
+#define INT_MSK_PWRON_IT_MSK_MASK                       0x04
+#define INT_MSK_PWRON_IT_MSK_SHIFT                      2
+#define INT_MSK_VMBHI_IT_MSK_MASK                       0x02
+#define INT_MSK_VMBHI_IT_MSK_SHIFT                      1
+#define INT_MSK_VMBDCH_IT_MSK_MASK                      0x01
+#define INT_MSK_VMBDCH_IT_MSK_SHIFT                     0
+
+
+/*Register INT_STS2  (0x80) register.RegisterDescription */
+#define INT_STS2_GPIO3_F_IT_MASK                        0x80
+#define INT_STS2_GPIO3_F_IT_SHIFT                       7
+#define INT_STS2_GPIO3_R_IT_MASK                        0x40
+#define INT_STS2_GPIO3_R_IT_SHIFT                       6
+#define INT_STS2_GPIO2_F_IT_MASK                        0x20
+#define INT_STS2_GPIO2_F_IT_SHIFT                       5
+#define INT_STS2_GPIO2_R_IT_MASK                        0x10
+#define INT_STS2_GPIO2_R_IT_SHIFT                       4
+#define INT_STS2_GPIO1_F_IT_MASK                        0x08
+#define INT_STS2_GPIO1_F_IT_SHIFT                       3
+#define INT_STS2_GPIO1_R_IT_MASK                        0x04
+#define INT_STS2_GPIO1_R_IT_SHIFT                       2
+#define INT_STS2_GPIO0_F_IT_MASK                        0x02
+#define INT_STS2_GPIO0_F_IT_SHIFT                       1
+#define INT_STS2_GPIO0_R_IT_MASK                        0x01
+#define INT_STS2_GPIO0_R_IT_SHIFT                       0
+
+
+/*Register INT_MSK2  (0x80) register.RegisterDescription */
+#define INT_MSK2_GPIO3_F_IT_MSK_MASK                    0x80
+#define INT_MSK2_GPIO3_F_IT_MSK_SHIFT                   7
+#define INT_MSK2_GPIO3_R_IT_MSK_MASK                    0x40
+#define INT_MSK2_GPIO3_R_IT_MSK_SHIFT                   6
+#define INT_MSK2_GPIO2_F_IT_MSK_MASK                    0x20
+#define INT_MSK2_GPIO2_F_IT_MSK_SHIFT                   5
+#define INT_MSK2_GPIO2_R_IT_MSK_MASK                    0x10
+#define INT_MSK2_GPIO2_R_IT_MSK_SHIFT                   4
+#define INT_MSK2_GPIO1_F_IT_MSK_MASK                    0x08
+#define INT_MSK2_GPIO1_F_IT_MSK_SHIFT                   3
+#define INT_MSK2_GPIO1_R_IT_MSK_MASK                    0x04
+#define INT_MSK2_GPIO1_R_IT_MSK_SHIFT                   2
+#define INT_MSK2_GPIO0_F_IT_MSK_MASK                    0x02
+#define INT_MSK2_GPIO0_F_IT_MSK_SHIFT                   1
+#define INT_MSK2_GPIO0_R_IT_MSK_MASK                    0x01
+#define INT_MSK2_GPIO0_R_IT_MSK_SHIFT                   0
+
+
+/*Register INT_STS3  (0x80) register.RegisterDescription */
+#define INT_STS3_GPIO5_F_IT_MASK                        0x08
+#define INT_STS3_GPIO5_F_IT_SHIFT                       3
+#define INT_STS3_GPIO5_R_IT_MASK                        0x04
+#define INT_STS3_GPIO5_R_IT_SHIFT                       2
+#define INT_STS3_GPIO4_F_IT_MASK                        0x02
+#define INT_STS3_GPIO4_F_IT_SHIFT                       1
+#define INT_STS3_GPIO4_R_IT_MASK                        0x01
+#define INT_STS3_GPIO4_R_IT_SHIFT                       0
+
+
+/*Register INT_MSK3  (0x80) register.RegisterDescription */
+#define INT_MSK3_GPIO5_F_IT_MSK_MASK                    0x08
+#define INT_MSK3_GPIO5_F_IT_MSK_SHIFT                   3
+#define INT_MSK3_GPIO5_R_IT_MSK_MASK                    0x04
+#define INT_MSK3_GPIO5_R_IT_MSK_SHIFT                   2
+#define INT_MSK3_GPIO4_F_IT_MSK_MASK                    0x02
+#define INT_MSK3_GPIO4_F_IT_MSK_SHIFT                   1
+#define INT_MSK3_GPIO4_R_IT_MSK_MASK                    0x01
+#define INT_MSK3_GPIO4_R_IT_MSK_SHIFT                   0
+
+
+/*Register GPIO  (0x80) register.RegisterDescription */
+#define GPIO_DEB_MASK                           0x10
+#define GPIO_DEB_SHIFT                          4
+#define GPIO_PUEN_MASK                          0x08
+#define GPIO_PUEN_SHIFT                         3
+#define GPIO_CFG_MASK                           0x04
+#define GPIO_CFG_SHIFT                          2
+#define GPIO_STS_MASK                           0x02
+#define GPIO_STS_SHIFT                          1
+#define GPIO_SET_MASK                           0x01
+#define GPIO_SET_SHIFT                          0
+
+
+/*Register JTAGVERNUM  (0x80) register.RegisterDescription */
+#define JTAGVERNUM_VERNUM_MASK                          0x0F
+#define JTAGVERNUM_VERNUM_SHIFT                         0
+
+
+/* Register VDDCTRL (0x27) bit definitions */
+#define VDDCTRL_ST_MASK                                  0x03
+#define VDDCTRL_ST_SHIFT                                 0
+
+
+/*Register VDDCTRL_OP  (0x28) bit definitios */
+#define VDDCTRL_OP_CMD_MASK                              0x80
+#define VDDCTRL_OP_CMD_SHIFT                             7
+#define VDDCTRL_OP_SEL_MASK                              0x7F
+#define VDDCTRL_OP_SEL_SHIFT                             0
+
+
+/*Register VDDCTRL_SR  (0x29) bit definitions */
+#define VDDCTRL_SR_SEL_MASK                              0x7F
+#define VDDCTRL_SR_SEL_SHIFT                             0
+
+
+/* IRQ Definitions */
+#define TPS65910_IRQ_VBAT_VMBDCH                        0
+#define TPS65910_IRQ_VBAT_VMHI                          1
+#define TPS65910_IRQ_PWRON                              2
+#define TPS65910_IRQ_PWRON_LP                           3
+#define TPS65910_IRQ_PWRHOLD                            4
+#define TPS65910_IRQ_HOTDIE                             5
+#define TPS65910_IRQ_RTC_ALARM                          6
+#define TPS65910_IRQ_RTC_PERIOD                         7
+#define TPS65910_IRQ_GPIO_R                             8
+#define TPS65910_IRQ_GPIO_F                             9
+#define TPS65910_NUM_IRQ                                10
+
+#define TPS65911_IRQ_VBAT_VMBDCH                        0
+#define TPS65911_IRQ_VBAT_VMBDCH2L                      1
+#define TPS65911_IRQ_VBAT_VMBDCH2H                      2
+#define TPS65911_IRQ_VBAT_VMHI                          3
+#define TPS65911_IRQ_PWRON                              4
+#define TPS65911_IRQ_PWRON_LP                           5
+#define TPS65911_IRQ_PWRHOLD_F                          6
+#define TPS65911_IRQ_PWRHOLD_R                          7
+#define TPS65911_IRQ_HOTDIE                             8
+#define TPS65911_IRQ_RTC_ALARM                          9
+#define TPS65911_IRQ_RTC_PERIOD                         10
+#define TPS65911_IRQ_GPIO0_R                            11
+#define TPS65911_IRQ_GPIO0_F                            12
+#define TPS65911_IRQ_GPIO1_R                            13
+#define TPS65911_IRQ_GPIO1_F                            14
+#define TPS65911_IRQ_GPIO2_R                            15
+#define TPS65911_IRQ_GPIO2_F                            16
+#define TPS65911_IRQ_GPIO3_R                            17
+#define TPS65911_IRQ_GPIO3_F                            18
+#define TPS65911_IRQ_GPIO4_R                            19
+#define TPS65911_IRQ_GPIO4_F                            20
+#define TPS65911_IRQ_GPIO5_R                            21
+#define TPS65911_IRQ_GPIO5_F                            22
+#define TPS65911_IRQ_WTCHDG                             23
+#define TPS65911_IRQ_PWRDN                              24
+
+#define TPS65911_NUM_IRQ                                25
+
+
+/* GPIO Register Definitions */
+#define TPS65910_GPIO_DEB                               BIT(2)
+#define TPS65910_GPIO_PUEN                              BIT(3)
+#define TPS65910_GPIO_CFG                               BIT(2)
+#define TPS65910_GPIO_STS                               BIT(1)
+#define TPS65910_GPIO_SET                               BIT(0)
+
+/**
+ * struct tps65910_board
+ * Board platform data may be used to initialize regulators.
+ */
+
+struct tps65910_board {
+        int gpio_base;
+        int irq;
+        int irq_base;
+        int vmbch_threshold;
+        int vmbch2_threshold;
+        struct regulator_init_data *tps65910_pmic_init_data;
+};
+
+/**
+ * struct tps65910 - tps65910 sub-driver chip access routines
+ */
+
+struct tps65910 {
+        struct device *dev;
+        struct i2c_client *i2c_client;
+        struct mutex io_mutex;
+        unsigned int id;
+        int (*read)(struct tps65910 *tps65910, u8 reg, int size, void *dest);
+        int (*write)(struct tps65910 *tps65910, u8 reg, int size, void *src);
+
+        /* Client devices */
+        struct tps65910_pmic *pmic;
+        struct tps65910_rtc *rtc;
+        struct tps65910_power *power;
+
+        /* GPIO Handling */
+        struct gpio_chip gpio;
+
+        /* IRQ Handling */
+        struct mutex irq_lock;
+        int chip_irq;
+        int irq_base;
+        int irq_num;
+        u32 irq_mask;
+};
+
+struct tps65910_platform_data {
+        int irq;
+        int irq_base;
+};
+
+int tps65910_set_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
+int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
+void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base);
+int tps65910_irq_init(struct tps65910 *tps65910, int irq,
+                struct tps65910_platform_data *pdata);
+
+static inline int tps65910_chip_id(struct tps65910 *tps65910)
+{
+        return tps65910->id;
+}
+
+#endif /*  __LINUX_MFD_TPS65910_H */
diff --git a/include/linux/mfd/twl4030-codec.h b/include/linux/mfd/twl4030-codec.h
index 2ec317c68e59..5cc16bbd1da1 100644
--- a/include/linux/mfd/twl4030-codec.h
+++ b/include/linux/mfd/twl4030-codec.h
@@ -1,7 +1,7 @@
 /*
  * MFD driver for twl4030 codec submodule
  *
- * Author:      Peter Ujfalusi <peter.ujfalusi@nokia.com>
+ * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
  *
  * Copyright:   (C) 2009 Nokia Corporation
  *
diff --git a/include/linux/mfd/wl1273-core.h b/include/linux/mfd/wl1273-core.h
new file mode 100644
index 000000000000..db2f3f454a1b
--- /dev/null
+++ b/include/linux/mfd/wl1273-core.h
@@ -0,0 +1,290 @@
+/*
+ * include/linux/mfd/wl1273-core.h
+ *
+ * Some definitions for the wl1273 radio receiver/transmitter chip.
+ *
+ * Copyright (C) 2010 Nokia Corporation
+ * Author: Matti J. Aaltonen <matti.j.aaltonen@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ */
+
+#ifndef WL1273_CORE_H
+#define WL1273_CORE_H
+
+#include <linux/i2c.h>
+#include <linux/mfd/core.h>
+
+#define WL1273_FM_DRIVER_NAME   "wl1273-fm"
+#define RX71_FM_I2C_ADDR        0x22
+
+#define WL1273_STEREO_GET               0
+#define WL1273_RSSI_LVL_GET             1
+#define WL1273_IF_COUNT_GET             2
+#define WL1273_FLAG_GET                 3
+#define WL1273_RDS_SYNC_GET             4
+#define WL1273_RDS_DATA_GET             5
+#define WL1273_FREQ_SET                 10
+#define WL1273_AF_FREQ_SET              11
+#define WL1273_MOST_MODE_SET            12
+#define WL1273_MOST_BLEND_SET           13
+#define WL1273_DEMPH_MODE_SET           14
+#define WL1273_SEARCH_LVL_SET           15
+#define WL1273_BAND_SET                 16
+#define WL1273_MUTE_STATUS_SET          17
+#define WL1273_RDS_PAUSE_LVL_SET        18
+#define WL1273_RDS_PAUSE_DUR_SET        19
+#define WL1273_RDS_MEM_SET              20
+#define WL1273_RDS_BLK_B_SET            21
+#define WL1273_RDS_MSK_B_SET            22
+#define WL1273_RDS_PI_MASK_SET          23
+#define WL1273_RDS_PI_SET               24
+#define WL1273_RDS_SYSTEM_SET           25
+#define WL1273_INT_MASK_SET             26
+#define WL1273_SEARCH_DIR_SET           27
+#define WL1273_VOLUME_SET               28
+#define WL1273_AUDIO_ENABLE             29
+#define WL1273_PCM_MODE_SET             30
+#define WL1273_I2S_MODE_CONFIG_SET      31
+#define WL1273_POWER_SET                32
+#define WL1273_INTX_CONFIG_SET          33
+#define WL1273_PULL_EN_SET              34
+#define WL1273_HILO_SET                 35
+#define WL1273_SWITCH2FREF              36
+#define WL1273_FREQ_DRIFT_REPORT        37
+
+#define WL1273_PCE_GET                  40
+#define WL1273_FIRM_VER_GET             41
+#define WL1273_ASIC_VER_GET             42
+#define WL1273_ASIC_ID_GET              43
+#define WL1273_MAN_ID_GET               44
+#define WL1273_TUNER_MODE_SET           45
+#define WL1273_STOP_SEARCH              46
+#define WL1273_RDS_CNTRL_SET            47
+
+#define WL1273_WRITE_HARDWARE_REG       100
+#define WL1273_CODE_DOWNLOAD            101
+#define WL1273_RESET                    102
+
+#define WL1273_FM_POWER_MODE            254
+#define WL1273_FM_INTERRUPT             255
+
+/* Transmitter API */
+
+#define WL1273_CHANL_SET                        55
+#define WL1273_SCAN_SPACING_SET                 56
+#define WL1273_REF_SET                          57
+#define WL1273_POWER_ENB_SET                    90
+#define WL1273_POWER_ATT_SET                    58
+#define WL1273_POWER_LEV_SET                    59
+#define WL1273_AUDIO_DEV_SET                    60
+#define WL1273_PILOT_DEV_SET                    61
+#define WL1273_RDS_DEV_SET                      62
+#define WL1273_PUPD_SET                         91
+#define WL1273_AUDIO_IO_SET                     63
+#define WL1273_PREMPH_SET                       64
+#define WL1273_MONO_SET                         66
+#define WL1273_MUTE                             92
+#define WL1273_MPX_LMT_ENABLE                   67
+#define WL1273_PI_SET                           93
+#define WL1273_ECC_SET                          69
+#define WL1273_PTY                              70
+#define WL1273_AF                               71
+#define WL1273_DISPLAY_MODE                     74
+#define WL1273_RDS_REP_SET                      77
+#define WL1273_RDS_CONFIG_DATA_SET              98
+#define WL1273_RDS_DATA_SET                     99
+#define WL1273_RDS_DATA_ENB                     94
+#define WL1273_TA_SET                           78
+#define WL1273_TP_SET                           79
+#define WL1273_DI_SET                           80
+#define WL1273_MS_SET                           81
+#define WL1273_PS_SCROLL_SPEED                  82
+#define WL1273_TX_AUDIO_LEVEL_TEST              96
+#define WL1273_TX_AUDIO_LEVEL_TEST_THRESHOLD    73
+#define WL1273_TX_AUDIO_INPUT_LEVEL_RANGE_SET   54
+#define WL1273_RX_ANTENNA_SELECT                87
+#define WL1273_I2C_DEV_ADDR_SET                 86
+#define WL1273_REF_ERR_CALIB_PARAM_SET          88
+#define WL1273_REF_ERR_CALIB_PERIODICITY_SET    89
+#define WL1273_SOC_INT_TRIGGER                  52
+#define WL1273_SOC_AUDIO_PATH_SET               83
+#define WL1273_SOC_PCMI_OVERRIDE                84
+#define WL1273_SOC_I2S_OVERRIDE                 85
+#define WL1273_RSSI_BLOCK_SCAN_FREQ_SET         95
+#define WL1273_RSSI_BLOCK_SCAN_START            97
+#define WL1273_RSSI_BLOCK_SCAN_DATA_GET         5
+#define WL1273_READ_FMANT_TUNE_VALUE            104
+
+#define WL1273_RDS_OFF          0
+#define WL1273_RDS_ON           1
+#define WL1273_RDS_RESET        2
+
+#define WL1273_AUDIO_DIGITAL    0
+#define WL1273_AUDIO_ANALOG     1
+
+#define WL1273_MODE_RX          BIT(0)
+#define WL1273_MODE_TX          BIT(1)
+#define WL1273_MODE_OFF         BIT(2)
+#define WL1273_MODE_SUSPENDED   BIT(3)
+
+#define WL1273_RADIO_CHILD      BIT(0)
+#define WL1273_CODEC_CHILD      BIT(1)
+
+#define WL1273_RX_MONO          1
+#define WL1273_RX_STEREO        0
+#define WL1273_TX_MONO          0
+#define WL1273_TX_STEREO        1
+
+#define WL1273_MAX_VOLUME       0xffff
+#define WL1273_DEFAULT_VOLUME   0x78b8
+
+/* I2S protocol, left channel first, data width 16 bits */
+#define WL1273_PCM_DEF_MODE             0x00
+
+/* Rx */
+#define WL1273_AUDIO_ENABLE_I2S         BIT(0)
+#define WL1273_AUDIO_ENABLE_ANALOG      BIT(1)
+
+/* Tx */
+#define WL1273_AUDIO_IO_SET_ANALOG      0
+#define WL1273_AUDIO_IO_SET_I2S         1
+
+#define WL1273_PUPD_SET_OFF             0x00
+#define WL1273_PUPD_SET_ON              0x01
+#define WL1273_PUPD_SET_RETENTION       0x10
+
+/* I2S mode */
+#define WL1273_IS2_WIDTH_32     0x0
+#define WL1273_IS2_WIDTH_40     0x1
+#define WL1273_IS2_WIDTH_22_23  0x2
+#define WL1273_IS2_WIDTH_23_22  0x3
+#define WL1273_IS2_WIDTH_48     0x4
+#define WL1273_IS2_WIDTH_50     0x5
+#define WL1273_IS2_WIDTH_60     0x6
+#define WL1273_IS2_WIDTH_64     0x7
+#define WL1273_IS2_WIDTH_80     0x8
+#define WL1273_IS2_WIDTH_96     0x9
+#define WL1273_IS2_WIDTH_128    0xa
+#define WL1273_IS2_WIDTH        0xf
+
+#define WL1273_IS2_FORMAT_STD   (0x0 << 4)
+#define WL1273_IS2_FORMAT_LEFT  (0x1 << 4)
+#define WL1273_IS2_FORMAT_RIGHT (0x2 << 4)
+#define WL1273_IS2_FORMAT_USER  (0x3 << 4)
+
+#define WL1273_IS2_MASTER       (0x0 << 6)
+#define WL1273_IS2_SLAVEW       (0x1 << 6)
+
+#define WL1273_IS2_TRI_AFTER_SENDING    (0x0 << 7)
+#define WL1273_IS2_TRI_ALWAYS_ACTIVE    (0x1 << 7)
+
+#define WL1273_IS2_SDOWS_RR     (0x0 << 8)
+#define WL1273_IS2_SDOWS_RF     (0x1 << 8)
+#define WL1273_IS2_SDOWS_FR     (0x2 << 8)
+#define WL1273_IS2_SDOWS_FF     (0x3 << 8)
+
+#define WL1273_IS2_TRI_OPT      (0x0 << 10)
+#define WL1273_IS2_TRI_ALWAYS   (0x1 << 10)
+
+#define WL1273_IS2_RATE_48K     (0x0 << 12)
+#define WL1273_IS2_RATE_44_1K   (0x1 << 12)
+#define WL1273_IS2_RATE_32K     (0x2 << 12)
+#define WL1273_IS2_RATE_22_05K  (0x4 << 12)
+#define WL1273_IS2_RATE_16K     (0x5 << 12)
+#define WL1273_IS2_RATE_12K     (0x8 << 12)
+#define WL1273_IS2_RATE_11_025  (0x9 << 12)
+#define WL1273_IS2_RATE_8K      (0xa << 12)
+#define WL1273_IS2_RATE         (0xf << 12)
+
+#define WL1273_I2S_DEF_MODE     (WL1273_IS2_WIDTH_32 | \
+                                 WL1273_IS2_FORMAT_STD | \
+                                 WL1273_IS2_MASTER | \
+                                 WL1273_IS2_TRI_AFTER_SENDING | \
+                                 WL1273_IS2_SDOWS_RR | \
+                                 WL1273_IS2_TRI_OPT | \
+                                 WL1273_IS2_RATE_48K)
+
+#define SCHAR_MIN (-128)
+#define SCHAR_MAX 127
+
+#define WL1273_FR_EVENT                 BIT(0)
+#define WL1273_BL_EVENT                 BIT(1)
+#define WL1273_RDS_EVENT                BIT(2)
+#define WL1273_BBLK_EVENT               BIT(3)
+#define WL1273_LSYNC_EVENT              BIT(4)
+#define WL1273_LEV_EVENT                BIT(5)
+#define WL1273_IFFR_EVENT               BIT(6)
+#define WL1273_PI_EVENT                 BIT(7)
+#define WL1273_PD_EVENT                 BIT(8)
+#define WL1273_STIC_EVENT               BIT(9)
+#define WL1273_MAL_EVENT                BIT(10)
+#define WL1273_POW_ENB_EVENT            BIT(11)
+#define WL1273_SCAN_OVER_EVENT          BIT(12)
+#define WL1273_ERROR_EVENT              BIT(13)
+
+#define TUNER_MODE_STOP_SEARCH          0
+#define TUNER_MODE_PRESET               1
+#define TUNER_MODE_AUTO_SEEK            2
+#define TUNER_MODE_AF                   3
+#define TUNER_MODE_AUTO_SEEK_PI         4
+#define TUNER_MODE_AUTO_SEEK_BULK       5
+
+#define RDS_BLOCK_SIZE  3
+
+struct wl1273_fm_platform_data {
+        int (*request_resources) (struct i2c_client *client);
+        void (*free_resources) (void);
+        void (*enable) (void);
+        void (*disable) (void);
+
+        u8 forbidden_modes;
+        unsigned int children;
+};
+
+#define WL1273_FM_CORE_CELLS    2
+
+#define WL1273_BAND_OTHER       0
+#define WL1273_BAND_JAPAN       1
+
+#define WL1273_BAND_JAPAN_LOW   76000
+#define WL1273_BAND_JAPAN_HIGH  90000
+#define WL1273_BAND_OTHER_LOW   87500
+#define WL1273_BAND_OTHER_HIGH  108000
+
+#define WL1273_BAND_TX_LOW      76000
+#define WL1273_BAND_TX_HIGH     108000
+
+struct wl1273_core {
+        struct mfd_cell cells[WL1273_FM_CORE_CELLS];
+        struct wl1273_fm_platform_data *pdata;
+
+        unsigned int mode;
+        unsigned int i2s_mode;
+        unsigned int volume;
+        unsigned int audio_mode;
+        unsigned int channel_number;
+        struct mutex lock; /* for serializing fm radio operations */
+
+        struct i2c_client *client;
+
+        int (*read)(struct wl1273_core *core, u8, u16 *);
+        int (*write)(struct wl1273_core *core, u8, u16);
+        int (*write_data)(struct wl1273_core *core, u8 *, u16);
+        int (*set_audio)(struct wl1273_core *core, unsigned int);
+        int (*set_volume)(struct wl1273_core *core, unsigned int);
+};
+
+#endif  /* ifndef WL1273_CORE_H */
diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h
index eb5bd4e0e03c..0d515ee1c247 100644
--- a/include/linux/mfd/wm831x/core.h
+++ b/include/linux/mfd/wm831x/core.h
@@ -238,6 +238,16 @@ struct regulator_dev;
 
 #define WM831X_NUM_IRQ_REGS 5
 
+enum wm831x_parent {
+        WM8310 = 0x8310,
+        WM8311 = 0x8311,
+        WM8312 = 0x8312,
+        WM8320 = 0x8320,
+        WM8321 = 0x8321,
+        WM8325 = 0x8325,
+        WM8326 = 0x8326,
+};
+
 struct wm831x {
         struct mutex io_lock;
 
@@ -285,33 +295,10 @@ int wm831x_set_bits(struct wm831x *wm831x, unsigned short reg,
 int wm831x_bulk_read(struct wm831x *wm831x, unsigned short reg,
                      int count, u16 *buf);
 
+int wm831x_device_init(struct wm831x *wm831x, unsigned long id, int irq);
+void wm831x_device_exit(struct wm831x *wm831x);
+int wm831x_device_suspend(struct wm831x *wm831x);
 int wm831x_irq_init(struct wm831x *wm831x, int irq);
 void wm831x_irq_exit(struct wm831x *wm831x);
 
-static inline int __must_check wm831x_request_irq(struct wm831x *wm831x,
-                                                  unsigned int irq,
-                                                  irq_handler_t handler,
-                                                  unsigned long flags,
-                                                  const char *name,
-                                                  void *dev)
-{
-        return request_threaded_irq(irq, NULL, handler, flags, name, dev);
-}
-
-static inline void wm831x_free_irq(struct wm831x *wm831x,
-                                   unsigned int irq, void *dev)
-{
-        free_irq(irq, dev);
-}
-
-static inline void wm831x_disable_irq(struct wm831x *wm831x, int irq)
-{
-        disable_irq(irq);
-}
-
-static inline void wm831x_enable_irq(struct wm831x *wm831x, int irq)
-{
-        enable_irq(irq);
-}
-
 #endif
diff --git a/include/linux/mfd/wm831x/pdata.h b/include/linux/mfd/wm831x/pdata.h
index fd322aca33ba..ff42d700293f 100644
--- a/include/linux/mfd/wm831x/pdata.h
+++ b/include/linux/mfd/wm831x/pdata.h
@@ -80,7 +80,10 @@ struct wm831x_touch_pdata {
         int isel;              /** Current for pen down (uA) */
         int rpu;               /** Pen down sensitivity resistor divider */
         int pressure;          /** Report pressure (boolean) */
-        int data_irq;          /** Touch data ready IRQ */
+        unsigned int data_irq; /** Touch data ready IRQ */
+        int data_irqf;         /** IRQ flags for data ready IRQ */
+        unsigned int pd_irq;   /** Touch pendown detect IRQ */
+        int pd_irqf;           /** IRQ flags for pen down IRQ */
 };
 
 enum wm831x_watchdog_action {
@@ -102,14 +105,24 @@ struct wm831x_watchdog_pdata {
 #define WM831X_MAX_LDO    11
 #define WM831X_MAX_ISINK  2
 
+#define WM831X_GPIO_CONFIGURE 0x10000
+#define WM831X_GPIO_NUM 16
+
 struct wm831x_pdata {
+        /** Used to distinguish multiple WM831x chips */
+        int wm831x_num;
+
         /** Called before subdevices are set up */
         int (*pre_init)(struct wm831x *wm831x);
         /** Called after subdevices are set up */
         int (*post_init)(struct wm831x *wm831x);
 
+        /** Put the /IRQ line into CMOS mode */
+        bool irq_cmos;
+
         int irq_base;
         int gpio_base;
+        int gpio_defaults[WM831X_GPIO_NUM];
         struct wm831x_backlight_pdata *backlight;
         struct wm831x_backup_pdata *backup;
         struct wm831x_battery_pdata *battery;
diff --git a/include/linux/mfd/wm8350/audio.h b/include/linux/mfd/wm8350/audio.h
index a95141eafce3..bd581c6fa085 100644
--- a/include/linux/mfd/wm8350/audio.h
+++ b/include/linux/mfd/wm8350/audio.h
@@ -522,9 +522,6 @@
 #define WM8350_MCLK_SEL_PLL_32K                 3
 #define WM8350_MCLK_SEL_MCLK                    5
 
-#define WM8350_MCLK_DIR_OUT                     0
-#define WM8350_MCLK_DIR_IN                      1
-
 /* clock divider id's */
 #define WM8350_ADC_CLKDIV                       0
 #define WM8350_DAC_CLKDIV                       1
diff --git a/include/linux/mfd/wm8350/pmic.h b/include/linux/mfd/wm8350/pmic.h
index e786fe9841ef..579b50ca2e02 100644
--- a/include/linux/mfd/wm8350/pmic.h
+++ b/include/linux/mfd/wm8350/pmic.h
@@ -1,5 +1,5 @@
 /*
- * pmic.h  --  Power Managment Driver for Wolfson WM8350 PMIC
+ * pmic.h  --  Power Management Driver for Wolfson WM8350 PMIC
  *
  * Copyright 2007 Wolfson Microelectronics PLC
  *
diff --git a/include/linux/mfd/wm8994/core.h b/include/linux/mfd/wm8994/core.h
index de79baee4925..f0b69cdae41c 100644
--- a/include/linux/mfd/wm8994/core.h
+++ b/include/linux/mfd/wm8994/core.h
@@ -17,6 +17,11 @@
 
 #include <linux/interrupt.h>
 
+enum wm8994_type {
+        WM8994 = 0,
+        WM8958 = 1,
+};
+
 struct regulator_dev;
 struct regulator_bulk_data;
 
@@ -48,11 +53,13 @@ struct wm8994 {
         struct mutex io_lock;
         struct mutex irq_lock;
 
+        enum wm8994_type type;
+
         struct device *dev;
         int (*read_dev)(struct wm8994 *wm8994, unsigned short reg,
                         int bytes, void *dest);
         int (*write_dev)(struct wm8994 *wm8994, unsigned short reg,
-                         int bytes, void *src);
+                         int bytes, const void *src);
 
         void *control_data;
 
@@ -64,10 +71,12 @@ struct wm8994 {
         u16 irq_masks_cache[WM8994_NUM_IRQ_REGS];
 
         /* Used over suspend/resume */
+        bool suspended;
         u16 ldo_regs[WM8994_NUM_LDO_REGS];
         u16 gpio_regs[WM8994_NUM_GPIO_REGS];
 
         struct regulator_dev *dbvdd;
+        int num_supplies;
         struct regulator_bulk_data *supplies;
 };
 
@@ -79,6 +88,8 @@ int wm8994_set_bits(struct wm8994 *wm8994, unsigned short reg,
                     unsigned short mask, unsigned short val);
 int wm8994_bulk_read(struct wm8994 *wm8994, unsigned short reg,
                      int count, u16 *buf);
+int wm8994_bulk_write(struct wm8994 *wm8994, unsigned short reg,
+                     int count, const u16 *buf);
 
 
 /* Helper to save on boilerplate */
diff --git a/include/linux/mfd/wm8994/pdata.h b/include/linux/mfd/wm8994/pdata.h
index 5c51f367c061..d12f8d635a81 100644
--- a/include/linux/mfd/wm8994/pdata.h
+++ b/include/linux/mfd/wm8994/pdata.h
@@ -29,7 +29,13 @@ struct wm8994_ldo_pdata {
 #define WM8994_CONFIGURE_GPIO 0x8000
 
 #define WM8994_DRC_REGS 5
-#define WM8994_EQ_REGS  19
+#define WM8994_EQ_REGS  20
+#define WM8958_MBC_CUTOFF_REGS 20
+#define WM8958_MBC_COEFF_REGS  48
+#define WM8958_MBC_COMBINED_REGS 56
+#define WM8958_VSS_HPF_REGS 2
+#define WM8958_VSS_REGS 148
+#define WM8958_ENH_EQ_REGS 32
 
 /**
  * DRC configurations are specified with a label and a set of register
@@ -59,6 +65,54 @@ struct wm8994_retune_mobile_cfg {
         u16 regs[WM8994_EQ_REGS];
 };
 
+/**
+ * Multiband compressor configurations are specified with a label and
+ * two sets of values to write.  Configurations are expected to be
+ * generated using the multiband compressor configuration panel in
+ * WISCE - see http://www.wolfsonmicro.com/wisce/
+ */
+struct wm8958_mbc_cfg {
+        const char *name;
+        u16 cutoff_regs[WM8958_MBC_CUTOFF_REGS];
+        u16 coeff_regs[WM8958_MBC_COEFF_REGS];
+
+        /* Coefficient layout when using MBC+VSS firmware */
+        u16 combined_regs[WM8958_MBC_COMBINED_REGS];
+};
+
+/**
+ * VSS HPF configurations are specified with a label and two values to
+ * write.  Configurations are expected to be generated using the
+ * multiband compressor configuration panel in WISCE - see
+ * http://www.wolfsonmicro.com/wisce/
+ */
+struct wm8958_vss_hpf_cfg {
+        const char *name;
+        u16 regs[WM8958_VSS_HPF_REGS];
+};
+
+/**
+ * VSS configurations are specified with a label and array of values
+ * to write.  Configurations are expected to be generated using the
+ * multiband compressor configuration panel in WISCE - see
+ * http://www.wolfsonmicro.com/wisce/
+ */
+struct wm8958_vss_cfg {
+        const char *name;
+        u16 regs[WM8958_VSS_REGS];
+};
+
+/**
+ * Enhanced EQ configurations are specified with a label and array of
+ * values to write.  Configurations are expected to be generated using
+ * the multiband compressor configuration panel in WISCE - see
+ * http://www.wolfsonmicro.com/wisce/
+ */
+struct wm8958_enh_eq_cfg {
+        const char *name;
+        u16 regs[WM8958_ENH_EQ_REGS];
+};
+
 struct wm8994_pdata {
         int gpio_base;
 
@@ -78,6 +132,18 @@ struct wm8994_pdata {
         int num_retune_mobile_cfgs;
         struct wm8994_retune_mobile_cfg *retune_mobile_cfgs;
 
+        int num_mbc_cfgs;
+        struct wm8958_mbc_cfg *mbc_cfgs;
+
+        int num_vss_cfgs;
+        struct wm8958_vss_cfg *vss_cfgs;
+
+        int num_vss_hpf_cfgs;
+        struct wm8958_vss_hpf_cfg *vss_hpf_cfgs;
+
+        int num_enh_eq_cfgs;
+        struct wm8958_enh_eq_cfg *enh_eq_cfgs;
+
         /* LINEOUT can be differential or single ended */
         unsigned int lineout1_diff:1;
         unsigned int lineout2_diff:1;
@@ -86,13 +152,21 @@ struct wm8994_pdata {
         unsigned int lineout1fb:1;
         unsigned int lineout2fb:1;
 
-        /* Microphone biases: 0=0.9*AVDD1 1=0.65*AVVD1 */
+        /* IRQ for microphone detection if brought out directly as a
+         * signal.
+         */
+        int micdet_irq;
+
+        /* WM8994 microphone biases: 0=0.9*AVDD1 1=0.65*AVVD1 */
         unsigned int micbias1_lvl:1;
         unsigned int micbias2_lvl:1;
 
-        /* Jack detect threashold levels, see datasheet for values */
+        /* WM8994 jack detect threashold levels, see datasheet for values */
         unsigned int jd_scthr:2;
         unsigned int jd_thr:2;
+
+        /* WM8958 microphone bias configuration */
+        int micbias[2];
 };
 
 #endif
diff --git a/include/linux/mfd/wm8994/registers.h b/include/linux/mfd/wm8994/registers.h
index 967f62f54159..f3ee84284670 100644
--- a/include/linux/mfd/wm8994/registers.h
+++ b/include/linux/mfd/wm8994/registers.h
@@ -63,13 +63,19 @@
 #define WM8994_MICBIAS                          0x3A
 #define WM8994_LDO_1                            0x3B
 #define WM8994_LDO_2                            0x3C
+#define WM8958_MICBIAS1                         0x3D
+#define WM8958_MICBIAS2                         0x3E
 #define WM8994_CHARGE_PUMP_1                    0x4C
+#define WM8958_CHARGE_PUMP_2                    0x4D
 #define WM8994_CLASS_W_1                        0x51
 #define WM8994_DC_SERVO_1                       0x54
 #define WM8994_DC_SERVO_2                       0x55
 #define WM8994_DC_SERVO_4                       0x57
 #define WM8994_DC_SERVO_READBACK                0x58
 #define WM8994_ANALOGUE_HP_1                    0x60
+#define WM8958_MIC_DETECT_1                     0xD0
+#define WM8958_MIC_DETECT_2                     0xD1
+#define WM8958_MIC_DETECT_3                     0xD2
 #define WM8994_CHIP_REVISION                    0x100
 #define WM8994_CONTROL_INTERFACE                0x101
 #define WM8994_WRITE_SEQUENCER_CTRL_1           0x110
@@ -109,6 +115,10 @@
 #define WM8994_AIF2DAC_LRCLK                    0x315
 #define WM8994_AIF2DAC_DATA                     0x316
 #define WM8994_AIF2ADC_DATA                     0x317
+#define WM8958_AIF3_CONTROL_1                   0x320
+#define WM8958_AIF3_CONTROL_2                   0x321
+#define WM8958_AIF3DAC_DATA                     0x322
+#define WM8958_AIF3ADC_DATA                     0x323
 #define WM8994_AIF1_ADC1_LEFT_VOLUME            0x400
 #define WM8994_AIF1_ADC1_RIGHT_VOLUME           0x401
 #define WM8994_AIF1_DAC1_LEFT_VOLUME            0x402
@@ -242,6 +252,83 @@
 #define WM8994_INTERRUPT_STATUS_2_MASK          0x739
 #define WM8994_INTERRUPT_CONTROL                0x740
 #define WM8994_IRQ_DEBOUNCE                     0x748
+#define WM8958_DSP2_PROGRAM                     0x900
+#define WM8958_DSP2_CONFIG                      0x901
+#define WM8958_DSP2_MAGICNUM                    0xA00
+#define WM8958_DSP2_RELEASEYEAR                 0xA01
+#define WM8958_DSP2_RELEASEMONTHDAY             0xA02
+#define WM8958_DSP2_RELEASETIME                 0xA03
+#define WM8958_DSP2_VERMAJMIN                   0xA04
+#define WM8958_DSP2_VERBUILD                    0xA05
+#define WM8958_DSP2_EXECCONTROL                 0xA0D
+#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1     0x2200
+#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_2     0x2201
+#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C2_1     0x2202
+#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C2_2     0x2203
+#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C3_1     0x2204
+#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C3_2     0x2205
+#define WM8958_MBC_BAND_2_UPPER_CUTOFF_C2_1     0x2206
+#define WM8958_MBC_BAND_2_UPPER_CUTOFF_C2_2     0x2207
+#define WM8958_MBC_BAND_2_UPPER_CUTOFF_C3_1     0x2208
+#define WM8958_MBC_BAND_2_UPPER_CUTOFF_C3_2     0x2209
+#define WM8958_MBC_BAND_2_UPPER_CUTOFF_C1_1     0x220A
+#define WM8958_MBC_BAND_2_UPPER_CUTOFF_C1_2     0x220B
+#define WM8958_MBC_BAND_1_UPPER_CUTOFF_C1_1     0x220C
+#define WM8958_MBC_BAND_1_UPPER_CUTOFF_C1_2     0x220D
+#define WM8958_MBC_BAND_1_UPPER_CUTOFF_C2_1     0x220E
+#define WM8958_MBC_BAND_1_UPPER_CUTOFF_C2_2     0x220F
+#define WM8958_MBC_BAND_1_UPPER_CUTOFF_C3_1     0x2210
+#define WM8958_MBC_BAND_1_UPPER_CUTOFF_C3_2     0x2211
+#define WM8958_MBC_BAND_1_LOWER_CUTOFF_1        0x2212
+#define WM8958_MBC_BAND_1_LOWER_CUTOFF_2        0x2213
+#define WM8958_MBC_BAND_1_K_1                   0x2400
+#define WM8958_MBC_BAND_1_K_2                   0x2401
+#define WM8958_MBC_BAND_1_N1_1                  0x2402
+#define WM8958_MBC_BAND_1_N1_2                  0x2403
+#define WM8958_MBC_BAND_1_N2_1                  0x2404
+#define WM8958_MBC_BAND_1_N2_2                  0x2405
+#define WM8958_MBC_BAND_1_N3_1                  0x2406
+#define WM8958_MBC_BAND_1_N3_2                  0x2407
+#define WM8958_MBC_BAND_1_N4_1                  0x2408
+#define WM8958_MBC_BAND_1_N4_2                  0x2409
+#define WM8958_MBC_BAND_1_N5_1                  0x240A
+#define WM8958_MBC_BAND_1_N5_2                  0x240B
+#define WM8958_MBC_BAND_1_X1_1                  0x240C
+#define WM8958_MBC_BAND_1_X1_2                  0x240D
+#define WM8958_MBC_BAND_1_X2_1                  0x240E
+#define WM8958_MBC_BAND_1_X2_2                  0x240F
+#define WM8958_MBC_BAND_1_X3_1                  0x2410
+#define WM8958_MBC_BAND_1_X3_2                  0x2411
+#define WM8958_MBC_BAND_1_ATTACK_1              0x2412
+#define WM8958_MBC_BAND_1_ATTACK_2              0x2413
+#define WM8958_MBC_BAND_1_DECAY_1               0x2414
+#define WM8958_MBC_BAND_1_DECAY_2               0x2415
+#define WM8958_MBC_BAND_2_K_1                   0x2416
+#define WM8958_MBC_BAND_2_K_2                   0x2417
+#define WM8958_MBC_BAND_2_N1_1                  0x2418
+#define WM8958_MBC_BAND_2_N1_2                  0x2419
+#define WM8958_MBC_BAND_2_N2_1                  0x241A
+#define WM8958_MBC_BAND_2_N2_2                  0x241B
+#define WM8958_MBC_BAND_2_N3_1                  0x241C
+#define WM8958_MBC_BAND_2_N3_2                  0x241D
+#define WM8958_MBC_BAND_2_N4_1                  0x241E
+#define WM8958_MBC_BAND_2_N4_2                  0x241F
+#define WM8958_MBC_BAND_2_N5_1                  0x2420
+#define WM8958_MBC_BAND_2_N5_2                  0x2421
+#define WM8958_MBC_BAND_2_X1_1                  0x2422
+#define WM8958_MBC_BAND_2_X1_2                  0x2423
+#define WM8958_MBC_BAND_2_X2_1                  0x2424
+#define WM8958_MBC_BAND_2_X2_2                  0x2425
+#define WM8958_MBC_BAND_2_X3_1                  0x2426
+#define WM8958_MBC_BAND_2_X3_2                  0x2427
+#define WM8958_MBC_BAND_2_ATTACK_1              0x2428
+#define WM8958_MBC_BAND_2_ATTACK_2              0x2429
+#define WM8958_MBC_BAND_2_DECAY_1               0x242A
+#define WM8958_MBC_BAND_2_DECAY_2               0x242B
+#define WM8958_MBC_B2_PG2_1                     0x242C
+#define WM8958_MBC_B2_PG2_2                     0x242D
+#define WM8958_MBC_B1_PG2_1                     0x242E
+#define WM8958_MBC_B1_PG2_2                     0x242F
 #define WM8994_WRITE_SEQUENCER_0                0x3000
 #define WM8994_WRITE_SEQUENCER_1                0x3001
 #define WM8994_WRITE_SEQUENCER_2                0x3002
@@ -992,6 +1079,12 @@
 /*
  * R6 (0x06) - Power Management (6)
  */
+#define WM8958_AIF3ADC_SRC_MASK                 0x0600  /* AIF3ADC_SRC - [10:9] */
+#define WM8958_AIF3ADC_SRC_SHIFT                     9  /* AIF3ADC_SRC - [10:9] */
+#define WM8958_AIF3ADC_SRC_WIDTH                     2  /* AIF3ADC_SRC - [10:9] */
+#define WM8958_AIF2DAC_SRC_MASK                 0x0180  /* AIF2DAC_SRC - [8:7] */
+#define WM8958_AIF2DAC_SRC_SHIFT                     7  /* AIF2DAC_SRC - [8:7] */
+#define WM8958_AIF2DAC_SRC_WIDTH                     2  /* AIF2DAC_SRC - [8:7] */
 #define WM8994_AIF3_TRI                         0x0020  /* AIF3_TRI */
 #define WM8994_AIF3_TRI_MASK                    0x0020  /* AIF3_TRI */
 #define WM8994_AIF3_TRI_SHIFT                        5  /* AIF3_TRI */
@@ -1836,6 +1929,14 @@
 #define WM8994_CP_ENA_WIDTH                          1  /* CP_ENA */
 
 /*
+ * R77 (0x4D) - Charge Pump (2)
+ */
+#define WM8958_CP_DISCH                         0x8000  /* CP_DISCH */
+#define WM8958_CP_DISCH_MASK                    0x8000  /* CP_DISCH */
+#define WM8958_CP_DISCH_SHIFT                       15  /* CP_DISCH */
+#define WM8958_CP_DISCH_WIDTH                        1  /* CP_DISCH */
+
+/*
  * R81 (0x51) - Class W (1)
  */
 #define WM8994_CP_DYN_SRC_SEL_MASK              0x0300  /* CP_DYN_SRC_SEL - [9:8] */
@@ -1952,6 +2053,46 @@
 #define WM8994_HPOUT1R_DLY_WIDTH                     1  /* HPOUT1R_DLY */
 
 /*
+ * R208 (0xD0) - Mic Detect 1
+ */
+#define WM8958_MICD_BIAS_STARTTIME_MASK         0xF000  /* MICD_BIAS_STARTTIME - [15:12] */
+#define WM8958_MICD_BIAS_STARTTIME_SHIFT            12  /* MICD_BIAS_STARTTIME - [15:12] */
+#define WM8958_MICD_BIAS_STARTTIME_WIDTH             4  /* MICD_BIAS_STARTTIME - [15:12] */
+#define WM8958_MICD_RATE_MASK                   0x0F00  /* MICD_RATE - [11:8] */
+#define WM8958_MICD_RATE_SHIFT                       8  /* MICD_RATE - [11:8] */
+#define WM8958_MICD_RATE_WIDTH                       4  /* MICD_RATE - [11:8] */
+#define WM8958_MICD_DBTIME                      0x0002  /* MICD_DBTIME */
+#define WM8958_MICD_DBTIME_MASK                 0x0002  /* MICD_DBTIME */
+#define WM8958_MICD_DBTIME_SHIFT                     1  /* MICD_DBTIME */
+#define WM8958_MICD_DBTIME_WIDTH                     1  /* MICD_DBTIME */
+#define WM8958_MICD_ENA                         0x0001  /* MICD_ENA */
+#define WM8958_MICD_ENA_MASK                    0x0001  /* MICD_ENA */
+#define WM8958_MICD_ENA_SHIFT                        0  /* MICD_ENA */
+#define WM8958_MICD_ENA_WIDTH                        1  /* MICD_ENA */
+
+/*
+ * R209 (0xD1) - Mic Detect 2
+ */
+#define WM8958_MICD_LVL_SEL_MASK                0x00FF  /* MICD_LVL_SEL - [7:0] */
+#define WM8958_MICD_LVL_SEL_SHIFT                    0  /* MICD_LVL_SEL - [7:0] */
+#define WM8958_MICD_LVL_SEL_WIDTH                    8  /* MICD_LVL_SEL - [7:0] */
+
+/*
+ * R210 (0xD2) - Mic Detect 3
+ */
+#define WM8958_MICD_LVL_MASK                    0x07FC  /* MICD_LVL - [10:2] */
+#define WM8958_MICD_LVL_SHIFT                        2  /* MICD_LVL - [10:2] */
+#define WM8958_MICD_LVL_WIDTH                        9  /* MICD_LVL - [10:2] */
+#define WM8958_MICD_VALID                       0x0002  /* MICD_VALID */
+#define WM8958_MICD_VALID_MASK                  0x0002  /* MICD_VALID */
+#define WM8958_MICD_VALID_SHIFT                      1  /* MICD_VALID */
+#define WM8958_MICD_VALID_WIDTH                      1  /* MICD_VALID */
+#define WM8958_MICD_STS                         0x0001  /* MICD_STS */
+#define WM8958_MICD_STS_MASK                    0x0001  /* MICD_STS */
+#define WM8958_MICD_STS_SHIFT                        0  /* MICD_STS */
+#define WM8958_MICD_STS_WIDTH                        1  /* MICD_STS */
+
+/*
  * R256 (0x100) - Chip Revision
  */
 #define WM8994_CHIP_REV_MASK                    0x000F  /* CHIP_REV - [3:0] */
@@ -2069,6 +2210,14 @@
 /*
  * R520 (0x208) - Clocking (1)
  */
+#define WM8958_DSP2CLK_ENA                      0x4000  /* DSP2CLK_ENA */
+#define WM8958_DSP2CLK_ENA_MASK                 0x4000  /* DSP2CLK_ENA */
+#define WM8958_DSP2CLK_ENA_SHIFT                    14  /* DSP2CLK_ENA */
+#define WM8958_DSP2CLK_ENA_WIDTH                     1  /* DSP2CLK_ENA */
+#define WM8958_DSP2CLK_SRC                      0x1000  /* DSP2CLK_SRC */
+#define WM8958_DSP2CLK_SRC_MASK                 0x1000  /* DSP2CLK_SRC */
+#define WM8958_DSP2CLK_SRC_SHIFT                    12  /* DSP2CLK_SRC */
+#define WM8958_DSP2CLK_SRC_WIDTH                     1  /* DSP2CLK_SRC */
 #define WM8994_TOCLK_ENA                        0x0010  /* TOCLK_ENA */
 #define WM8994_TOCLK_ENA_MASK                   0x0010  /* TOCLK_ENA */
 #define WM8994_TOCLK_ENA_SHIFT                       4  /* TOCLK_ENA */
@@ -2553,6 +2702,63 @@
 #define WM8994_AIF2ADCR_DAT_INV_WIDTH                1  /* AIF2ADCR_DAT_INV */
 
 /*
+ * R800 (0x320) - AIF3 Control (1)
+ */
+#define WM8958_AIF3_LRCLK_INV                   0x0080  /* AIF3_LRCLK_INV */
+#define WM8958_AIF3_LRCLK_INV_MASK              0x0080  /* AIF3_LRCLK_INV */
+#define WM8958_AIF3_LRCLK_INV_SHIFT                  7  /* AIF3_LRCLK_INV */
+#define WM8958_AIF3_LRCLK_INV_WIDTH                  1  /* AIF3_LRCLK_INV */
+#define WM8958_AIF3_WL_MASK                     0x0060  /* AIF3_WL - [6:5] */
+#define WM8958_AIF3_WL_SHIFT                         5  /* AIF3_WL - [6:5] */
+#define WM8958_AIF3_WL_WIDTH                         2  /* AIF3_WL - [6:5] */
+#define WM8958_AIF3_FMT_MASK                    0x0018  /* AIF3_FMT - [4:3] */
+#define WM8958_AIF3_FMT_SHIFT                        3  /* AIF3_FMT - [4:3] */
+#define WM8958_AIF3_FMT_WIDTH                        2  /* AIF3_FMT - [4:3] */
+
+/*
+ * R801 (0x321) - AIF3 Control (2)
+ */
+#define WM8958_AIF3DAC_BOOST_MASK               0x0C00  /* AIF3DAC_BOOST - [11:10] */
+#define WM8958_AIF3DAC_BOOST_SHIFT                  10  /* AIF3DAC_BOOST - [11:10] */
+#define WM8958_AIF3DAC_BOOST_WIDTH                   2  /* AIF3DAC_BOOST - [11:10] */
+#define WM8958_AIF3DAC_COMP                     0x0010  /* AIF3DAC_COMP */
+#define WM8958_AIF3DAC_COMP_MASK                0x0010  /* AIF3DAC_COMP */
+#define WM8958_AIF3DAC_COMP_SHIFT                    4  /* AIF3DAC_COMP */
+#define WM8958_AIF3DAC_COMP_WIDTH                    1  /* AIF3DAC_COMP */
+#define WM8958_AIF3DAC_COMPMODE                 0x0008  /* AIF3DAC_COMPMODE */
+#define WM8958_AIF3DAC_COMPMODE_MASK            0x0008  /* AIF3DAC_COMPMODE */
+#define WM8958_AIF3DAC_COMPMODE_SHIFT                3  /* AIF3DAC_COMPMODE */
+#define WM8958_AIF3DAC_COMPMODE_WIDTH                1  /* AIF3DAC_COMPMODE */
+#define WM8958_AIF3ADC_COMP                     0x0004  /* AIF3ADC_COMP */
+#define WM8958_AIF3ADC_COMP_MASK                0x0004  /* AIF3ADC_COMP */
+#define WM8958_AIF3ADC_COMP_SHIFT                    2  /* AIF3ADC_COMP */
+#define WM8958_AIF3ADC_COMP_WIDTH                    1  /* AIF3ADC_COMP */
+#define WM8958_AIF3ADC_COMPMODE                 0x0002  /* AIF3ADC_COMPMODE */
+#define WM8958_AIF3ADC_COMPMODE_MASK            0x0002  /* AIF3ADC_COMPMODE */
+#define WM8958_AIF3ADC_COMPMODE_SHIFT                1  /* AIF3ADC_COMPMODE */
+#define WM8958_AIF3ADC_COMPMODE_WIDTH                1  /* AIF3ADC_COMPMODE */
+#define WM8958_AIF3_LOOPBACK                    0x0001  /* AIF3_LOOPBACK */
+#define WM8958_AIF3_LOOPBACK_MASK               0x0001  /* AIF3_LOOPBACK */
+#define WM8958_AIF3_LOOPBACK_SHIFT                   0  /* AIF3_LOOPBACK */
+#define WM8958_AIF3_LOOPBACK_WIDTH                   1  /* AIF3_LOOPBACK */
+
+/*
+ * R802 (0x322) - AIF3DAC Data
+ */
+#define WM8958_AIF3DAC_DAT_INV                  0x0001  /* AIF3DAC_DAT_INV */
+#define WM8958_AIF3DAC_DAT_INV_MASK             0x0001  /* AIF3DAC_DAT_INV */
+#define WM8958_AIF3DAC_DAT_INV_SHIFT                 0  /* AIF3DAC_DAT_INV */
+#define WM8958_AIF3DAC_DAT_INV_WIDTH                 1  /* AIF3DAC_DAT_INV */
+
+/*
+ * R803 (0x323) - AIF3ADC Data
+ */
+#define WM8958_AIF3ADC_DAT_INV                  0x0001  /* AIF3ADC_DAT_INV */
+#define WM8958_AIF3ADC_DAT_INV_MASK             0x0001  /* AIF3ADC_DAT_INV */
+#define WM8958_AIF3ADC_DAT_INV_SHIFT                 0  /* AIF3ADC_DAT_INV */
+#define WM8958_AIF3ADC_DAT_INV_WIDTH                 1  /* AIF3ADC_DAT_INV */
+
+/*
  * R1024 (0x400) - AIF1 ADC1 Left Volume
  */
 #define WM8994_AIF1ADC1_VU                      0x0100  /* AIF1ADC1_VU */
@@ -4289,4 +4495,102 @@
 #define WM8994_TEMP_SHUT_DB_SHIFT                    0  /* TEMP_SHUT_DB */
 #define WM8994_TEMP_SHUT_DB_WIDTH                    1  /* TEMP_SHUT_DB */
 
+/*
+ * R2304 (0x900) - DSP2_Program
+ */
+#define WM8958_DSP2_ENA                         0x0001  /* DSP2_ENA */
+#define WM8958_DSP2_ENA_MASK                    0x0001  /* DSP2_ENA */
+#define WM8958_DSP2_ENA_SHIFT                        0  /* DSP2_ENA */
+#define WM8958_DSP2_ENA_WIDTH                        1  /* DSP2_ENA */
+
+/*
+ * R2305 (0x901) - DSP2_Config
+ */
+#define WM8958_MBC_SEL_MASK                     0x0030  /* MBC_SEL - [5:4] */
+#define WM8958_MBC_SEL_SHIFT                         4  /* MBC_SEL - [5:4] */
+#define WM8958_MBC_SEL_WIDTH                         2  /* MBC_SEL - [5:4] */
+#define WM8958_MBC_ENA                          0x0001  /* MBC_ENA */
+#define WM8958_MBC_ENA_MASK                     0x0001  /* MBC_ENA */
+#define WM8958_MBC_ENA_SHIFT                         0  /* MBC_ENA */
+#define WM8958_MBC_ENA_WIDTH                         1  /* MBC_ENA */
+
+/*
+ * R2560 (0xA00) - DSP2_MagicNum
+ */
+#define WM8958_DSP2_MAGIC_NUM_MASK              0xFFFF  /* DSP2_MAGIC_NUM - [15:0] */
+#define WM8958_DSP2_MAGIC_NUM_SHIFT                  0  /* DSP2_MAGIC_NUM - [15:0] */
+#define WM8958_DSP2_MAGIC_NUM_WIDTH                 16  /* DSP2_MAGIC_NUM - [15:0] */
+
+/*
+ * R2561 (0xA01) - DSP2_ReleaseYear
+ */
+#define WM8958_DSP2_RELEASE_YEAR_MASK           0xFFFF  /* DSP2_RELEASE_YEAR - [15:0] */
+#define WM8958_DSP2_RELEASE_YEAR_SHIFT               0  /* DSP2_RELEASE_YEAR - [15:0] */
+#define WM8958_DSP2_RELEASE_YEAR_WIDTH              16  /* DSP2_RELEASE_YEAR - [15:0] */
+
+/*
+ * R2562 (0xA02) - DSP2_ReleaseMonthDay
+ */
+#define WM8958_DSP2_RELEASE_MONTH_MASK          0xFF00  /* DSP2_RELEASE_MONTH - [15:8] */
+#define WM8958_DSP2_RELEASE_MONTH_SHIFT              8  /* DSP2_RELEASE_MONTH - [15:8] */
+#define WM8958_DSP2_RELEASE_MONTH_WIDTH              8  /* DSP2_RELEASE_MONTH - [15:8] */
+#define WM8958_DSP2_RELEASE_DAY_MASK            0x00FF  /* DSP2_RELEASE_DAY - [7:0] */
+#define WM8958_DSP2_RELEASE_DAY_SHIFT                0  /* DSP2_RELEASE_DAY - [7:0] */
+#define WM8958_DSP2_RELEASE_DAY_WIDTH                8  /* DSP2_RELEASE_DAY - [7:0] */
+
+/*
+ * R2563 (0xA03) - DSP2_ReleaseTime
+ */
+#define WM8958_DSP2_RELEASE_HOURS_MASK          0xFF00  /* DSP2_RELEASE_HOURS - [15:8] */
+#define WM8958_DSP2_RELEASE_HOURS_SHIFT              8  /* DSP2_RELEASE_HOURS - [15:8] */
+#define WM8958_DSP2_RELEASE_HOURS_WIDTH              8  /* DSP2_RELEASE_HOURS - [15:8] */
+#define WM8958_DSP2_RELEASE_MINS_MASK           0x00FF  /* DSP2_RELEASE_MINS - [7:0] */
+#define WM8958_DSP2_RELEASE_MINS_SHIFT               0  /* DSP2_RELEASE_MINS - [7:0] */
+#define WM8958_DSP2_RELEASE_MINS_WIDTH               8  /* DSP2_RELEASE_MINS - [7:0] */
+
+/*
+ * R2564 (0xA04) - DSP2_VerMajMin
+ */
+#define WM8958_DSP2_MAJOR_VER_MASK              0xFF00  /* DSP2_MAJOR_VER - [15:8] */
+#define WM8958_DSP2_MAJOR_VER_SHIFT                  8  /* DSP2_MAJOR_VER - [15:8] */
+#define WM8958_DSP2_MAJOR_VER_WIDTH                  8  /* DSP2_MAJOR_VER - [15:8] */
+#define WM8958_DSP2_MINOR_VER_MASK              0x00FF  /* DSP2_MINOR_VER - [7:0] */
+#define WM8958_DSP2_MINOR_VER_SHIFT                  0  /* DSP2_MINOR_VER - [7:0] */
+#define WM8958_DSP2_MINOR_VER_WIDTH                  8  /* DSP2_MINOR_VER - [7:0] */
+
+/*
+ * R2565 (0xA05) - DSP2_VerBuild
+ */
+#define WM8958_DSP2_BUILD_VER_MASK              0xFFFF  /* DSP2_BUILD_VER - [15:0] */
+#define WM8958_DSP2_BUILD_VER_SHIFT                  0  /* DSP2_BUILD_VER - [15:0] */
+#define WM8958_DSP2_BUILD_VER_WIDTH                 16  /* DSP2_BUILD_VER - [15:0] */
+
+/*
+ * R2573 (0xA0D) - DSP2_ExecControl
+ */
+#define WM8958_DSP2_STOPC                       0x0020  /* DSP2_STOPC */
+#define WM8958_DSP2_STOPC_MASK                  0x0020  /* DSP2_STOPC */
+#define WM8958_DSP2_STOPC_SHIFT                      5  /* DSP2_STOPC */
+#define WM8958_DSP2_STOPC_WIDTH                      1  /* DSP2_STOPC */
+#define WM8958_DSP2_STOPS                       0x0010  /* DSP2_STOPS */
+#define WM8958_DSP2_STOPS_MASK                  0x0010  /* DSP2_STOPS */
+#define WM8958_DSP2_STOPS_SHIFT                      4  /* DSP2_STOPS */
+#define WM8958_DSP2_STOPS_WIDTH                      1  /* DSP2_STOPS */
+#define WM8958_DSP2_STOPI                       0x0008  /* DSP2_STOPI */
+#define WM8958_DSP2_STOPI_MASK                  0x0008  /* DSP2_STOPI */
+#define WM8958_DSP2_STOPI_SHIFT                      3  /* DSP2_STOPI */
+#define WM8958_DSP2_STOPI_WIDTH                      1  /* DSP2_STOPI */
+#define WM8958_DSP2_STOP                        0x0004  /* DSP2_STOP */
+#define WM8958_DSP2_STOP_MASK                   0x0004  /* DSP2_STOP */
+#define WM8958_DSP2_STOP_SHIFT                       2  /* DSP2_STOP */
+#define WM8958_DSP2_STOP_WIDTH                       1  /* DSP2_STOP */
+#define WM8958_DSP2_RUNR                        0x0002  /* DSP2_RUNR */
+#define WM8958_DSP2_RUNR_MASK                   0x0002  /* DSP2_RUNR */
+#define WM8958_DSP2_RUNR_SHIFT                       1  /* DSP2_RUNR */
+#define WM8958_DSP2_RUNR_WIDTH                       1  /* DSP2_RUNR */
+#define WM8958_DSP2_RUN                         0x0001  /* DSP2_RUN */
+#define WM8958_DSP2_RUN_MASK                    0x0001  /* DSP2_RUN */
+#define WM8958_DSP2_RUN_SHIFT                        0  /* DSP2_RUN */
+#define WM8958_DSP2_RUN_WIDTH                        1  /* DSP2_RUN */
+
 #endif