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authorDmitry Torokhov <dmitry.torokhov@gmail.com>2013-11-14 20:38:05 -0500
committerDmitry Torokhov <dmitry.torokhov@gmail.com>2013-11-14 20:38:05 -0500
commit42249094f79422fbf5ed4b54eeb48ff096809b8f (patch)
tree91e6850c8c7e8cc284cf8bb6363f8662f84011f4 /include/linux/mfd
parent936816161978ca716a56c5e553c68f25972b1e3a (diff)
parent2c027b7c48a888ab173ba45babb4525e278375d9 (diff)
Merge branch 'next' into for-linus
Merge first round of changes for 3.13 merge window.
Diffstat (limited to 'include/linux/mfd')
-rw-r--r--include/linux/mfd/88pm80x.h17
-rw-r--r--include/linux/mfd/abx500/ab8500-sysctrl.h4
-rw-r--r--include/linux/mfd/abx500/ab8500.h2
-rw-r--r--include/linux/mfd/arizona/core.h4
-rw-r--r--include/linux/mfd/arizona/gpio.h96
-rw-r--r--include/linux/mfd/arizona/pdata.h2
-rw-r--r--include/linux/mfd/arizona/registers.h47
-rw-r--r--include/linux/mfd/da9063/core.h93
-rw-r--r--include/linux/mfd/da9063/pdata.h111
-rw-r--r--include/linux/mfd/da9063/registers.h1028
-rw-r--r--include/linux/mfd/davinci_voicecodec.h8
-rw-r--r--include/linux/mfd/dbx500-prcmu.h12
-rw-r--r--include/linux/mfd/kempld.h125
-rw-r--r--include/linux/mfd/max77693-private.h13
-rw-r--r--include/linux/mfd/max77693.h18
-rw-r--r--include/linux/mfd/max8998-private.h7
-rw-r--r--include/linux/mfd/max8998.h20
-rw-r--r--include/linux/mfd/mc13xxx.h100
-rw-r--r--include/linux/mfd/mcp.h2
-rw-r--r--include/linux/mfd/palmas.h142
-rw-r--r--include/linux/mfd/rtsx_common.h3
-rw-r--r--include/linux/mfd/rtsx_pci.h67
-rw-r--r--include/linux/mfd/samsung/core.h6
-rw-r--r--include/linux/mfd/samsung/s2mps11.h18
-rw-r--r--include/linux/mfd/syscon/clps711x.h94
-rw-r--r--include/linux/mfd/syscon/imx6q-iomuxc-gpr.h137
-rw-r--r--include/linux/mfd/ti_am335x_tscadc.h52
-rw-r--r--include/linux/mfd/tmio.h6
-rw-r--r--include/linux/mfd/tps65217.h19
-rw-r--r--include/linux/mfd/twl6040.h9
-rw-r--r--include/linux/mfd/ucb1x00.h1
-rw-r--r--include/linux/mfd/wm8994/core.h2
-rw-r--r--include/linux/mfd/wm8994/pdata.h10
-rw-r--r--include/linux/mfd/wm8994/registers.h8
34 files changed, 2072 insertions, 211 deletions
diff --git a/include/linux/mfd/88pm80x.h b/include/linux/mfd/88pm80x.h
index e94537befabd..97cb283cc8e1 100644
--- a/include/linux/mfd/88pm80x.h
+++ b/include/linux/mfd/88pm80x.h
@@ -17,7 +17,6 @@
17#include <linux/regmap.h> 17#include <linux/regmap.h>
18#include <linux/atomic.h> 18#include <linux/atomic.h>
19 19
20#define PM80X_VERSION_MASK (0xFF) /* 80X chip ID mask */
21enum { 20enum {
22 CHIP_INVALID = 0, 21 CHIP_INVALID = 0,
23 CHIP_PM800, 22 CHIP_PM800,
@@ -299,8 +298,7 @@ struct pm80x_chip {
299 struct regmap *regmap; 298 struct regmap *regmap;
300 struct regmap_irq_chip *regmap_irq_chip; 299 struct regmap_irq_chip *regmap_irq_chip;
301 struct regmap_irq_chip_data *irq_data; 300 struct regmap_irq_chip_data *irq_data;
302 unsigned char version; 301 int type;
303 int id;
304 int irq; 302 int irq;
305 int irq_mode; 303 int irq_mode;
306 unsigned long wu_flag; 304 unsigned long wu_flag;
@@ -309,8 +307,14 @@ struct pm80x_chip {
309 307
310struct pm80x_platform_data { 308struct pm80x_platform_data {
311 struct pm80x_rtc_pdata *rtc; 309 struct pm80x_rtc_pdata *rtc;
312 unsigned short power_page_addr; /* power page I2C address */ 310 /*
313 unsigned short gpadc_page_addr; /* gpadc page I2C address */ 311 * For the regulator not defined, set regulators[not_defined] to be
312 * NULL. num_regulators are the number of regulators supposed to be
313 * initialized. If all regulators are not defined, set num_regulators
314 * to be 0.
315 */
316 struct regulator_init_data *regulators[PM800_ID_RG_MAX];
317 unsigned int num_regulators;
314 int irq_mode; /* Clear interrupt by read/write(0/1) */ 318 int irq_mode; /* Clear interrupt by read/write(0/1) */
315 int batt_det; /* enable/disable */ 319 int batt_det; /* enable/disable */
316 int (*plat_config)(struct pm80x_chip *chip, 320 int (*plat_config)(struct pm80x_chip *chip,
@@ -363,7 +367,6 @@ static inline int pm80x_dev_resume(struct device *dev)
363} 367}
364#endif 368#endif
365 369
366extern int pm80x_init(struct i2c_client *client, 370extern int pm80x_init(struct i2c_client *client);
367 const struct i2c_device_id *id);
368extern int pm80x_deinit(void); 371extern int pm80x_deinit(void);
369#endif /* __LINUX_MFD_88PM80X_H */ 372#endif /* __LINUX_MFD_88PM80X_H */
diff --git a/include/linux/mfd/abx500/ab8500-sysctrl.h b/include/linux/mfd/abx500/ab8500-sysctrl.h
index 990bc93f46e1..adba89d9c660 100644
--- a/include/linux/mfd/abx500/ab8500-sysctrl.h
+++ b/include/linux/mfd/abx500/ab8500-sysctrl.h
@@ -278,8 +278,8 @@ struct ab8500_sysctrl_platform_data {
278 278
279#define AB9540_SYSCLK12CONFCTRL_PLL26TO38ENA BIT(0) 279#define AB9540_SYSCLK12CONFCTRL_PLL26TO38ENA BIT(0)
280#define AB9540_SYSCLK12CONFCTRL_SYSCLK12USBMUXSEL BIT(1) 280#define AB9540_SYSCLK12CONFCTRL_SYSCLK12USBMUXSEL BIT(1)
281#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL_MASK 0x0C 281#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL0 BIT(2)
282#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL_SHIFT 2 282#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL1 BIT(3)
283#define AB9540_SYSCLK12CONFCTRL_SYSCLK12BUFMUX BIT(4) 283#define AB9540_SYSCLK12CONFCTRL_SYSCLK12BUFMUX BIT(4)
284#define AB9540_SYSCLK12CONFCTRL_SYSCLK12PLLMUX BIT(5) 284#define AB9540_SYSCLK12CONFCTRL_SYSCLK12PLLMUX BIT(5)
285#define AB9540_SYSCLK12CONFCTRL_SYSCLK2MUXVALID BIT(6) 285#define AB9540_SYSCLK12CONFCTRL_SYSCLK2MUXVALID BIT(6)
diff --git a/include/linux/mfd/abx500/ab8500.h b/include/linux/mfd/abx500/ab8500.h
index 0390d5943ed6..f4acd898dac9 100644
--- a/include/linux/mfd/abx500/ab8500.h
+++ b/include/linux/mfd/abx500/ab8500.h
@@ -291,6 +291,8 @@ enum ab8500_version {
291#define AB8540_INT_FSYNC2R 213 291#define AB8540_INT_FSYNC2R 213
292#define AB8540_INT_BITCLK2F 214 292#define AB8540_INT_BITCLK2F 214
293#define AB8540_INT_BITCLK2R 215 293#define AB8540_INT_BITCLK2R 215
294/* ab8540_irq_regoffset[27] -> IT[Source|Latch|Mask]33 */
295#define AB8540_INT_RTC_1S 216
294 296
295/* 297/*
296 * AB8500_AB9540_NR_IRQS is used when configuring the IRQ numbers for the 298 * AB8500_AB9540_NR_IRQS is used when configuring the IRQ numbers for the
diff --git a/include/linux/mfd/arizona/core.h b/include/linux/mfd/arizona/core.h
index cc281368dc55..5cf8b91ce996 100644
--- a/include/linux/mfd/arizona/core.h
+++ b/include/linux/mfd/arizona/core.h
@@ -23,6 +23,7 @@
23enum arizona_type { 23enum arizona_type {
24 WM5102 = 1, 24 WM5102 = 1,
25 WM5110 = 2, 25 WM5110 = 2,
26 WM8997 = 3,
26}; 27};
27 28
28#define ARIZONA_IRQ_GP1 0 29#define ARIZONA_IRQ_GP1 0
@@ -95,6 +96,8 @@ struct arizona {
95 96
96 struct arizona_pdata pdata; 97 struct arizona_pdata pdata;
97 98
99 unsigned int external_dcvdd:1;
100
98 int irq; 101 int irq;
99 struct irq_domain *virq; 102 struct irq_domain *virq;
100 struct regmap_irq_chip_data *aod_irq_chip; 103 struct regmap_irq_chip_data *aod_irq_chip;
@@ -119,5 +122,6 @@ int arizona_set_irq_wake(struct arizona *arizona, int irq, int on);
119 122
120int wm5102_patch(struct arizona *arizona); 123int wm5102_patch(struct arizona *arizona);
121int wm5110_patch(struct arizona *arizona); 124int wm5110_patch(struct arizona *arizona);
125int wm8997_patch(struct arizona *arizona);
122 126
123#endif 127#endif
diff --git a/include/linux/mfd/arizona/gpio.h b/include/linux/mfd/arizona/gpio.h
new file mode 100644
index 000000000000..d2146bb74f89
--- /dev/null
+++ b/include/linux/mfd/arizona/gpio.h
@@ -0,0 +1,96 @@
1/*
2 * GPIO configuration for Arizona devices
3 *
4 * Copyright 2013 Wolfson Microelectronics. PLC.
5 *
6 * Author: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef _ARIZONA_GPIO_H
14#define _ARIZONA_GPIO_H
15
16#define ARIZONA_GP_FN_TXLRCLK 0x00
17#define ARIZONA_GP_FN_GPIO 0x01
18#define ARIZONA_GP_FN_IRQ1 0x02
19#define ARIZONA_GP_FN_IRQ2 0x03
20#define ARIZONA_GP_FN_OPCLK 0x04
21#define ARIZONA_GP_FN_FLL1_OUT 0x05
22#define ARIZONA_GP_FN_FLL2_OUT 0x06
23#define ARIZONA_GP_FN_PWM1 0x08
24#define ARIZONA_GP_FN_PWM2 0x09
25#define ARIZONA_GP_FN_SYSCLK_UNDERCLOCKED 0x0A
26#define ARIZONA_GP_FN_ASYNCCLK_UNDERCLOCKED 0x0B
27#define ARIZONA_GP_FN_FLL1_LOCK 0x0C
28#define ARIZONA_GP_FN_FLL2_LOCK 0x0D
29#define ARIZONA_GP_FN_FLL1_CLOCK_OK 0x0F
30#define ARIZONA_GP_FN_FLL2_CLOCK_OK 0x10
31#define ARIZONA_GP_FN_HEADPHONE_DET 0x12
32#define ARIZONA_GP_FN_MIC_DET 0x13
33#define ARIZONA_GP_FN_WSEQ_STATUS 0x15
34#define ARIZONA_GP_FN_CIF_ADDRESS_ERROR 0x16
35#define ARIZONA_GP_FN_ASRC1_LOCK 0x1A
36#define ARIZONA_GP_FN_ASRC2_LOCK 0x1B
37#define ARIZONA_GP_FN_ASRC_CONFIG_ERROR 0x1C
38#define ARIZONA_GP_FN_DRC1_SIGNAL_DETECT 0x1D
39#define ARIZONA_GP_FN_DRC1_ANTICLIP 0x1E
40#define ARIZONA_GP_FN_DRC1_DECAY 0x1F
41#define ARIZONA_GP_FN_DRC1_NOISE 0x20
42#define ARIZONA_GP_FN_DRC1_QUICK_RELEASE 0x21
43#define ARIZONA_GP_FN_DRC2_SIGNAL_DETECT 0x22
44#define ARIZONA_GP_FN_DRC2_ANTICLIP 0x23
45#define ARIZONA_GP_FN_DRC2_DECAY 0x24
46#define ARIZONA_GP_FN_DRC2_NOISE 0x25
47#define ARIZONA_GP_FN_DRC2_QUICK_RELEASE 0x26
48#define ARIZONA_GP_FN_MIXER_DROPPED_SAMPLE 0x27
49#define ARIZONA_GP_FN_AIF1_CONFIG_ERROR 0x28
50#define ARIZONA_GP_FN_AIF2_CONFIG_ERROR 0x29
51#define ARIZONA_GP_FN_AIF3_CONFIG_ERROR 0x2A
52#define ARIZONA_GP_FN_SPK_TEMP_SHUTDOWN 0x2B
53#define ARIZONA_GP_FN_SPK_TEMP_WARNING 0x2C
54#define ARIZONA_GP_FN_UNDERCLOCKED 0x2D
55#define ARIZONA_GP_FN_OVERCLOCKED 0x2E
56#define ARIZONA_GP_FN_DSP_IRQ1 0x35
57#define ARIZONA_GP_FN_DSP_IRQ2 0x36
58#define ARIZONA_GP_FN_ASYNC_OPCLK 0x3D
59#define ARIZONA_GP_FN_BOOT_DONE 0x44
60#define ARIZONA_GP_FN_DSP1_RAM_READY 0x45
61#define ARIZONA_GP_FN_SYSCLK_ENA_STATUS 0x4B
62#define ARIZONA_GP_FN_ASYNCCLK_ENA_STATUS 0x4C
63
64#define ARIZONA_GPN_DIR 0x8000 /* GPN_DIR */
65#define ARIZONA_GPN_DIR_MASK 0x8000 /* GPN_DIR */
66#define ARIZONA_GPN_DIR_SHIFT 15 /* GPN_DIR */
67#define ARIZONA_GPN_DIR_WIDTH 1 /* GPN_DIR */
68#define ARIZONA_GPN_PU 0x4000 /* GPN_PU */
69#define ARIZONA_GPN_PU_MASK 0x4000 /* GPN_PU */
70#define ARIZONA_GPN_PU_SHIFT 14 /* GPN_PU */
71#define ARIZONA_GPN_PU_WIDTH 1 /* GPN_PU */
72#define ARIZONA_GPN_PD 0x2000 /* GPN_PD */
73#define ARIZONA_GPN_PD_MASK 0x2000 /* GPN_PD */
74#define ARIZONA_GPN_PD_SHIFT 13 /* GPN_PD */
75#define ARIZONA_GPN_PD_WIDTH 1 /* GPN_PD */
76#define ARIZONA_GPN_LVL 0x0800 /* GPN_LVL */
77#define ARIZONA_GPN_LVL_MASK 0x0800 /* GPN_LVL */
78#define ARIZONA_GPN_LVL_SHIFT 11 /* GPN_LVL */
79#define ARIZONA_GPN_LVL_WIDTH 1 /* GPN_LVL */
80#define ARIZONA_GPN_POL 0x0400 /* GPN_POL */
81#define ARIZONA_GPN_POL_MASK 0x0400 /* GPN_POL */
82#define ARIZONA_GPN_POL_SHIFT 10 /* GPN_POL */
83#define ARIZONA_GPN_POL_WIDTH 1 /* GPN_POL */
84#define ARIZONA_GPN_OP_CFG 0x0200 /* GPN_OP_CFG */
85#define ARIZONA_GPN_OP_CFG_MASK 0x0200 /* GPN_OP_CFG */
86#define ARIZONA_GPN_OP_CFG_SHIFT 9 /* GPN_OP_CFG */
87#define ARIZONA_GPN_OP_CFG_WIDTH 1 /* GPN_OP_CFG */
88#define ARIZONA_GPN_DB 0x0100 /* GPN_DB */
89#define ARIZONA_GPN_DB_MASK 0x0100 /* GPN_DB */
90#define ARIZONA_GPN_DB_SHIFT 8 /* GPN_DB */
91#define ARIZONA_GPN_DB_WIDTH 1 /* GPN_DB */
92#define ARIZONA_GPN_FN_MASK 0x007F /* GPN_DB */
93#define ARIZONA_GPN_FN_SHIFT 0 /* GPN_DB */
94#define ARIZONA_GPN_FN_WIDTH 7 /* GPN_DB */
95
96#endif
diff --git a/include/linux/mfd/arizona/pdata.h b/include/linux/mfd/arizona/pdata.h
index 80dead1f7100..12a5c135c746 100644
--- a/include/linux/mfd/arizona/pdata.h
+++ b/include/linux/mfd/arizona/pdata.h
@@ -77,7 +77,7 @@ struct arizona_micbias {
77 int mV; /** Regulated voltage */ 77 int mV; /** Regulated voltage */
78 unsigned int ext_cap:1; /** External capacitor fitted */ 78 unsigned int ext_cap:1; /** External capacitor fitted */
79 unsigned int discharge:1; /** Actively discharge */ 79 unsigned int discharge:1; /** Actively discharge */
80 unsigned int fast_start:1; /** Enable aggressive startup ramp rate */ 80 unsigned int soft_start:1; /** Disable aggressive startup ramp rate */
81 unsigned int bypass:1; /** Use bypass mode */ 81 unsigned int bypass:1; /** Use bypass mode */
82}; 82};
83 83
diff --git a/include/linux/mfd/arizona/registers.h b/include/linux/mfd/arizona/registers.h
index 715b6ba3d52a..4706d3d46e56 100644
--- a/include/linux/mfd/arizona/registers.h
+++ b/include/linux/mfd/arizona/registers.h
@@ -215,6 +215,9 @@
215#define ARIZONA_DAC_DIGITAL_VOLUME_6R 0x43D 215#define ARIZONA_DAC_DIGITAL_VOLUME_6R 0x43D
216#define ARIZONA_DAC_VOLUME_LIMIT_6R 0x43E 216#define ARIZONA_DAC_VOLUME_LIMIT_6R 0x43E
217#define ARIZONA_NOISE_GATE_SELECT_6R 0x43F 217#define ARIZONA_NOISE_GATE_SELECT_6R 0x43F
218#define ARIZONA_DRE_ENABLE 0x440
219#define ARIZONA_DRE_CONTROL_2 0x442
220#define ARIZONA_DRE_CONTROL_3 0x443
218#define ARIZONA_DAC_AEC_CONTROL_1 0x450 221#define ARIZONA_DAC_AEC_CONTROL_1 0x450
219#define ARIZONA_NOISE_GATE_CONTROL 0x458 222#define ARIZONA_NOISE_GATE_CONTROL 0x458
220#define ARIZONA_PDM_SPK1_CTRL_1 0x490 223#define ARIZONA_PDM_SPK1_CTRL_1 0x490
@@ -1002,6 +1005,7 @@
1002#define ARIZONA_DSP2_CLOCKING_1 0x1201 1005#define ARIZONA_DSP2_CLOCKING_1 0x1201
1003#define ARIZONA_DSP2_STATUS_1 0x1204 1006#define ARIZONA_DSP2_STATUS_1 0x1204
1004#define ARIZONA_DSP2_STATUS_2 0x1205 1007#define ARIZONA_DSP2_STATUS_2 0x1205
1008#define ARIZONA_DSP2_STATUS_3 0x1206
1005#define ARIZONA_DSP2_SCRATCH_0 0x1240 1009#define ARIZONA_DSP2_SCRATCH_0 0x1240
1006#define ARIZONA_DSP2_SCRATCH_1 0x1241 1010#define ARIZONA_DSP2_SCRATCH_1 0x1241
1007#define ARIZONA_DSP2_SCRATCH_2 0x1242 1011#define ARIZONA_DSP2_SCRATCH_2 0x1242
@@ -1010,6 +1014,7 @@
1010#define ARIZONA_DSP3_CLOCKING_1 0x1301 1014#define ARIZONA_DSP3_CLOCKING_1 0x1301
1011#define ARIZONA_DSP3_STATUS_1 0x1304 1015#define ARIZONA_DSP3_STATUS_1 0x1304
1012#define ARIZONA_DSP3_STATUS_2 0x1305 1016#define ARIZONA_DSP3_STATUS_2 0x1305
1017#define ARIZONA_DSP3_STATUS_3 0x1306
1013#define ARIZONA_DSP3_SCRATCH_0 0x1340 1018#define ARIZONA_DSP3_SCRATCH_0 0x1340
1014#define ARIZONA_DSP3_SCRATCH_1 0x1341 1019#define ARIZONA_DSP3_SCRATCH_1 0x1341
1015#define ARIZONA_DSP3_SCRATCH_2 0x1342 1020#define ARIZONA_DSP3_SCRATCH_2 0x1342
@@ -1018,6 +1023,7 @@
1018#define ARIZONA_DSP4_CLOCKING_1 0x1401 1023#define ARIZONA_DSP4_CLOCKING_1 0x1401
1019#define ARIZONA_DSP4_STATUS_1 0x1404 1024#define ARIZONA_DSP4_STATUS_1 0x1404
1020#define ARIZONA_DSP4_STATUS_2 0x1405 1025#define ARIZONA_DSP4_STATUS_2 0x1405
1026#define ARIZONA_DSP4_STATUS_3 0x1406
1021#define ARIZONA_DSP4_SCRATCH_0 0x1440 1027#define ARIZONA_DSP4_SCRATCH_0 0x1440
1022#define ARIZONA_DSP4_SCRATCH_1 0x1441 1028#define ARIZONA_DSP4_SCRATCH_1 0x1441
1023#define ARIZONA_DSP4_SCRATCH_2 0x1442 1029#define ARIZONA_DSP4_SCRATCH_2 0x1442
@@ -3130,6 +3136,47 @@
3130#define ARIZONA_OUT6R_NGATE_SRC_WIDTH 12 /* OUT6R_NGATE_SRC - [11:0] */ 3136#define ARIZONA_OUT6R_NGATE_SRC_WIDTH 12 /* OUT6R_NGATE_SRC - [11:0] */
3131 3137
3132/* 3138/*
3139 * R1088 (0x440) - DRE Enable
3140 */
3141#define ARIZONA_DRE3L_ENA 0x0010 /* DRE3L_ENA */
3142#define ARIZONA_DRE3L_ENA_MASK 0x0010 /* DRE3L_ENA */
3143#define ARIZONA_DRE3L_ENA_SHIFT 4 /* DRE3L_ENA */
3144#define ARIZONA_DRE3L_ENA_WIDTH 1 /* DRE3L_ENA */
3145#define ARIZONA_DRE2R_ENA 0x0008 /* DRE2R_ENA */
3146#define ARIZONA_DRE2R_ENA_MASK 0x0008 /* DRE2R_ENA */
3147#define ARIZONA_DRE2R_ENA_SHIFT 3 /* DRE2R_ENA */
3148#define ARIZONA_DRE2R_ENA_WIDTH 1 /* DRE2R_ENA */
3149#define ARIZONA_DRE2L_ENA 0x0004 /* DRE2L_ENA */
3150#define ARIZONA_DRE2L_ENA_MASK 0x0004 /* DRE2L_ENA */
3151#define ARIZONA_DRE2L_ENA_SHIFT 2 /* DRE2L_ENA */
3152#define ARIZONA_DRE2L_ENA_WIDTH 1 /* DRE2L_ENA */
3153#define ARIZONA_DRE1R_ENA 0x0002 /* DRE1R_ENA */
3154#define ARIZONA_DRE1R_ENA_MASK 0x0002 /* DRE1R_ENA */
3155#define ARIZONA_DRE1R_ENA_SHIFT 1 /* DRE1R_ENA */
3156#define ARIZONA_DRE1R_ENA_WIDTH 1 /* DRE1R_ENA */
3157#define ARIZONA_DRE1L_ENA 0x0001 /* DRE1L_ENA */
3158#define ARIZONA_DRE1L_ENA_MASK 0x0001 /* DRE1L_ENA */
3159#define ARIZONA_DRE1L_ENA_SHIFT 0 /* DRE1L_ENA */
3160#define ARIZONA_DRE1L_ENA_WIDTH 1 /* DRE1L_ENA */
3161
3162/*
3163 * R1090 (0x442) - DRE Control 2
3164 */
3165#define ARIZONA_DRE_T_LOW_MASK 0x3F00 /* DRE_T_LOW - [13:8] */
3166#define ARIZONA_DRE_T_LOW_SHIFT 8 /* DRE_T_LOW - [13:8] */
3167#define ARIZONA_DRE_T_LOW_WIDTH 6 /* DRE_T_LOW - [13:8] */
3168
3169/*
3170 * R1091 (0x443) - DRE Control 3
3171 */
3172#define ARIZONA_DRE_GAIN_SHIFT_MASK 0xC000 /* DRE_GAIN_SHIFT - [15:14] */
3173#define ARIZONA_DRE_GAIN_SHIFT_SHIFT 14 /* DRE_GAIN_SHIFT - [15:14] */
3174#define ARIZONA_DRE_GAIN_SHIFT_WIDTH 2 /* DRE_GAIN_SHIFT - [15:14] */
3175#define ARIZONA_DRE_LOW_LEVEL_ABS_MASK 0x000F /* LOW_LEVEL_ABS - [3:0] */
3176#define ARIZONA_DRE_LOW_LEVEL_ABS_SHIFT 0 /* LOW_LEVEL_ABS - [3:0] */
3177#define ARIZONA_DRE_LOW_LEVEL_ABS_WIDTH 4 /* LOW_LEVEL_ABS - [3:0] */
3178
3179/*
3133 * R1104 (0x450) - DAC AEC Control 1 3180 * R1104 (0x450) - DAC AEC Control 1
3134 */ 3181 */
3135#define ARIZONA_AEC_LOOPBACK_SRC_MASK 0x003C /* AEC_LOOPBACK_SRC - [5:2] */ 3182#define ARIZONA_AEC_LOOPBACK_SRC_MASK 0x003C /* AEC_LOOPBACK_SRC - [5:2] */
diff --git a/include/linux/mfd/da9063/core.h b/include/linux/mfd/da9063/core.h
new file mode 100644
index 000000000000..2d2a0af675fd
--- /dev/null
+++ b/include/linux/mfd/da9063/core.h
@@ -0,0 +1,93 @@
1/*
2 * Definitions for DA9063 MFD driver
3 *
4 * Copyright 2012 Dialog Semiconductor Ltd.
5 *
6 * Author: Michal Hajduk <michal.hajduk@diasemi.com>
7 * Krystian Garbaciak <krystian.garbaciak@diasemi.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#ifndef __MFD_DA9063_CORE_H__
17#define __MFD_DA9063_CORE_H__
18
19#include <linux/interrupt.h>
20#include <linux/mfd/da9063/registers.h>
21
22/* DA9063 modules */
23#define DA9063_DRVNAME_CORE "da9063-core"
24#define DA9063_DRVNAME_REGULATORS "da9063-regulators"
25#define DA9063_DRVNAME_LEDS "da9063-leds"
26#define DA9063_DRVNAME_WATCHDOG "da9063-watchdog"
27#define DA9063_DRVNAME_HWMON "da9063-hwmon"
28#define DA9063_DRVNAME_ONKEY "da9063-onkey"
29#define DA9063_DRVNAME_RTC "da9063-rtc"
30#define DA9063_DRVNAME_VIBRATION "da9063-vibration"
31
32enum da9063_models {
33 PMIC_DA9063 = 0x61,
34};
35
36/* Interrupts */
37enum da9063_irqs {
38 DA9063_IRQ_ONKEY = 0,
39 DA9063_IRQ_ALARM,
40 DA9063_IRQ_TICK,
41 DA9063_IRQ_ADC_RDY,
42 DA9063_IRQ_SEQ_RDY,
43 DA9063_IRQ_WAKE,
44 DA9063_IRQ_TEMP,
45 DA9063_IRQ_COMP_1V2,
46 DA9063_IRQ_LDO_LIM,
47 DA9063_IRQ_REG_UVOV,
48 DA9063_IRQ_VDD_MON,
49 DA9063_IRQ_WARN,
50 DA9063_IRQ_GPI0,
51 DA9063_IRQ_GPI1,
52 DA9063_IRQ_GPI2,
53 DA9063_IRQ_GPI3,
54 DA9063_IRQ_GPI4,
55 DA9063_IRQ_GPI5,
56 DA9063_IRQ_GPI6,
57 DA9063_IRQ_GPI7,
58 DA9063_IRQ_GPI8,
59 DA9063_IRQ_GPI9,
60 DA9063_IRQ_GPI10,
61 DA9063_IRQ_GPI11,
62 DA9063_IRQ_GPI12,
63 DA9063_IRQ_GPI13,
64 DA9063_IRQ_GPI14,
65 DA9063_IRQ_GPI15,
66};
67
68#define DA9063_IRQ_BASE_OFFSET 0
69#define DA9063_NUM_IRQ (DA9063_IRQ_GPI15 + 1 - DA9063_IRQ_BASE_OFFSET)
70
71struct da9063 {
72 /* Device */
73 struct device *dev;
74 unsigned short model;
75 unsigned short revision;
76 unsigned int flags;
77
78 /* Control interface */
79 struct regmap *regmap;
80
81 /* Interrupts */
82 int chip_irq;
83 unsigned int irq_base;
84 struct regmap_irq_chip_data *regmap_irq;
85};
86
87int da9063_device_init(struct da9063 *da9063, unsigned int irq);
88int da9063_irq_init(struct da9063 *da9063);
89
90void da9063_device_exit(struct da9063 *da9063);
91void da9063_irq_exit(struct da9063 *da9063);
92
93#endif /* __MFD_DA9063_CORE_H__ */
diff --git a/include/linux/mfd/da9063/pdata.h b/include/linux/mfd/da9063/pdata.h
new file mode 100644
index 000000000000..95c8742215a7
--- /dev/null
+++ b/include/linux/mfd/da9063/pdata.h
@@ -0,0 +1,111 @@
1/*
2 * Platform configuration options for DA9063
3 *
4 * Copyright 2012 Dialog Semiconductor Ltd.
5 *
6 * Author: Michal Hajduk <michal.hajduk@diasemi.com>
7 * Author: Krystian Garbaciak <krystian.garbaciak@diasemi.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#ifndef __MFD_DA9063_PDATA_H__
17#define __MFD_DA9063_PDATA_H__
18
19#include <linux/regulator/machine.h>
20
21/*
22 * Regulator configuration
23 */
24/* DA9063 regulator IDs */
25enum {
26 /* BUCKs */
27 DA9063_ID_BCORE1,
28 DA9063_ID_BCORE2,
29 DA9063_ID_BPRO,
30 DA9063_ID_BMEM,
31 DA9063_ID_BIO,
32 DA9063_ID_BPERI,
33
34 /* BCORE1 and BCORE2 in merged mode */
35 DA9063_ID_BCORES_MERGED,
36 /* BMEM and BIO in merged mode */
37 DA9063_ID_BMEM_BIO_MERGED,
38 /* When two BUCKs are merged, they cannot be reused separately */
39
40 /* LDOs */
41 DA9063_ID_LDO1,
42 DA9063_ID_LDO2,
43 DA9063_ID_LDO3,
44 DA9063_ID_LDO4,
45 DA9063_ID_LDO5,
46 DA9063_ID_LDO6,
47 DA9063_ID_LDO7,
48 DA9063_ID_LDO8,
49 DA9063_ID_LDO9,
50 DA9063_ID_LDO10,
51 DA9063_ID_LDO11,
52};
53
54/* Regulators platform data */
55struct da9063_regulator_data {
56 int id;
57 struct regulator_init_data *initdata;
58};
59
60struct da9063_regulators_pdata {
61 unsigned n_regulators;
62 struct da9063_regulator_data *regulator_data;
63};
64
65
66/*
67 * RGB LED configuration
68 */
69/* LED IDs for flags in struct led_info. */
70enum {
71 DA9063_GPIO11_LED,
72 DA9063_GPIO14_LED,
73 DA9063_GPIO15_LED,
74
75 DA9063_LED_NUM
76};
77#define DA9063_LED_ID_MASK 0x3
78
79/* LED polarity for flags in struct led_info. */
80#define DA9063_LED_HIGH_LEVEL_ACTIVE 0x0
81#define DA9063_LED_LOW_LEVEL_ACTIVE 0x4
82
83
84/*
85 * General PMIC configuration
86 */
87/* HWMON ADC channels configuration */
88#define DA9063_FLG_FORCE_IN0_MANUAL_MODE 0x0010
89#define DA9063_FLG_FORCE_IN0_AUTO_MODE 0x0020
90#define DA9063_FLG_FORCE_IN1_MANUAL_MODE 0x0040
91#define DA9063_FLG_FORCE_IN1_AUTO_MODE 0x0080
92#define DA9063_FLG_FORCE_IN2_MANUAL_MODE 0x0100
93#define DA9063_FLG_FORCE_IN2_AUTO_MODE 0x0200
94#define DA9063_FLG_FORCE_IN3_MANUAL_MODE 0x0400
95#define DA9063_FLG_FORCE_IN3_AUTO_MODE 0x0800
96
97/* Disable register caching. */
98#define DA9063_FLG_NO_CACHE 0x0008
99
100struct da9063;
101
102/* DA9063 platform data */
103struct da9063_pdata {
104 int (*init)(struct da9063 *da9063);
105 int irq_base;
106 unsigned flags;
107 struct da9063_regulators_pdata *regulators_pdata;
108 struct led_platform_data *leds_pdata;
109};
110
111#endif /* __MFD_DA9063_PDATA_H__ */
diff --git a/include/linux/mfd/da9063/registers.h b/include/linux/mfd/da9063/registers.h
new file mode 100644
index 000000000000..5834813fb5f3
--- /dev/null
+++ b/include/linux/mfd/da9063/registers.h
@@ -0,0 +1,1028 @@
1/*
2 * Registers definition for DA9063 modules
3 *
4 * Copyright 2012 Dialog Semiconductor Ltd.
5 *
6 * Author: Michal Hajduk <michal.hajduk@diasemi.com>
7 * Krystian Garbaciak <krystian.garbaciak@diasemi.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#ifndef _DA9063_REG_H
17#define _DA9063_REG_H
18
19#define DA9063_I2C_PAGE_SEL_SHIFT 1
20
21#define DA9063_EVENT_REG_NUM 4
22#define DA9210_EVENT_REG_NUM 2
23#define DA9063_EXT_EVENT_REG_NUM (DA9063_EVENT_REG_NUM + \
24 DA9210_EVENT_REG_NUM)
25
26/* Page selection I2C or SPI always in the begining of any page. */
27/* Page 0 : I2C access 0x000 - 0x0FF SPI access 0x000 - 0x07F */
28/* Page 1 : SPI access 0x080 - 0x0FF */
29/* Page 2 : I2C access 0x100 - 0x1FF SPI access 0x100 - 0x17F */
30/* Page 3 : SPI access 0x180 - 0x1FF */
31#define DA9063_REG_PAGE_CON 0x00
32
33/* System Control and Event Registers */
34#define DA9063_REG_STATUS_A 0x01
35#define DA9063_REG_STATUS_B 0x02
36#define DA9063_REG_STATUS_C 0x03
37#define DA9063_REG_STATUS_D 0x04
38#define DA9063_REG_FAULT_LOG 0x05
39#define DA9063_REG_EVENT_A 0x06
40#define DA9063_REG_EVENT_B 0x07
41#define DA9063_REG_EVENT_C 0x08
42#define DA9063_REG_EVENT_D 0x09
43#define DA9063_REG_IRQ_MASK_A 0x0A
44#define DA9063_REG_IRQ_MASK_B 0x0B
45#define DA9063_REG_IRQ_MASK_C 0x0C
46#define DA9063_REG_IRQ_MASK_D 0x0D
47#define DA9063_REG_CONTROL_A 0x0E
48#define DA9063_REG_CONTROL_B 0x0F
49#define DA9063_REG_CONTROL_C 0x10
50#define DA9063_REG_CONTROL_D 0x11
51#define DA9063_REG_CONTROL_E 0x12
52#define DA9063_REG_CONTROL_F 0x13
53#define DA9063_REG_PD_DIS 0x14
54
55/* GPIO Control Registers */
56#define DA9063_REG_GPIO_0_1 0x15
57#define DA9063_REG_GPIO_2_3 0x16
58#define DA9063_REG_GPIO_4_5 0x17
59#define DA9063_REG_GPIO_6_7 0x18
60#define DA9063_REG_GPIO_8_9 0x19
61#define DA9063_REG_GPIO_10_11 0x1A
62#define DA9063_REG_GPIO_12_13 0x1B
63#define DA9063_REG_GPIO_14_15 0x1C
64#define DA9063_REG_GPIO_MODE_0_7 0x1D
65#define DA9063_REG_GPIO_MODE_8_15 0x1E
66#define DA9063_REG_GPIO_SWITCH_CONT 0x1F
67
68/* Regulator Control Registers */
69#define DA9063_REG_BCORE2_CONT 0x20
70#define DA9063_REG_BCORE1_CONT 0x21
71#define DA9063_REG_BPRO_CONT 0x22
72#define DA9063_REG_BMEM_CONT 0x23
73#define DA9063_REG_BIO_CONT 0x24
74#define DA9063_REG_BPERI_CONT 0x25
75#define DA9063_REG_LDO1_CONT 0x26
76#define DA9063_REG_LDO2_CONT 0x27
77#define DA9063_REG_LDO3_CONT 0x28
78#define DA9063_REG_LDO4_CONT 0x29
79#define DA9063_REG_LDO5_CONT 0x2A
80#define DA9063_REG_LDO6_CONT 0x2B
81#define DA9063_REG_LDO7_CONT 0x2C
82#define DA9063_REG_LDO8_CONT 0x2D
83#define DA9063_REG_LDO9_CONT 0x2E
84#define DA9063_REG_LDO10_CONT 0x2F
85#define DA9063_REG_LDO11_CONT 0x30
86#define DA9063_REG_VIB 0x31
87#define DA9063_REG_DVC_1 0x32
88#define DA9063_REG_DVC_2 0x33
89
90/* GP-ADC Control Registers */
91#define DA9063_REG_ADC_MAN 0x34
92#define DA9063_REG_ADC_CONT 0x35
93#define DA9063_REG_VSYS_MON 0x36
94#define DA9063_REG_ADC_RES_L 0x37
95#define DA9063_REG_ADC_RES_H 0x38
96#define DA9063_REG_VSYS_RES 0x39
97#define DA9063_REG_ADCIN1_RES 0x3A
98#define DA9063_REG_ADCIN2_RES 0x3B
99#define DA9063_REG_ADCIN3_RES 0x3C
100#define DA9063_REG_MON1_RES 0x3D
101#define DA9063_REG_MON2_RES 0x3E
102#define DA9063_REG_MON3_RES 0x3F
103
104/* RTC Calendar and Alarm Registers */
105#define DA9063_REG_COUNT_S 0x40
106#define DA9063_REG_COUNT_MI 0x41
107#define DA9063_REG_COUNT_H 0x42
108#define DA9063_REG_COUNT_D 0x43
109#define DA9063_REG_COUNT_MO 0x44
110#define DA9063_REG_COUNT_Y 0x45
111#define DA9063_REG_ALARM_MI 0x46
112#define DA9063_REG_ALARM_H 0x47
113#define DA9063_REG_ALARM_D 0x48
114#define DA9063_REG_ALARM_MO 0x49
115#define DA9063_REG_ALARM_Y 0x4A
116#define DA9063_REG_SECOND_A 0x4B
117#define DA9063_REG_SECOND_B 0x4C
118#define DA9063_REG_SECOND_C 0x4D
119#define DA9063_REG_SECOND_D 0x4E
120
121/* Sequencer Control Registers */
122#define DA9063_REG_SEQ 0x81
123#define DA9063_REG_SEQ_TIMER 0x82
124#define DA9063_REG_ID_2_1 0x83
125#define DA9063_REG_ID_4_3 0x84
126#define DA9063_REG_ID_6_5 0x85
127#define DA9063_REG_ID_8_7 0x86
128#define DA9063_REG_ID_10_9 0x87
129#define DA9063_REG_ID_12_11 0x88
130#define DA9063_REG_ID_14_13 0x89
131#define DA9063_REG_ID_16_15 0x8A
132#define DA9063_REG_ID_18_17 0x8B
133#define DA9063_REG_ID_20_19 0x8C
134#define DA9063_REG_ID_22_21 0x8D
135#define DA9063_REG_ID_24_23 0x8E
136#define DA9063_REG_ID_26_25 0x8F
137#define DA9063_REG_ID_28_27 0x90
138#define DA9063_REG_ID_30_29 0x91
139#define DA9063_REG_ID_32_31 0x92
140#define DA9063_REG_SEQ_A 0x95
141#define DA9063_REG_SEQ_B 0x96
142#define DA9063_REG_WAIT 0x97
143#define DA9063_REG_EN_32K 0x98
144#define DA9063_REG_RESET 0x99
145
146/* Regulator Setting Registers */
147#define DA9063_REG_BUCK_ILIM_A 0x9A
148#define DA9063_REG_BUCK_ILIM_B 0x9B
149#define DA9063_REG_BUCK_ILIM_C 0x9C
150#define DA9063_REG_BCORE2_CFG 0x9D
151#define DA9063_REG_BCORE1_CFG 0x9E
152#define DA9063_REG_BPRO_CFG 0x9F
153#define DA9063_REG_BIO_CFG 0xA0
154#define DA9063_REG_BMEM_CFG 0xA1
155#define DA9063_REG_BPERI_CFG 0xA2
156#define DA9063_REG_VBCORE2_A 0xA3
157#define DA9063_REG_VBCORE1_A 0xA4
158#define DA9063_REG_VBPRO_A 0xA5
159#define DA9063_REG_VBMEM_A 0xA6
160#define DA9063_REG_VBIO_A 0xA7
161#define DA9063_REG_VBPERI_A 0xA8
162#define DA9063_REG_VLDO1_A 0xA9
163#define DA9063_REG_VLDO2_A 0xAA
164#define DA9063_REG_VLDO3_A 0xAB
165#define DA9063_REG_VLDO4_A 0xAC
166#define DA9063_REG_VLDO5_A 0xAD
167#define DA9063_REG_VLDO6_A 0xAE
168#define DA9063_REG_VLDO7_A 0xAF
169#define DA9063_REG_VLDO8_A 0xB0
170#define DA9063_REG_VLDO9_A 0xB1
171#define DA9063_REG_VLDO10_A 0xB2
172#define DA9063_REG_VLDO11_A 0xB3
173#define DA9063_REG_VBCORE2_B 0xB4
174#define DA9063_REG_VBCORE1_B 0xB5
175#define DA9063_REG_VBPRO_B 0xB6
176#define DA9063_REG_VBMEM_B 0xB7
177#define DA9063_REG_VBIO_B 0xB8
178#define DA9063_REG_VBPERI_B 0xB9
179#define DA9063_REG_VLDO1_B 0xBA
180#define DA9063_REG_VLDO2_B 0xBB
181#define DA9063_REG_VLDO3_B 0xBC
182#define DA9063_REG_VLDO4_B 0xBD
183#define DA9063_REG_VLDO5_B 0xBE
184#define DA9063_REG_VLDO6_B 0xBF
185#define DA9063_REG_VLDO7_B 0xC0
186#define DA9063_REG_VLDO8_B 0xC1
187#define DA9063_REG_VLDO9_B 0xC2
188#define DA9063_REG_VLDO10_B 0xC3
189#define DA9063_REG_VLDO11_B 0xC4
190
191/* Backup Battery Charger Control Register */
192#define DA9063_REG_BBAT_CONT 0xC5
193
194/* GPIO PWM (LED) */
195#define DA9063_REG_GPO11_LED 0xC6
196#define DA9063_REG_GPO14_LED 0xC7
197#define DA9063_REG_GPO15_LED 0xC8
198
199/* GP-ADC Threshold Registers */
200#define DA9063_REG_ADC_CFG 0xC9
201#define DA9063_REG_AUTO1_HIGH 0xCA
202#define DA9063_REG_AUTO1_LOW 0xCB
203#define DA9063_REG_AUTO2_HIGH 0xCC
204#define DA9063_REG_AUTO2_LOW 0xCD
205#define DA9063_REG_AUTO3_HIGH 0xCE
206#define DA9063_REG_AUTO3_LOW 0xCF
207
208/* DA9063 Configuration registers */
209/* OTP */
210#define DA9063_REG_OPT_COUNT 0x101
211#define DA9063_REG_OPT_ADDR 0x102
212#define DA9063_REG_OPT_DATA 0x103
213
214/* Customer Trim and Configuration */
215#define DA9063_REG_T_OFFSET 0x104
216#define DA9063_REG_INTERFACE 0x105
217#define DA9063_REG_CONFIG_A 0x106
218#define DA9063_REG_CONFIG_B 0x107
219#define DA9063_REG_CONFIG_C 0x108
220#define DA9063_REG_CONFIG_D 0x109
221#define DA9063_REG_CONFIG_E 0x10A
222#define DA9063_REG_CONFIG_F 0x10B
223#define DA9063_REG_CONFIG_G 0x10C
224#define DA9063_REG_CONFIG_H 0x10D
225#define DA9063_REG_CONFIG_I 0x10E
226#define DA9063_REG_CONFIG_J 0x10F
227#define DA9063_REG_CONFIG_K 0x110
228#define DA9063_REG_CONFIG_L 0x111
229#define DA9063_REG_MON_REG_1 0x112
230#define DA9063_REG_MON_REG_2 0x113
231#define DA9063_REG_MON_REG_3 0x114
232#define DA9063_REG_MON_REG_4 0x115
233#define DA9063_REG_MON_REG_5 0x116
234#define DA9063_REG_MON_REG_6 0x117
235#define DA9063_REG_TRIM_CLDR 0x118
236
237/* General Purpose Registers */
238#define DA9063_REG_GP_ID_0 0x119
239#define DA9063_REG_GP_ID_1 0x11A
240#define DA9063_REG_GP_ID_2 0x11B
241#define DA9063_REG_GP_ID_3 0x11C
242#define DA9063_REG_GP_ID_4 0x11D
243#define DA9063_REG_GP_ID_5 0x11E
244#define DA9063_REG_GP_ID_6 0x11F
245#define DA9063_REG_GP_ID_7 0x120
246#define DA9063_REG_GP_ID_8 0x121
247#define DA9063_REG_GP_ID_9 0x122
248#define DA9063_REG_GP_ID_10 0x123
249#define DA9063_REG_GP_ID_11 0x124
250#define DA9063_REG_GP_ID_12 0x125
251#define DA9063_REG_GP_ID_13 0x126
252#define DA9063_REG_GP_ID_14 0x127
253#define DA9063_REG_GP_ID_15 0x128
254#define DA9063_REG_GP_ID_16 0x129
255#define DA9063_REG_GP_ID_17 0x12A
256#define DA9063_REG_GP_ID_18 0x12B
257#define DA9063_REG_GP_ID_19 0x12C
258
259/* Chip ID and variant */
260#define DA9063_REG_CHIP_ID 0x181
261#define DA9063_REG_CHIP_VARIANT 0x182
262
263/*
264 * PMIC registers bits
265 */
266/* DA9063_REG_PAGE_CON (addr=0x00) */
267#define DA9063_PEG_PAGE_SHIFT 0
268#define DA9063_REG_PAGE_MASK 0x07
269#define DA9063_REG_PAGE0 0x00
270#define DA9063_REG_PAGE2 0x02
271#define DA9063_PAGE_WRITE_MODE 0x00
272#define DA9063_REPEAT_WRITE_MODE 0x40
273#define DA9063_PAGE_REVERT 0x80
274
275/* DA9063_REG_STATUS_A (addr=0x01) */
276#define DA9063_NONKEY 0x01
277#define DA9063_WAKE 0x02
278#define DA9063_DVC_BUSY 0x04
279#define DA9063_COMP_1V2 0x08
280
281/* DA9063_REG_STATUS_B (addr=0x02) */
282#define DA9063_GPI0 0x01
283#define DA9063_GPI1 0x02
284#define DA9063_GPI2 0x04
285#define DA9063_GPI3 0x08
286#define DA9063_GPI4 0x10
287#define DA9063_GPI5 0x20
288#define DA9063_GPI6 0x40
289#define DA9063_GPI7 0x80
290
291/* DA9063_REG_STATUS_C (addr=0x03) */
292#define DA9063_GPI8 0x01
293#define DA9063_GPI9 0x02
294#define DA9063_GPI10 0x04
295#define DA9063_GPI11 0x08
296#define DA9063_GPI12 0x10
297#define DA9063_GPI13 0x20
298#define DA9063_GPI14 0x40
299#define DA9063_GPI15 0x80
300
301/* DA9063_REG_STATUS_D (addr=0x04) */
302#define DA9063_LDO3_LIM 0x08
303#define DA9063_LDO4_LIM 0x10
304#define DA9063_LDO7_LIM 0x20
305#define DA9063_LDO8_LIM 0x40
306#define DA9063_LDO11_LIM 0x80
307
308/* DA9063_REG_FAULT_LOG (addr=0x05) */
309#define DA9063_TWD_ERROR 0x01
310#define DA9063_POR 0x02
311#define DA9063_VDD_FAULT 0x04
312#define DA9063_VDD_START 0x08
313#define DA9063_TEMP_CRIT 0x10
314#define DA9063_KEY_RESET 0x20
315#define DA9063_NSHUTDOWN 0x40
316#define DA9063_WAIT_SHUT 0x80
317
318/* DA9063_REG_EVENT_A (addr=0x06) */
319#define DA9063_E_NONKEY 0x01
320#define DA9063_E_ALARM 0x02
321#define DA9063_E_TICK 0x04
322#define DA9063_E_ADC_RDY 0x08
323#define DA9063_E_SEQ_RDY 0x10
324#define DA9063_EVENTS_B 0x20
325#define DA9063_EVENTS_C 0x40
326#define DA9063_EVENTS_D 0x80
327
328/* DA9063_REG_EVENT_B (addr=0x07) */
329#define DA9063_E_WAKE 0x01
330#define DA9063_E_TEMP 0x02
331#define DA9063_E_COMP_1V2 0x04
332#define DA9063_E_LDO_LIM 0x08
333#define DA9063_E_REG_UVOV 0x10
334#define DA9063_E_DVC_RDY 0x20
335#define DA9063_E_VDD_MON 0x40
336#define DA9063_E_VDD_WARN 0x80
337
338/* DA9063_REG_EVENT_C (addr=0x08) */
339#define DA9063_E_GPI0 0x01
340#define DA9063_E_GPI1 0x02
341#define DA9063_E_GPI2 0x04
342#define DA9063_E_GPI3 0x08
343#define DA9063_E_GPI4 0x10
344#define DA9063_E_GPI5 0x20
345#define DA9063_E_GPI6 0x40
346#define DA9063_E_GPI7 0x80
347
348/* DA9063_REG_EVENT_D (addr=0x09) */
349#define DA9063_E_GPI8 0x01
350#define DA9063_E_GPI9 0x02
351#define DA9063_E_GPI10 0x04
352#define DA9063_E_GPI11 0x08
353#define DA9063_E_GPI12 0x10
354#define DA9063_E_GPI13 0x20
355#define DA9063_E_GPI14 0x40
356#define DA9063_E_GPI15 0x80
357
358/* DA9063_REG_IRQ_MASK_A (addr=0x0A) */
359#define DA9063_M_ONKEY 0x01
360#define DA9063_M_ALARM 0x02
361#define DA9063_M_TICK 0x04
362#define DA9063_M_ADC_RDY 0x08
363#define DA9063_M_SEQ_RDY 0x10
364
365/* DA9063_REG_IRQ_MASK_B (addr=0x0B) */
366#define DA9063_M_WAKE 0x01
367#define DA9063_M_TEMP 0x02
368#define DA9063_M_COMP_1V2 0x04
369#define DA9063_M_LDO_LIM 0x08
370#define DA9063_M_UVOV 0x10
371#define DA9063_M_DVC_RDY 0x20
372#define DA9063_M_VDD_MON 0x40
373#define DA9063_M_VDD_WARN 0x80
374
375/* DA9063_REG_IRQ_MASK_C (addr=0x0C) */
376#define DA9063_M_GPI0 0x01
377#define DA9063_M_GPI1 0x02
378#define DA9063_M_GPI2 0x04
379#define DA9063_M_GPI3 0x08
380#define DA9063_M_GPI4 0x10
381#define DA9063_M_GPI5 0x20
382#define DA9063_M_GPI6 0x40
383#define DA9063_M_GPI7 0x80
384
385/* DA9063_REG_IRQ_MASK_D (addr=0x0D) */
386#define DA9063_M_GPI8 0x01
387#define DA9063_M_GPI9 0x02
388#define DA9063_M_GPI10 0x04
389#define DA9063_M_GPI11 0x08
390#define DA9063_M_GPI12 0x10
391#define DA9063_M_GPI13 0x20
392#define DA9063_M_GPI14 0x40
393#define DA9063_M_GPI15 0x80
394
395/* DA9063_REG_CONTROL_A (addr=0x0E) */
396#define DA9063_SYSTEM_EN 0x01
397#define DA9063_POWER_EN 0x02
398#define DA9063_POWER1_EN 0x04
399#define DA9063_STANDBY 0x08
400#define DA9063_M_SYSTEM_EN 0x10
401#define DA9063_M_POWER_EN 0x20
402#define DA9063_M_POWER1_EN 0x40
403#define DA9063_CP_EN 0x80
404
405/* DA9063_REG_CONTROL_B (addr=0x0F) */
406#define DA9063_CHG_SEL 0x01
407#define DA9063_WATCHDOG_PD 0x02
408#define DA9063_NRES_MODE 0x08
409#define DA9063_NONKEY_LOCK 0x10
410
411/* DA9063_REG_CONTROL_C (addr=0x10) */
412#define DA9063_DEBOUNCING_MASK 0x07
413#define DA9063_DEBOUNCING_OFF 0x0
414#define DA9063_DEBOUNCING_0MS1 0x1
415#define DA9063_DEBOUNCING_1MS 0x2
416#define DA9063_DEBOUNCING_10MS24 0x3
417#define DA9063_DEBOUNCING_51MS2 0x4
418#define DA9063_DEBOUNCING_256MS 0x5
419#define DA9063_DEBOUNCING_512MS 0x6
420#define DA9063_DEBOUNCING_1024MS 0x7
421
422#define DA9063_AUTO_BOOT 0x08
423#define DA9063_OTPREAD_EN 0x10
424#define DA9063_SLEW_RATE_MASK 0x60
425#define DA9063_SLEW_RATE_4US 0x00
426#define DA9063_SLEW_RATE_3US 0x20
427#define DA9063_SLEW_RATE_1US 0x40
428#define DA9063_SLEW_RATE_0US5 0x60
429#define DA9063_DEF_SUPPLY 0x80
430
431/* DA9063_REG_CONTROL_D (addr=0x11) */
432#define DA9063_TWDSCALE_MASK 0x07
433#define DA9063_BLINK_FRQ_MASK 0x38
434#define DA9063_BLINK_FRQ_OFF 0x00
435#define DA9063_BLINK_FRQ_1S0 0x08
436#define DA9063_BLINK_FRQ_2S0 0x10
437#define DA9063_BLINK_FRQ_4S0 0x18
438#define DA9063_BLINK_FRQ_0S18 0x20
439#define DA9063_BLINK_FRQ_2S0_VDD 0x28
440#define DA9063_BLINK_FRQ_4S0_VDD 0x30
441#define DA9063_BLINK_FRQ_0S18_VDD 0x38
442
443#define DA9063_BLINK_DUR_MASK 0xC0
444#define DA9063_BLINK_DUR_10MS 0x00
445#define DA9063_BLINK_DUR_20MS 0x40
446#define DA9063_BLINK_DUR_40MS 0x80
447#define DA9063_BLINK_DUR_20MSDBL 0xC0
448
449/* DA9063_REG_CONTROL_E (addr=0x12) */
450#define DA9063_RTC_MODE_PD 0x01
451#define DA9063_RTC_MODE_SD 0x02
452#define DA9063_RTC_EN 0x04
453#define DA9063_ECO_MODE 0x08
454#define DA9063_PM_FB1_PIN 0x10
455#define DA9063_PM_FB2_PIN 0x20
456#define DA9063_PM_FB3_PIN 0x40
457#define DA9063_V_LOCK 0x80
458
459/* DA9063_REG_CONTROL_F (addr=0x13) */
460#define DA9063_WATCHDOG 0x01
461#define DA9063_SHUTDOWN 0x02
462#define DA9063_WAKE_UP 0x04
463
464/* DA9063_REG_PD_DIS (addr=0x14) */
465#define DA9063_GPI_DIS 0x01
466#define DA9063_GPADC_PAUSE 0x02
467#define DA9063_PMIF_DIS 0x04
468#define DA9063_HS2WIRE_DIS 0x08
469#define DA9063_BBAT_DIS 0x20
470#define DA9063_OUT_32K_PAUSE 0x40
471#define DA9063_PMCONT_DIS 0x80
472
473/* DA9063_REG_GPIO_0_1 (addr=0x15) */
474#define DA9063_GPIO0_PIN_MASK 0x03
475#define DA9063_GPIO0_PIN_ADCIN1 0x00
476#define DA9063_GPIO0_PIN_GPI 0x01
477#define DA9063_GPIO0_PIN_GPO_OD 0x02
478#define DA9063_GPIO0_PIN_GPO 0x03
479#define DA9063_GPIO0_TYPE 0x04
480#define DA9063_GPIO0_TYPE_GPI_ACT_LOW 0x00
481#define DA9063_GPIO0_TYPE_GPO_VDD_IO1 0x00
482#define DA9063_GPIO0_TYPE_GPI_ACT_HIGH 0x04
483#define DA9063_GPIO0_TYPE_GPO_VDD_IO2 0x04
484#define DA9063_GPIO0_NO_WAKEUP 0x08
485#define DA9063_GPIO1_PIN_MASK 0x30
486#define DA9063_GPIO1_PIN_ADCIN2_COMP 0x00
487#define DA9063_GPIO1_PIN_GPI 0x10
488#define DA9063_GPIO1_PIN_GPO_OD 0x20
489#define DA9063_GPIO1_PIN_GPO 0x30
490#define DA9063_GPIO1_TYPE 0x40
491#define DA9063_GPIO1_TYPE_GPI_ACT_LOW 0x00
492#define DA9063_GPIO1_TYPE_GPO_VDD_IO1 0x00
493#define DA9063_GPIO1_TYPE_GPI_ACT_HIGH 0x04
494#define DA9063_GPIO1_TYPE_GPO_VDD_IO2 0x04
495#define DA9063_GPIO1_NO_WAKEUP 0x80
496
497/* DA9063_REG_GPIO_2_3 (addr=0x16) */
498#define DA9063_GPIO2_PIN_MASK 0x03
499#define DA9063_GPIO2_PIN_ADCIN3 0x00
500#define DA9063_GPIO2_PIN_GPI 0x01
501#define DA9063_GPIO2_PIN_GPO_PSS 0x02
502#define DA9063_GPIO2_PIN_GPO 0x03
503#define DA9063_GPIO2_TYPE 0x04
504#define DA9063_GPIO2_TYPE_GPI_ACT_LOW 0x00
505#define DA9063_GPIO2_TYPE_GPO_VDD_IO1 0x00
506#define DA9063_GPIO2_TYPE_GPI_ACT_HIGH 0x04
507#define DA9063_GPIO2_TYPE_GPO_VDD_IO2 0x04
508#define DA9063_GPIO2_NO_WAKEUP 0x08
509#define DA9063_GPIO3_PIN_MASK 0x30
510#define DA9063_GPIO3_PIN_CORE_SW_G 0x00
511#define DA9063_GPIO3_PIN_GPI 0x10
512#define DA9063_GPIO3_PIN_GPO_OD 0x20
513#define DA9063_GPIO3_PIN_GPO 0x30
514#define DA9063_GPIO3_TYPE 0x40
515#define DA9063_GPIO3_TYPE_GPI_ACT_LOW 0x00
516#define DA9063_GPIO3_TYPE_GPO_VDD_IO1 0x00
517#define DA9063_GPIO3_TYPE_GPI_ACT_HIGH 0x04
518#define DA9063_GPIO3_TYPE_GPO_VDD_IO2 0x04
519#define DA9063_GPIO3_NO_WAKEUP 0x80
520
521/* DA9063_REG_GPIO_4_5 (addr=0x17) */
522#define DA9063_GPIO4_PIN_MASK 0x03
523#define DA9063_GPIO4_PIN_CORE_SW_S 0x00
524#define DA9063_GPIO4_PIN_GPI 0x01
525#define DA9063_GPIO4_PIN_GPO_OD 0x02
526#define DA9063_GPIO4_PIN_GPO 0x03
527#define DA9063_GPIO4_TYPE 0x04
528#define DA9063_GPIO4_TYPE_GPI_ACT_LOW 0x00
529#define DA9063_GPIO4_TYPE_GPO_VDD_IO1 0x00
530#define DA9063_GPIO4_TYPE_GPI_ACT_HIGH 0x04
531#define DA9063_GPIO4_TYPE_GPO_VDD_IO2 0x04
532#define DA9063_GPIO4_NO_WAKEUP 0x08
533#define DA9063_GPIO5_PIN_MASK 0x30
534#define DA9063_GPIO5_PIN_PERI_SW_G 0x00
535#define DA9063_GPIO5_PIN_GPI 0x10
536#define DA9063_GPIO5_PIN_GPO_OD 0x20
537#define DA9063_GPIO5_PIN_GPO 0x30
538#define DA9063_GPIO5_TYPE 0x40
539#define DA9063_GPIO5_TYPE_GPI_ACT_LOW 0x00
540#define DA9063_GPIO5_TYPE_GPO_VDD_IO1 0x00
541#define DA9063_GPIO5_TYPE_GPI_ACT_HIGH 0x04
542#define DA9063_GPIO5_TYPE_GPO_VDD_IO2 0x04
543#define DA9063_GPIO5_NO_WAKEUP 0x80
544
545/* DA9063_REG_GPIO_6_7 (addr=0x18) */
546#define DA9063_GPIO6_PIN_MASK 0x03
547#define DA9063_GPIO6_PIN_PERI_SW_S 0x00
548#define DA9063_GPIO6_PIN_GPI 0x01
549#define DA9063_GPIO6_PIN_GPO_OD 0x02
550#define DA9063_GPIO6_PIN_GPO 0x03
551#define DA9063_GPIO6_TYPE 0x04
552#define DA9063_GPIO6_TYPE_GPI_ACT_LOW 0x00
553#define DA9063_GPIO6_TYPE_GPO_VDD_IO1 0x00
554#define DA9063_GPIO6_TYPE_GPI_ACT_HIGH 0x04
555#define DA9063_GPIO6_TYPE_GPO_VDD_IO2 0x04
556#define DA9063_GPIO6_NO_WAKEUP 0x08
557#define DA9063_GPIO7_PIN_MASK 0x30
558#define DA9063_GPIO7_PIN_GPI 0x10
559#define DA9063_GPIO7_PIN_GPO_PSS 0x20
560#define DA9063_GPIO7_PIN_GPO 0x30
561#define DA9063_GPIO7_TYPE 0x40
562#define DA9063_GPIO7_TYPE_GPI_ACT_LOW 0x00
563#define DA9063_GPIO7_TYPE_GPO_VDD_IO1 0x00
564#define DA9063_GPIO7_TYPE_GPI_ACT_HIGH 0x04
565#define DA9063_GPIO7_TYPE_GPO_VDD_IO2 0x04
566#define DA9063_GPIO7_NO_WAKEUP 0x80
567
568/* DA9063_REG_GPIO_8_9 (addr=0x19) */
569#define DA9063_GPIO8_PIN_MASK 0x03
570#define DA9063_GPIO8_PIN_GPI_SYS_EN 0x00
571#define DA9063_GPIO8_PIN_GPI 0x01
572#define DA9063_GPIO8_PIN_GPO_PSS 0x02
573#define DA9063_GPIO8_PIN_GPO 0x03
574#define DA9063_GPIO8_TYPE 0x04
575#define DA9063_GPIO8_TYPE_GPI_ACT_LOW 0x00
576#define DA9063_GPIO8_TYPE_GPO_VDD_IO1 0x00
577#define DA9063_GPIO8_TYPE_GPI_ACT_HIGH 0x04
578#define DA9063_GPIO8_TYPE_GPO_VDD_IO2 0x04
579#define DA9063_GPIO8_NO_WAKEUP 0x08
580#define DA9063_GPIO9_PIN_MASK 0x30
581#define DA9063_GPIO9_PIN_GPI_PWR_EN 0x00
582#define DA9063_GPIO9_PIN_GPI 0x10
583#define DA9063_GPIO9_PIN_GPO_PSS 0x20
584#define DA9063_GPIO9_PIN_GPO 0x30
585#define DA9063_GPIO9_TYPE 0x40
586#define DA9063_GPIO9_TYPE_GPI_ACT_LOW 0x00
587#define DA9063_GPIO9_TYPE_GPO_VDD_IO1 0x00
588#define DA9063_GPIO9_TYPE_GPI_ACT_HIGH 0x04
589#define DA9063_GPIO9_TYPE_GPO_VDD_IO2 0x04
590#define DA9063_GPIO9_NO_WAKEUP 0x80
591
592/* DA9063_REG_GPIO_10_11 (addr=0x1A) */
593#define DA9063_GPIO10_PIN_MASK 0x03
594#define DA9063_GPIO10_PIN_GPI_PWR1_EN 0x00
595#define DA9063_GPIO10_PIN_GPI 0x01
596#define DA9063_GPIO10_PIN_GPO_OD 0x02
597#define DA9063_GPIO10_PIN_GPO 0x03
598#define DA9063_GPIO10_TYPE 0x04
599#define DA9063_GPIO10_TYPE_GPI_ACT_LOW 0x00
600#define DA9063_GPIO10_TYPE_GPO_VDD_IO1 0x00
601#define DA9063_GPIO10_TYPE_GPI_ACT_HIGH 0x04
602#define DA9063_GPIO10_TYPE_GPO_VDD_IO2 0x04
603#define DA9063_GPIO10_NO_WAKEUP 0x08
604#define DA9063_GPIO11_PIN_MASK 0x30
605#define DA9063_GPIO11_PIN_GPO_OD 0x00
606#define DA9063_GPIO11_PIN_GPI 0x10
607#define DA9063_GPIO11_PIN_GPO_PSS 0x20
608#define DA9063_GPIO11_PIN_GPO 0x30
609#define DA9063_GPIO11_TYPE 0x40
610#define DA9063_GPIO11_TYPE_GPI_ACT_LOW 0x00
611#define DA9063_GPIO11_TYPE_GPO_VDD_IO1 0x00
612#define DA9063_GPIO11_TYPE_GPI_ACT_HIGH 0x04
613#define DA9063_GPIO11_TYPE_GPO_VDD_IO2 0x04
614#define DA9063_GPIO11_NO_WAKEUP 0x80
615
616/* DA9063_REG_GPIO_12_13 (addr=0x1B) */
617#define DA9063_GPIO12_PIN_MASK 0x03
618#define DA9063_GPIO12_PIN_NVDDFLT_OUT 0x00
619#define DA9063_GPIO12_PIN_GPI 0x01
620#define DA9063_GPIO12_PIN_VSYSMON_OUT 0x02
621#define DA9063_GPIO12_PIN_GPO 0x03
622#define DA9063_GPIO12_TYPE 0x04
623#define DA9063_GPIO12_TYPE_GPI_ACT_LOW 0x00
624#define DA9063_GPIO12_TYPE_GPO_VDD_IO1 0x00
625#define DA9063_GPIO12_TYPE_GPI_ACT_HIGH 0x04
626#define DA9063_GPIO12_TYPE_GPO_VDD_IO2 0x04
627#define DA9063_GPIO12_NO_WAKEUP 0x08
628#define DA9063_GPIO13_PIN_MASK 0x30
629#define DA9063_GPIO13_PIN_GPFB1_OUT 0x00
630#define DA9063_GPIO13_PIN_GPI 0x10
631#define DA9063_GPIO13_PIN_GPFB1_OUTOD 0x20
632#define DA9063_GPIO13_PIN_GPO 0x30
633#define DA9063_GPIO13_TYPE 0x40
634#define DA9063_GPIO13_TYPE_GPFB1_OUT 0x00
635#define DA9063_GPIO13_TYPE_GPI 0x00
636#define DA9063_GPIO13_TYPE_GPFB1_OUTOD 0x04
637#define DA9063_GPIO13_TYPE_GPO 0x04
638#define DA9063_GPIO13_NO_WAKEUP 0x80
639
640/* DA9063_REG_GPIO_14_15 (addr=0x1C) */
641#define DA9063_GPIO14_PIN_MASK 0x03
642#define DA9063_GPIO14_PIN_GPO_OD 0x00
643#define DA9063_GPIO14_PIN_GPI 0x01
644#define DA9063_GPIO14_PIN_HS2DATA 0x02
645#define DA9063_GPIO14_PIN_GPO 0x03
646#define DA9063_GPIO14_TYPE 0x04
647#define DA9063_GPIO14_TYPE_GPI_ACT_LOW 0x00
648#define DA9063_GPIO14_TYPE_GPO_VDD_IO1 0x00
649#define DA9063_GPIO14_TYPE_GPI_ACT_HIGH 0x04
650#define DA9063_GPIO14_TYPE_GPO_VDD_IO2 0x04
651#define DA9063_GPIO14_NO_WAKEUP 0x08
652#define DA9063_GPIO15_PIN_MASK 0x30
653#define DA9063_GPIO15_PIN_GPO_OD 0x00
654#define DA9063_GPIO15_PIN_GPI 0x10
655#define DA9063_GPIO15_PIN_GPO 0x30
656#define DA9063_GPIO15_TYPE 0x40
657#define DA9063_GPIO15_TYPE_GPFB1_OUT 0x00
658#define DA9063_GPIO15_TYPE_GPI 0x00
659#define DA9063_GPIO15_TYPE_GPFB1_OUTOD 0x04
660#define DA9063_GPIO15_TYPE_GPO 0x04
661#define DA9063_GPIO15_NO_WAKEUP 0x80
662
663/* DA9063_REG_GPIO_MODE_0_7 (addr=0x1D) */
664#define DA9063_GPIO0_MODE 0x01
665#define DA9063_GPIO1_MODE 0x02
666#define DA9063_GPIO2_MODE 0x04
667#define DA9063_GPIO3_MODE 0x08
668#define DA9063_GPIO4_MODE 0x10
669#define DA9063_GPIO5_MODE 0x20
670#define DA9063_GPIO6_MODE 0x40
671#define DA9063_GPIO7_MODE 0x80
672
673/* DA9063_REG_GPIO_MODE_8_15 (addr=0x1E) */
674#define DA9063_GPIO8_MODE 0x01
675#define DA9063_GPIO9_MODE 0x02
676#define DA9063_GPIO10_MODE 0x04
677#define DA9063_GPIO11_MODE 0x08
678#define DA9063_GPIO11_MODE_LED_ACT_HIGH 0x00
679#define DA9063_GPIO11_MODE_LED_ACT_LOW 0x08
680#define DA9063_GPIO12_MODE 0x10
681#define DA9063_GPIO13_MODE 0x20
682#define DA9063_GPIO14_MODE 0x40
683#define DA9063_GPIO14_MODE_LED_ACT_HIGH 0x00
684#define DA9063_GPIO14_MODE_LED_ACT_LOW 0x40
685#define DA9063_GPIO15_MODE 0x80
686#define DA9063_GPIO15_MODE_LED_ACT_HIGH 0x00
687#define DA9063_GPIO15_MODE_LED_ACT_LOW 0x80
688
689/* DA9063_REG_SWITCH_CONT (addr=0x1F) */
690#define DA9063_CORE_SW_GPI_MASK 0x03
691#define DA9063_CORE_SW_GPI_OFF 0x00
692#define DA9063_CORE_SW_GPI_GPIO1 0x01
693#define DA9063_CORE_SW_GPI_GPIO2 0x02
694#define DA9063_CORE_SW_GPI_GPIO13 0x03
695#define DA9063_PERI_SW_GPI_MASK 0x0C
696#define DA9063_PERI_SW_GPI_OFF 0x00
697#define DA9063_PERI_SW_GPI_GPIO1 0x04
698#define DA9063_PERI_SW_GPI_GPIO2 0x08
699#define DA9063_PERI_SW_GPI_GPIO13 0x0C
700#define DA9063_SWITCH_SR_MASK 0x30
701#define DA9063_SWITCH_SR_1MV 0x00
702#define DA9063_SWITCH_SR_5MV 0x10
703#define DA9063_SWITCH_SR_10MV 0x20
704#define DA9063_SWITCH_SR_50MV 0x30
705#define DA9063_SWITCH_SR_DIS 0x40
706#define DA9063_CP_EN_MODE 0x80
707
708/* DA9063_REGL_Bxxxx_CONT common bits (addr=0x20-0x25) */
709#define DA9063_BUCK_EN 0x01
710#define DA9063_BUCK_GPI_MASK 0x06
711#define DA9063_BUCK_GPI_OFF 0x00
712#define DA9063_BUCK_GPI_GPIO1 0x02
713#define DA9063_BUCK_GPI_GPIO2 0x04
714#define DA9063_BUCK_GPI_GPIO13 0x06
715#define DA9063_BUCK_CONF 0x08
716#define DA9063_VBUCK_GPI_MASK 0x60
717#define DA9063_VBUCK_GPI_OFF 0x00
718#define DA9063_VBUCK_GPI_GPIO1 0x20
719#define DA9063_VBUCK_GPI_GPIO2 0x40
720#define DA9063_VBUCK_GPI_GPIO13 0x60
721
722/* DA9063_REG_BCORE1_CONT specific bits (addr=0x21) */
723#define DA9063_CORE_SW_EN 0x10
724#define DA9063_CORE_SW_CONF 0x80
725
726/* DA9063_REG_BPERI_CONT specific bits (addr=0x25) */
727#define DA9063_PERI_SW_EN 0x10
728#define DA9063_PERI_SW_CONF 0x80
729
730/* DA9063_REG_LDOx_CONT common bits (addr=0x26-0x30) */
731#define DA9063_LDO_EN 0x01
732#define DA9063_LDO_GPI_MASK 0x06
733#define DA9063_LDO_GPI_OFF 0x00
734#define DA9063_LDO_GPI_GPIO1 0x02
735#define DA9063_LDO_GPI_GPIO2 0x04
736#define DA9063_LDO_GPI_GPIO13 0x06
737#define DA9063_LDO_PD_DIS 0x08
738#define DA9063_VLDO_GPI_MASK 0x60
739#define DA9063_VLDO_GPI_OFF 0x00
740#define DA9063_VLDO_GPI_GPIO1 0x20
741#define DA9063_VLDO_GPI_GPIO2 0x40
742#define DA9063_VLDO_GPI_GPIO13 0x60
743#define DA9063_LDO_CONF 0x80
744
745/* DA9063_REG_LDO5_CONT specific bits (addr=0x2A) */
746#define DA9063_VLDO5_SEL 0x10
747
748/* DA9063_REG_LDO6_CONT specific bits (addr=0x2B) */
749#define DA9063_VLDO6_SEL 0x10
750
751/* DA9063_REG_LDO7_CONT specific bits (addr=0x2C) */
752#define DA9063_VLDO7_SEL 0x10
753
754/* DA9063_REG_LDO8_CONT specific bits (addr=0x2D) */
755#define DA9063_VLDO8_SEL 0x10
756
757/* DA9063_REG_LDO9_CONT specific bits (addr=0x2E) */
758#define DA9063_VLDO9_SEL 0x10
759
760/* DA9063_REG_LDO10_CONT specific bits (addr=0x2F) */
761#define DA9063_VLDO10_SEL 0x10
762
763/* DA9063_REG_LDO11_CONT specific bits (addr=0x30) */
764#define DA9063_VLDO11_SEL 0x10
765
766/* DA9063_REG_VIB (addr=0x31) */
767#define DA9063_VIB_SET_MASK 0x3F
768#define DA9063_VIB_SET_OFF 0
769#define DA9063_VIB_SET_MAX 0x3F
770
771/* DA9063_REG_DVC_1 (addr=0x32) */
772#define DA9063_VBCORE1_SEL 0x01
773#define DA9063_VBCORE2_SEL 0x02
774#define DA9063_VBPRO_SEL 0x04
775#define DA9063_VBMEM_SEL 0x08
776#define DA9063_VBPERI_SEL 0x10
777#define DA9063_VLDO1_SEL 0x20
778#define DA9063_VLDO2_SEL 0x40
779#define DA9063_VLDO3_SEL 0x80
780
781/* DA9063_REG_DVC_2 (addr=0x33) */
782#define DA9063_VBIO_SEL 0x01
783#define DA9063_VLDO4_SEL 0x80
784
785/* DA9063_REG_ADC_MAN (addr=0x34) */
786#define DA9063_ADC_MUX_MASK 0x0F
787#define DA9063_ADC_MUX_VSYS 0x00
788#define DA9063_ADC_MUX_ADCIN1 0x01
789#define DA9063_ADC_MUX_ADCIN2 0x02
790#define DA9063_ADC_MUX_ADCIN3 0x03
791#define DA9063_ADC_MUX_T_SENSE 0x04
792#define DA9063_ADC_MUX_VBBAT 0x05
793#define DA9063_ADC_MUX_LDO_G1 0x08
794#define DA9063_ADC_MUX_LDO_G2 0x09
795#define DA9063_ADC_MUX_LDO_G3 0x0A
796#define DA9063_ADC_MAN 0x10
797#define DA9063_ADC_MODE 0x20
798
799/* DA9063_REG_ADC_CONT (addr=0x35) */
800#define DA9063_ADC_AUTO_VSYS_EN 0x01
801#define DA9063_ADC_AUTO_AD1_EN 0x02
802#define DA9063_ADC_AUTO_AD2_EN 0x04
803#define DA9063_ADC_AUTO_AD3_EN 0x08
804#define DA9063_ADC_AD1_ISRC_EN 0x10
805#define DA9063_ADC_AD2_ISRC_EN 0x20
806#define DA9063_ADC_AD3_ISRC_EN 0x40
807#define DA9063_COMP1V2_EN 0x80
808
809/* DA9063_REG_VSYS_MON (addr=0x36) */
810#define DA9063_VSYS_VAL_MASK 0xFF
811#define DA9063_VSYS_VAL_BASE 0x00
812
813/* DA9063_REG_ADC_RES_L (addr=0x37) */
814#define DA9063_ADC_RES_L_BITS 2
815#define DA9063_ADC_RES_L_MASK 0xC0
816
817/* DA9063_REG_ADC_RES_H (addr=0x38) */
818#define DA9063_ADC_RES_M_BITS 8
819#define DA9063_ADC_RES_M_MASK 0xFF
820
821/* DA9063_REG_(xxx_RES/ADC_RES_H) (addr=0x39-0x3F) */
822#define DA9063_ADC_VAL_MASK 0xFF
823
824/* DA9063_REG_COUNT_S (addr=0x40) */
825#define DA9063_RTC_READ 0x80
826#define DA9063_COUNT_SEC_MASK 0x3F
827
828/* DA9063_REG_COUNT_MI (addr=0x41) */
829#define DA9063_COUNT_MIN_MASK 0x3F
830
831/* DA9063_REG_COUNT_H (addr=0x42) */
832#define DA9063_COUNT_HOUR_MASK 0x1F
833
834/* DA9063_REG_COUNT_D (addr=0x43) */
835#define DA9063_COUNT_DAY_MASK 0x1F
836
837/* DA9063_REG_COUNT_MO (addr=0x44) */
838#define DA9063_COUNT_MONTH_MASK 0x0F
839
840/* DA9063_REG_COUNT_Y (addr=0x45) */
841#define DA9063_COUNT_YEAR_MASK 0x3F
842#define DA9063_MONITOR 0x40
843
844/* DA9063_REG_ALARM_MI (addr=0x46) */
845#define DA9063_ALARM_STATUS_ALARM 0x80
846#define DA9063_ALARM_STATUS_TICK 0x40
847#define DA9063_ALARM_MIN_MASK 0x3F
848
849/* DA9063_REG_ALARM_H (addr=0x47) */
850#define DA9063_ALARM_HOUR_MASK 0x1F
851
852/* DA9063_REG_ALARM_D (addr=0x48) */
853#define DA9063_ALARM_DAY_MASK 0x1F
854
855/* DA9063_REG_ALARM_MO (addr=0x49) */
856#define DA9063_TICK_WAKE 0x20
857#define DA9063_TICK_TYPE 0x10
858#define DA9063_TICK_TYPE_SEC 0x00
859#define DA9063_TICK_TYPE_MIN 0x10
860#define DA9063_ALARM_MONTH_MASK 0x0F
861
862/* DA9063_REG_ALARM_Y (addr=0x4A) */
863#define DA9063_TICK_ON 0x80
864#define DA9063_ALARM_ON 0x40
865#define DA9063_ALARM_YEAR_MASK 0x3F
866
867/* DA9063_REG_WAIT (addr=0x97)*/
868#define DA9063_REG_WAIT_TIME_MASK 0xF
869#define DA9063_WAIT_TIME_0_US 0x0
870#define DA9063_WAIT_TIME_512_US 0x1
871#define DA9063_WAIT_TIME_1_MS 0x2
872#define DA9063_WAIT_TIME_2_MS 0x3
873#define DA9063_WAIT_TIME_4_1_MS 0x4
874#define DA9063_WAIT_TIME_8_2_MS 0x5
875#define DA9063_WAIT_TIME_16_4_MS 0x6
876#define DA9063_WAIT_TIME_32_8_MS 0x7
877#define DA9063_WAIT_TIME_65_5_MS 0x8
878#define DA9063_WAIT_TIME_128_MS 0x9
879#define DA9063_WAIT_TIME_256_MS 0xA
880#define DA9063_WAIT_TIME_512_MS 0xB
881#define DA9063_WAIT_TIME_1_S 0xC
882#define DA9063_WAIT_TIME_2_1_S 0xD
883
884/* DA9063_REG_EN_32K (addr=0x98)*/
885#define DA9063_STABILIZ_TIME_MASK 0x7
886#define DA9063_CRYSTAL 0x08
887#define DA9063_DELAY_MODE 0x10
888#define DA9063_OUT_CLOCK 0x20
889#define DA9063_RTC_CLOCK 0x40
890#define DA9063_OUT_32K_EN 0x80
891
892/* DA9063_REG_CHIP_VARIANT */
893#define DA9063_CHIP_VARIANT_SHIFT 4
894
895/* DA9063_REG_BUCK_ILIM_A (addr=0x9A) */
896#define DA9063_BIO_ILIM_MASK 0x0F
897#define DA9063_BMEM_ILIM_MASK 0xF0
898
899/* DA9063_REG_BUCK_ILIM_B (addr=0x9B) */
900#define DA9063_BPRO_ILIM_MASK 0x0F
901#define DA9063_BPERI_ILIM_MASK 0xF0
902
903/* DA9063_REG_BUCK_ILIM_C (addr=0x9C) */
904#define DA9063_BCORE1_ILIM_MASK 0x0F
905#define DA9063_BCORE2_ILIM_MASK 0xF0
906
907/* DA9063_REG_Bxxxx_CFG common bits (addr=0x9D-0xA2) */
908#define DA9063_BUCK_FB_MASK 0x07
909#define DA9063_BUCK_PD_DIS_SHIFT 5
910#define DA9063_BUCK_MODE_MASK 0xC0
911#define DA9063_BUCK_MODE_MANUAL 0x00
912#define DA9063_BUCK_MODE_SLEEP 0x40
913#define DA9063_BUCK_MODE_SYNC 0x80
914#define DA9063_BUCK_MODE_AUTO 0xC0
915
916/* DA9063_REG_BPRO_CFG (addr=0x9F) */
917#define DA9063_BPRO_VTTR_EN 0x08
918#define DA9063_BPRO_VTT_EN 0x10
919
920/* DA9063_REG_VBxxxx_A/B (addr=0xA3-0xA8, 0xB4-0xB9) */
921#define DA9063_VBUCK_MASK 0x7F
922#define DA9063_VBUCK_BIAS 0
923#define DA9063_BUCK_SL 0x80
924
925/* DA9063_REG_VLDOx_A/B (addr=0xA9-0x3, 0xBA-0xC4) */
926#define DA9063_LDO_SL 0x80
927
928/* DA9063_REG_VLDO1_A/B (addr=0xA9, 0xBA) */
929#define DA9063_VLDO1_MASK 0x3F
930#define DA9063_VLDO1_BIAS 0
931
932/* DA9063_REG_VLDO2_A/B (addr=0xAA, 0xBB) */
933#define DA9063_VLDO2_MASK 0x3F
934#define DA9063_VLDO2_BIAS 0
935
936/* DA9063_REG_VLDO3_A/B (addr=0xAB, 0xBC) */
937#define DA9063_VLDO3_MASK 0x7F
938#define DA9063_VLDO3_BIAS 0
939
940/* DA9063_REG_VLDO4_A/B (addr=0xAC, 0xBD) */
941#define DA9063_VLDO4_MASK 0x7F
942#define DA9063_VLDO4_BIAS 0
943
944/* DA9063_REG_VLDO5_A/B (addr=0xAD, 0xBE) */
945#define DA9063_VLDO5_MASK 0x3F
946#define DA9063_VLDO5_BIAS 2
947
948/* DA9063_REG_VLDO6_A/B (addr=0xAE, 0xBF) */
949#define DA9063_VLDO6_MASK 0x3F
950#define DA9063_VLDO6_BIAS 2
951
952/* DA9063_REG_VLDO7_A/B (addr=0xAF, 0xC0) */
953#define DA9063_VLDO7_MASK 0x3F
954#define DA9063_VLDO7_BIAS 2
955
956/* DA9063_REG_VLDO8_A/B (addr=0xB0, 0xC1) */
957#define DA9063_VLDO8_MASK 0x3F
958#define DA9063_VLDO8_BIAS 2
959
960/* DA9063_REG_VLDO9_A/B (addr=0xB1, 0xC2) */
961#define DA9063_VLDO9_MASK 0x3F
962#define DA9063_VLDO9_BIAS 3
963
964/* DA9063_REG_VLDO10_A/B (addr=0xB2, 0xC3) */
965#define DA9063_VLDO10_MASK 0x3F
966#define DA9063_VLDO10_BIAS 2
967
968/* DA9063_REG_VLDO11_A/B (addr=0xB3, 0xC4) */
969#define DA9063_VLDO11_MASK 0x3F
970#define DA9063_VLDO11_BIAS 2
971
972/* DA9063_REG_GPO11_LED (addr=0xC6) */
973/* DA9063_REG_GPO14_LED (addr=0xC7) */
974/* DA9063_REG_GPO15_LED (addr=0xC8) */
975#define DA9063_GPIO_DIM 0x80
976#define DA9063_GPIO_PWM_MASK 0x7F
977
978/* DA9063_REG_CONFIG_H (addr=0x10D) */
979#define DA9063_PWM_CLK_MASK 0x01
980#define DA9063_PWM_CLK_PWM2MHZ 0x00
981#define DA9063_PWM_CLK_PWM1MHZ 0x01
982#define DA9063_LDO8_MODE_MASK 0x02
983#define DA9063_LDO8_MODE_LDO 0
984#define DA9063_LDO8_MODE_VIBR 0x02
985#define DA9063_MERGE_SENSE_MASK 0x04
986#define DA9063_MERGE_SENSE_GP_FB2 0x00
987#define DA9063_MERGE_SENSE_GPIO4 0x04
988#define DA9063_BCORE_MERGE 0x08
989#define DA9063_BPRO_OD 0x10
990#define DA9063_BCORE2_OD 0x20
991#define DA9063_BCORE1_OD 0x40
992#define DA9063_BUCK_MERGE 0x80
993
994/* DA9063_REG_CONFIG_I (addr=0x10E) */
995#define DA9063_NONKEY_PIN_MASK 0x03
996#define DA9063_NONKEY_PIN_PORT 0x00
997#define DA9063_NONKEY_PIN_SWDOWN 0x01
998#define DA9063_NONKEY_PIN_AUTODOWN 0x02
999#define DA9063_NONKEY_PIN_AUTOFLPRT 0x03
1000
1001/* DA9063_REG_MON_REG_5 (addr=0x116) */
1002#define DA9063_MON_A8_IDX_MASK 0x07
1003#define DA9063_MON_A8_IDX_NONE 0x00
1004#define DA9063_MON_A8_IDX_BCORE1 0x01
1005#define DA9063_MON_A8_IDX_BCORE2 0x02
1006#define DA9063_MON_A8_IDX_BPRO 0x03
1007#define DA9063_MON_A8_IDX_LDO3 0x04
1008#define DA9063_MON_A8_IDX_LDO4 0x05
1009#define DA9063_MON_A8_IDX_LDO11 0x06
1010#define DA9063_MON_A9_IDX_MASK 0x70
1011#define DA9063_MON_A9_IDX_NONE 0x00
1012#define DA9063_MON_A9_IDX_BIO 0x01
1013#define DA9063_MON_A9_IDX_BMEM 0x02
1014#define DA9063_MON_A9_IDX_BPERI 0x03
1015#define DA9063_MON_A9_IDX_LDO1 0x04
1016#define DA9063_MON_A9_IDX_LDO2 0x05
1017#define DA9063_MON_A9_IDX_LDO5 0x06
1018
1019/* DA9063_REG_MON_REG_6 (addr=0x117) */
1020#define DA9063_MON_A10_IDX_MASK 0x07
1021#define DA9063_MON_A10_IDX_NONE 0x00
1022#define DA9063_MON_A10_IDX_LDO6 0x01
1023#define DA9063_MON_A10_IDX_LDO7 0x02
1024#define DA9063_MON_A10_IDX_LDO8 0x03
1025#define DA9063_MON_A10_IDX_LDO9 0x04
1026#define DA9063_MON_A10_IDX_LDO10 0x05
1027
1028#endif /* _DA9063_REG_H */
diff --git a/include/linux/mfd/davinci_voicecodec.h b/include/linux/mfd/davinci_voicecodec.h
index 0ab61320ffa8..5166935ce66d 100644
--- a/include/linux/mfd/davinci_voicecodec.h
+++ b/include/linux/mfd/davinci_voicecodec.h
@@ -26,8 +26,11 @@
26#include <linux/kernel.h> 26#include <linux/kernel.h>
27#include <linux/platform_device.h> 27#include <linux/platform_device.h>
28#include <linux/mfd/core.h> 28#include <linux/mfd/core.h>
29#include <linux/platform_data/edma.h>
29 30
30#include <mach/edma.h> 31#include <mach/hardware.h>
32
33struct regmap;
31 34
32/* 35/*
33 * Register values. 36 * Register values.
@@ -112,8 +115,7 @@ struct davinci_vc {
112 115
113 /* Memory resources */ 116 /* Memory resources */
114 void __iomem *base; 117 void __iomem *base;
115 resource_size_t pbase; 118 struct regmap *regmap;
116 size_t base_size;
117 119
118 /* MFD cells */ 120 /* MFD cells */
119 struct mfd_cell cells[DAVINCI_VC_CELLS]; 121 struct mfd_cell cells[DAVINCI_VC_CELLS];
diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h
index 689e6a0d9c99..ca0790fba2f5 100644
--- a/include/linux/mfd/dbx500-prcmu.h
+++ b/include/linux/mfd/dbx500-prcmu.h
@@ -134,6 +134,11 @@ enum prcmu_clock {
134 PRCMU_SIACLK, 134 PRCMU_SIACLK,
135 PRCMU_SVACLK, 135 PRCMU_SVACLK,
136 PRCMU_ACLK, 136 PRCMU_ACLK,
137 PRCMU_HVACLK, /* Ux540 only */
138 PRCMU_G1CLK, /* Ux540 only */
139 PRCMU_SDMMCHCLK,
140 PRCMU_CAMCLK,
141 PRCMU_BML8580CLK,
137 PRCMU_NUM_REG_CLOCKS, 142 PRCMU_NUM_REG_CLOCKS,
138 PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS, 143 PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
139 PRCMU_CDCLK, 144 PRCMU_CDCLK,
@@ -148,6 +153,13 @@ enum prcmu_clock {
148 PRCMU_DSI0ESCCLK, 153 PRCMU_DSI0ESCCLK,
149 PRCMU_DSI1ESCCLK, 154 PRCMU_DSI1ESCCLK,
150 PRCMU_DSI2ESCCLK, 155 PRCMU_DSI2ESCCLK,
156 /* LCD DSI PLL - Ux540 only */
157 PRCMU_PLLDSI_LCD,
158 PRCMU_DSI0CLK_LCD,
159 PRCMU_DSI1CLK_LCD,
160 PRCMU_DSI0ESCCLK_LCD,
161 PRCMU_DSI1ESCCLK_LCD,
162 PRCMU_DSI2ESCCLK_LCD,
151}; 163};
152 164
153/** 165/**
diff --git a/include/linux/mfd/kempld.h b/include/linux/mfd/kempld.h
new file mode 100644
index 000000000000..b911ef3add03
--- /dev/null
+++ b/include/linux/mfd/kempld.h
@@ -0,0 +1,125 @@
1/*
2 * Kontron PLD driver definitions
3 *
4 * Copyright (c) 2010-2012 Kontron Europe GmbH
5 * Author: Michael Brunner <michael.brunner@kontron.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License 2 as published
9 * by the Free Software Foundation.
10 */
11
12#ifndef _LINUX_MFD_KEMPLD_H_
13#define _LINUX_MFD_KEMPLD_H_
14
15/* kempld register definitions */
16#define KEMPLD_IOINDEX 0xa80
17#define KEMPLD_IODATA 0xa81
18#define KEMPLD_MUTEX_KEY 0x80
19#define KEMPLD_VERSION 0x00
20#define KEMPLD_VERSION_LSB 0x00
21#define KEMPLD_VERSION_MSB 0x01
22#define KEMPLD_VERSION_GET_MINOR(x) (x & 0x1f)
23#define KEMPLD_VERSION_GET_MAJOR(x) ((x >> 5) & 0x1f)
24#define KEMPLD_VERSION_GET_NUMBER(x) ((x >> 10) & 0xf)
25#define KEMPLD_VERSION_GET_TYPE(x) ((x >> 14) & 0x3)
26#define KEMPLD_BUILDNR 0x02
27#define KEMPLD_BUILDNR_LSB 0x02
28#define KEMPLD_BUILDNR_MSB 0x03
29#define KEMPLD_FEATURE 0x04
30#define KEMPLD_FEATURE_LSB 0x04
31#define KEMPLD_FEATURE_MSB 0x05
32#define KEMPLD_FEATURE_BIT_I2C (1 << 0)
33#define KEMPLD_FEATURE_BIT_WATCHDOG (1 << 1)
34#define KEMPLD_FEATURE_BIT_GPIO (1 << 2)
35#define KEMPLD_FEATURE_MASK_UART (7 << 3)
36#define KEMPLD_FEATURE_BIT_NMI (1 << 8)
37#define KEMPLD_FEATURE_BIT_SMI (1 << 9)
38#define KEMPLD_FEATURE_BIT_SCI (1 << 10)
39#define KEMPLD_SPEC 0x06
40#define KEMPLD_SPEC_GET_MINOR(x) (x & 0x0f)
41#define KEMPLD_SPEC_GET_MAJOR(x) ((x >> 4) & 0x0f)
42#define KEMPLD_IRQ_GPIO 0x35
43#define KEMPLD_IRQ_I2C 0x36
44#define KEMPLD_CFG 0x37
45#define KEMPLD_CFG_GPIO_I2C_MUX (1 << 0)
46#define KEMPLD_CFG_BIOS_WP (1 << 7)
47
48#define KEMPLD_CLK 33333333
49
50#define KEMPLD_TYPE_RELEASE 0x0
51#define KEMPLD_TYPE_DEBUG 0x1
52#define KEMPLD_TYPE_CUSTOM 0x2
53
54/**
55 * struct kempld_info - PLD device information structure
56 * @major: PLD major revision
57 * @minor: PLD minor revision
58 * @buildnr: PLD build number
59 * @number: PLD board specific index
60 * @type: PLD type
61 * @spec_major: PLD FW specification major revision
62 * @spec_minor: PLD FW specification minor revision
63 */
64struct kempld_info {
65 unsigned int major;
66 unsigned int minor;
67 unsigned int buildnr;
68 unsigned int number;
69 unsigned int type;
70 unsigned int spec_major;
71 unsigned int spec_minor;
72};
73
74/**
75 * struct kempld_device_data - Internal representation of the PLD device
76 * @io_base: Pointer to the IO memory
77 * @io_index: Pointer to the IO index register
78 * @io_data: Pointer to the IO data register
79 * @pld_clock: PLD clock frequency
80 * @feature_mask: PLD feature mask
81 * @dev: Pointer to kernel device structure
82 * @info: KEMPLD info structure
83 * @lock: PLD mutex
84 */
85struct kempld_device_data {
86 void __iomem *io_base;
87 void __iomem *io_index;
88 void __iomem *io_data;
89 u32 pld_clock;
90 u32 feature_mask;
91 struct device *dev;
92 struct kempld_info info;
93 struct mutex lock;
94};
95
96/**
97 * struct kempld_platform_data - PLD hardware configuration structure
98 * @pld_clock: PLD clock frequency
99 * @gpio_base GPIO base pin number
100 * @ioresource: IO addresses of the PLD
101 * @get_mutex: PLD specific get_mutex callback
102 * @release_mutex: PLD specific release_mutex callback
103 * @get_info: PLD specific get_info callback
104 * @register_cells: PLD specific register_cells callback
105 */
106struct kempld_platform_data {
107 u32 pld_clock;
108 int gpio_base;
109 struct resource *ioresource;
110 void (*get_hardware_mutex) (struct kempld_device_data *);
111 void (*release_hardware_mutex) (struct kempld_device_data *);
112 int (*get_info) (struct kempld_device_data *);
113 int (*register_cells) (struct kempld_device_data *);
114};
115
116extern void kempld_get_mutex(struct kempld_device_data *pld);
117extern void kempld_release_mutex(struct kempld_device_data *pld);
118extern u8 kempld_read8(struct kempld_device_data *pld, u8 index);
119extern void kempld_write8(struct kempld_device_data *pld, u8 index, u8 data);
120extern u16 kempld_read16(struct kempld_device_data *pld, u8 index);
121extern void kempld_write16(struct kempld_device_data *pld, u8 index, u16 data);
122extern u32 kempld_read32(struct kempld_device_data *pld, u8 index);
123extern void kempld_write32(struct kempld_device_data *pld, u8 index, u32 data);
124
125#endif /* _LINUX_MFD_KEMPLD_H_ */
diff --git a/include/linux/mfd/max77693-private.h b/include/linux/mfd/max77693-private.h
index 1aa4f13cdfa6..244fb0d51589 100644
--- a/include/linux/mfd/max77693-private.h
+++ b/include/linux/mfd/max77693-private.h
@@ -85,6 +85,19 @@ enum max77693_pmic_reg {
85 MAX77693_PMIC_REG_END, 85 MAX77693_PMIC_REG_END,
86}; 86};
87 87
88/* MAX77693 CHG_CNFG_00 register */
89#define CHG_CNFG_00_CHG_MASK 0x1
90#define CHG_CNFG_00_BUCK_MASK 0x4
91
92/* MAX77693 CHG_CNFG_09 Register */
93#define CHG_CNFG_09_CHGIN_ILIM_MASK 0x7F
94
95/* MAX77693 CHG_CTRL Register */
96#define SAFEOUT_CTRL_SAFEOUT1_MASK 0x3
97#define SAFEOUT_CTRL_SAFEOUT2_MASK 0xC
98#define SAFEOUT_CTRL_ENSAFEOUT1_MASK 0x40
99#define SAFEOUT_CTRL_ENSAFEOUT2_MASK 0x80
100
88/* Slave addr = 0x4A: MUIC */ 101/* Slave addr = 0x4A: MUIC */
89enum max77693_muic_reg { 102enum max77693_muic_reg {
90 MAX77693_MUIC_REG_ID = 0x00, 103 MAX77693_MUIC_REG_ID = 0x00,
diff --git a/include/linux/mfd/max77693.h b/include/linux/mfd/max77693.h
index 3109a6c5c948..676f0f388992 100644
--- a/include/linux/mfd/max77693.h
+++ b/include/linux/mfd/max77693.h
@@ -30,6 +30,20 @@
30#ifndef __LINUX_MFD_MAX77693_H 30#ifndef __LINUX_MFD_MAX77693_H
31#define __LINUX_MFD_MAX77693_H 31#define __LINUX_MFD_MAX77693_H
32 32
33/* MAX77686 regulator IDs */
34enum max77693_regulators {
35 MAX77693_ESAFEOUT1 = 0,
36 MAX77693_ESAFEOUT2,
37 MAX77693_CHARGER,
38 MAX77693_REG_MAX,
39};
40
41struct max77693_regulator_data {
42 int id;
43 struct regulator_init_data *initdata;
44 struct device_node *of_node;
45};
46
33struct max77693_reg_data { 47struct max77693_reg_data {
34 u8 addr; 48 u8 addr;
35 u8 data; 49 u8 data;
@@ -52,6 +66,10 @@ struct max77693_muic_platform_data {
52struct max77693_platform_data { 66struct max77693_platform_data {
53 int wakeup; 67 int wakeup;
54 68
69 /* regulator data */
70 struct max77693_regulator_data *regulators;
71 int num_regulators;
72
55 /* muic data */ 73 /* muic data */
56 struct max77693_muic_platform_data *muic_data; 74 struct max77693_muic_platform_data *muic_data;
57}; 75};
diff --git a/include/linux/mfd/max8998-private.h b/include/linux/mfd/max8998-private.h
index effa5d3b96ae..84844e0a5704 100644
--- a/include/linux/mfd/max8998-private.h
+++ b/include/linux/mfd/max8998-private.h
@@ -132,9 +132,12 @@ enum {
132 132
133#define MAX8998_ENRAMP (1 << 4) 133#define MAX8998_ENRAMP (1 << 4)
134 134
135struct irq_domain;
136
135/** 137/**
136 * struct max8998_dev - max8998 master device for sub-drivers 138 * struct max8998_dev - max8998 master device for sub-drivers
137 * @dev: master device of the chip (can be used to access platform data) 139 * @dev: master device of the chip (can be used to access platform data)
140 * @pdata: platform data for the driver and subdrivers
138 * @i2c: i2c client private data for regulator 141 * @i2c: i2c client private data for regulator
139 * @rtc: i2c client private data for rtc 142 * @rtc: i2c client private data for rtc
140 * @iolock: mutex for serializing io access 143 * @iolock: mutex for serializing io access
@@ -148,12 +151,14 @@ enum {
148 */ 151 */
149struct max8998_dev { 152struct max8998_dev {
150 struct device *dev; 153 struct device *dev;
154 struct max8998_platform_data *pdata;
151 struct i2c_client *i2c; 155 struct i2c_client *i2c;
152 struct i2c_client *rtc; 156 struct i2c_client *rtc;
153 struct mutex iolock; 157 struct mutex iolock;
154 struct mutex irqlock; 158 struct mutex irqlock;
155 159
156 int irq_base; 160 unsigned int irq_base;
161 struct irq_domain *irq_domain;
157 int irq; 162 int irq;
158 int ono; 163 int ono;
159 u8 irq_masks_cur[MAX8998_NUM_IRQ_REGS]; 164 u8 irq_masks_cur[MAX8998_NUM_IRQ_REGS];
diff --git a/include/linux/mfd/max8998.h b/include/linux/mfd/max8998.h
index 6823548d0c0a..e3956a654cbc 100644
--- a/include/linux/mfd/max8998.h
+++ b/include/linux/mfd/max8998.h
@@ -58,10 +58,12 @@ enum {
58 * max8998_regulator_data - regulator data 58 * max8998_regulator_data - regulator data
59 * @id: regulator id 59 * @id: regulator id
60 * @initdata: regulator init data (contraints, supplies, ...) 60 * @initdata: regulator init data (contraints, supplies, ...)
61 * @reg_node: DT node of regulator (unused on non-DT platforms)
61 */ 62 */
62struct max8998_regulator_data { 63struct max8998_regulator_data {
63 int id; 64 int id;
64 struct regulator_init_data *initdata; 65 struct regulator_init_data *initdata;
66 struct device_node *reg_node;
65}; 67};
66 68
67/** 69/**
@@ -73,12 +75,8 @@ struct max8998_regulator_data {
73 * @buck_voltage_lock: Do NOT change the values of the following six 75 * @buck_voltage_lock: Do NOT change the values of the following six
74 * registers set by buck?_voltage?. The voltage of BUCK1/2 cannot 76 * registers set by buck?_voltage?. The voltage of BUCK1/2 cannot
75 * be other than the preset values. 77 * be other than the preset values.
76 * @buck1_voltage1: BUCK1 DVS mode 1 voltage register 78 * @buck1_voltage: BUCK1 DVS mode 1 voltage registers
77 * @buck1_voltage2: BUCK1 DVS mode 2 voltage register 79 * @buck2_voltage: BUCK2 DVS mode 2 voltage registers
78 * @buck1_voltage3: BUCK1 DVS mode 3 voltage register
79 * @buck1_voltage4: BUCK1 DVS mode 4 voltage register
80 * @buck2_voltage1: BUCK2 DVS mode 1 voltage register
81 * @buck2_voltage2: BUCK2 DVS mode 2 voltage register
82 * @buck1_set1: BUCK1 gpio pin 1 to set output voltage 80 * @buck1_set1: BUCK1 gpio pin 1 to set output voltage
83 * @buck1_set2: BUCK1 gpio pin 2 to set output voltage 81 * @buck1_set2: BUCK1 gpio pin 2 to set output voltage
84 * @buck1_default_idx: Default for BUCK1 gpio pin 1, 2 82 * @buck1_default_idx: Default for BUCK1 gpio pin 1, 2
@@ -100,15 +98,11 @@ struct max8998_regulator_data {
100struct max8998_platform_data { 98struct max8998_platform_data {
101 struct max8998_regulator_data *regulators; 99 struct max8998_regulator_data *regulators;
102 int num_regulators; 100 int num_regulators;
103 int irq_base; 101 unsigned int irq_base;
104 int ono; 102 int ono;
105 bool buck_voltage_lock; 103 bool buck_voltage_lock;
106 int buck1_voltage1; 104 int buck1_voltage[4];
107 int buck1_voltage2; 105 int buck2_voltage[2];
108 int buck1_voltage3;
109 int buck1_voltage4;
110 int buck2_voltage1;
111 int buck2_voltage2;
112 int buck1_set1; 106 int buck1_set1;
113 int buck1_set2; 107 int buck1_set2;
114 int buck1_default_idx; 108 int buck1_default_idx;
diff --git a/include/linux/mfd/mc13xxx.h b/include/linux/mfd/mc13xxx.h
index bf070755982e..41ed59276c00 100644
--- a/include/linux/mfd/mc13xxx.h
+++ b/include/linux/mfd/mc13xxx.h
@@ -78,20 +78,30 @@ struct mc13xxx_regulator_platform_data {
78 struct mc13xxx_regulator_init_data *regulators; 78 struct mc13xxx_regulator_init_data *regulators;
79}; 79};
80 80
81enum {
82 /* MC13783 LED IDs */
83 MC13783_LED_MD,
84 MC13783_LED_AD,
85 MC13783_LED_KP,
86 MC13783_LED_R1,
87 MC13783_LED_G1,
88 MC13783_LED_B1,
89 MC13783_LED_R2,
90 MC13783_LED_G2,
91 MC13783_LED_B2,
92 MC13783_LED_R3,
93 MC13783_LED_G3,
94 MC13783_LED_B3,
95 /* MC13892 LED IDs */
96 MC13892_LED_MD,
97 MC13892_LED_AD,
98 MC13892_LED_KP,
99 MC13892_LED_R,
100 MC13892_LED_G,
101 MC13892_LED_B,
102};
103
81struct mc13xxx_led_platform_data { 104struct mc13xxx_led_platform_data {
82#define MC13783_LED_MD 0
83#define MC13783_LED_AD 1
84#define MC13783_LED_KP 2
85#define MC13783_LED_R1 3
86#define MC13783_LED_G1 4
87#define MC13783_LED_B1 5
88#define MC13783_LED_R2 6
89#define MC13783_LED_G2 7
90#define MC13783_LED_B2 8
91#define MC13783_LED_R3 9
92#define MC13783_LED_G3 10
93#define MC13783_LED_B3 11
94#define MC13783_LED_MAX MC13783_LED_B3
95 int id; 105 int id;
96 const char *name; 106 const char *name;
97 const char *default_trigger; 107 const char *default_trigger;
@@ -100,46 +110,36 @@ struct mc13xxx_led_platform_data {
100 char max_current; 110 char max_current;
101}; 111};
102 112
113#define MAX_LED_CONTROL_REGS 6
114
103struct mc13xxx_leds_platform_data { 115struct mc13xxx_leds_platform_data {
104 int num_leds;
105 struct mc13xxx_led_platform_data *led; 116 struct mc13xxx_led_platform_data *led;
117 int num_leds;
106 118
107#define MC13783_LED_TRIODE_MD (1 << 0) 119/* LED Control 0 */
108#define MC13783_LED_TRIODE_AD (1 << 1) 120#define MC13783_LED_C0_ENABLE (1 << 0)
109#define MC13783_LED_TRIODE_KP (1 << 2) 121#define MC13783_LED_C0_TRIODE_MD (1 << 7)
110#define MC13783_LED_BOOST_EN (1 << 3) 122#define MC13783_LED_C0_TRIODE_AD (1 << 8)
111#define MC13783_LED_TC1HALF (1 << 4) 123#define MC13783_LED_C0_TRIODE_KP (1 << 9)
112#define MC13783_LED_SLEWLIMTC (1 << 5) 124#define MC13783_LED_C0_BOOST (1 << 10)
113#define MC13783_LED_SLEWLIMBL (1 << 6) 125#define MC13783_LED_C0_ABMODE(x) (((x) & 0x7) << 11)
114#define MC13783_LED_TRIODE_TC1 (1 << 7) 126#define MC13783_LED_C0_ABREF(x) (((x) & 0x3) << 14)
115#define MC13783_LED_TRIODE_TC2 (1 << 8) 127/* LED Control 1 */
116#define MC13783_LED_TRIODE_TC3 (1 << 9) 128#define MC13783_LED_C1_TC1HALF (1 << 18)
117 int flags; 129#define MC13783_LED_C1_SLEWLIM (1 << 23)
118 130/* LED Control 2 */
119#define MC13783_LED_AB_DISABLED 0 131#define MC13783_LED_C2_PERIOD(x) (((x) & 0x3) << 21)
120#define MC13783_LED_AB_MD1 1 132#define MC13783_LED_C2_SLEWLIM (1 << 23)
121#define MC13783_LED_AB_MD12 2 133/* LED Control 3 */
122#define MC13783_LED_AB_MD123 3 134#define MC13783_LED_C3_PERIOD(x) (((x) & 0x3) << 21)
123#define MC13783_LED_AB_MD1234 4 135#define MC13783_LED_C3_TRIODE_TC1 (1 << 23)
124#define MC13783_LED_AB_MD1234_AD1 5 136/* LED Control 4 */
125#define MC13783_LED_AB_MD1234_AD12 6 137#define MC13783_LED_C4_PERIOD(x) (((x) & 0x3) << 21)
126#define MC13783_LED_AB_MD1_AD 7 138#define MC13783_LED_C4_TRIODE_TC2 (1 << 23)
127 char abmode; 139/* LED Control 5 */
128 140#define MC13783_LED_C5_PERIOD(x) (((x) & 0x3) << 21)
129#define MC13783_LED_ABREF_200MV 0 141#define MC13783_LED_C5_TRIODE_TC3 (1 << 23)
130#define MC13783_LED_ABREF_400MV 1 142 u32 led_control[MAX_LED_CONTROL_REGS];
131#define MC13783_LED_ABREF_600MV 2
132#define MC13783_LED_ABREF_800MV 3
133 char abref;
134
135#define MC13783_LED_PERIOD_10MS 0
136#define MC13783_LED_PERIOD_100MS 1
137#define MC13783_LED_PERIOD_500MS 2
138#define MC13783_LED_PERIOD_2S 3
139 char bl_period;
140 char tc1_period;
141 char tc2_period;
142 char tc3_period;
143}; 143};
144 144
145struct mc13xxx_buttons_platform_data { 145struct mc13xxx_buttons_platform_data {
diff --git a/include/linux/mfd/mcp.h b/include/linux/mfd/mcp.h
index a9e8bd157673..f682953043ba 100644
--- a/include/linux/mfd/mcp.h
+++ b/include/linux/mfd/mcp.h
@@ -10,6 +10,8 @@
10#ifndef MCP_H 10#ifndef MCP_H
11#define MCP_H 11#define MCP_H
12 12
13#include <linux/device.h>
14
13struct mcp_ops; 15struct mcp_ops;
14 16
15struct mcp { 17struct mcp {
diff --git a/include/linux/mfd/palmas.h b/include/linux/mfd/palmas.h
index 8f21daf62fb5..9974e387e483 100644
--- a/include/linux/mfd/palmas.h
+++ b/include/linux/mfd/palmas.h
@@ -20,6 +20,8 @@
20#include <linux/leds.h> 20#include <linux/leds.h>
21#include <linux/regmap.h> 21#include <linux/regmap.h>
22#include <linux/regulator/driver.h> 22#include <linux/regulator/driver.h>
23#include <linux/extcon.h>
24#include <linux/usb/phy_companion.h>
23 25
24#define PALMAS_NUM_CLIENTS 3 26#define PALMAS_NUM_CLIENTS 3
25 27
@@ -32,11 +34,30 @@
32 ((a) == PALMAS_CHIP_ID)) 34 ((a) == PALMAS_CHIP_ID))
33#define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID) 35#define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID)
34 36
37/**
38 * Palmas PMIC feature types
39 *
40 * PALMAS_PMIC_FEATURE_SMPS10_BOOST - used when the PMIC provides SMPS10_BOOST
41 * regulator.
42 *
43 * PALMAS_PMIC_HAS(b, f) - macro to check if a bandgap device is capable of a
44 * specific feature (above) or not. Return non-zero, if yes.
45 */
46#define PALMAS_PMIC_FEATURE_SMPS10_BOOST BIT(0)
47#define PALMAS_PMIC_HAS(b, f) \
48 ((b)->features & PALMAS_PMIC_FEATURE_ ## f)
49
35struct palmas_pmic; 50struct palmas_pmic;
36struct palmas_gpadc; 51struct palmas_gpadc;
37struct palmas_resource; 52struct palmas_resource;
38struct palmas_usb; 53struct palmas_usb;
39 54
55enum palmas_usb_state {
56 PALMAS_USB_STATE_DISCONNECT,
57 PALMAS_USB_STATE_VBUS,
58 PALMAS_USB_STATE_ID,
59};
60
40struct palmas { 61struct palmas {
41 struct device *dev; 62 struct device *dev;
42 63
@@ -46,6 +67,7 @@ struct palmas {
46 /* Stored chip id */ 67 /* Stored chip id */
47 int id; 68 int id;
48 69
70 unsigned int features;
49 /* IRQ Data */ 71 /* IRQ Data */
50 int irq; 72 int irq;
51 u32 irq_mask; 73 u32 irq_mask;
@@ -138,7 +160,8 @@ enum palmas_regulators {
138 PALMAS_REG_SMPS7, 160 PALMAS_REG_SMPS7,
139 PALMAS_REG_SMPS8, 161 PALMAS_REG_SMPS8,
140 PALMAS_REG_SMPS9, 162 PALMAS_REG_SMPS9,
141 PALMAS_REG_SMPS10, 163 PALMAS_REG_SMPS10_OUT2,
164 PALMAS_REG_SMPS10_OUT1,
142 /* LDO regulators */ 165 /* LDO regulators */
143 PALMAS_REG_LDO1, 166 PALMAS_REG_LDO1,
144 PALMAS_REG_LDO2, 167 PALMAS_REG_LDO2,
@@ -161,6 +184,50 @@ enum palmas_regulators {
161 PALMAS_NUM_REGS, 184 PALMAS_NUM_REGS,
162}; 185};
163 186
187/* External controll signal name */
188enum {
189 PALMAS_EXT_CONTROL_ENABLE1 = 0x1,
190 PALMAS_EXT_CONTROL_ENABLE2 = 0x2,
191 PALMAS_EXT_CONTROL_NSLEEP = 0x4,
192};
193
194/*
195 * Palmas device resources can be controlled externally for
196 * enabling/disabling it rather than register write through i2c.
197 * Add the external controlled requestor ID for different resources.
198 */
199enum palmas_external_requestor_id {
200 PALMAS_EXTERNAL_REQSTR_ID_REGEN1,
201 PALMAS_EXTERNAL_REQSTR_ID_REGEN2,
202 PALMAS_EXTERNAL_REQSTR_ID_SYSEN1,
203 PALMAS_EXTERNAL_REQSTR_ID_SYSEN2,
204 PALMAS_EXTERNAL_REQSTR_ID_CLK32KG,
205 PALMAS_EXTERNAL_REQSTR_ID_CLK32KGAUDIO,
206 PALMAS_EXTERNAL_REQSTR_ID_REGEN3,
207 PALMAS_EXTERNAL_REQSTR_ID_SMPS12,
208 PALMAS_EXTERNAL_REQSTR_ID_SMPS3,
209 PALMAS_EXTERNAL_REQSTR_ID_SMPS45,
210 PALMAS_EXTERNAL_REQSTR_ID_SMPS6,
211 PALMAS_EXTERNAL_REQSTR_ID_SMPS7,
212 PALMAS_EXTERNAL_REQSTR_ID_SMPS8,
213 PALMAS_EXTERNAL_REQSTR_ID_SMPS9,
214 PALMAS_EXTERNAL_REQSTR_ID_SMPS10,
215 PALMAS_EXTERNAL_REQSTR_ID_LDO1,
216 PALMAS_EXTERNAL_REQSTR_ID_LDO2,
217 PALMAS_EXTERNAL_REQSTR_ID_LDO3,
218 PALMAS_EXTERNAL_REQSTR_ID_LDO4,
219 PALMAS_EXTERNAL_REQSTR_ID_LDO5,
220 PALMAS_EXTERNAL_REQSTR_ID_LDO6,
221 PALMAS_EXTERNAL_REQSTR_ID_LDO7,
222 PALMAS_EXTERNAL_REQSTR_ID_LDO8,
223 PALMAS_EXTERNAL_REQSTR_ID_LDO9,
224 PALMAS_EXTERNAL_REQSTR_ID_LDOLN,
225 PALMAS_EXTERNAL_REQSTR_ID_LDOUSB,
226
227 /* Last entry */
228 PALMAS_EXTERNAL_REQSTR_ID_MAX,
229};
230
164struct palmas_pmic_platform_data { 231struct palmas_pmic_platform_data {
165 /* An array of pointers to regulator init data indexed by regulator 232 /* An array of pointers to regulator init data indexed by regulator
166 * ID 233 * ID
@@ -180,9 +247,6 @@ struct palmas_pmic_platform_data {
180}; 247};
181 248
182struct palmas_usb_platform_data { 249struct palmas_usb_platform_data {
183 /* Set this if platform wishes its own vbus control */
184 int no_control_vbus;
185
186 /* Do we enable the wakeup comparator on probe */ 250 /* Do we enable the wakeup comparator on probe */
187 int wakeup; 251 int wakeup;
188}; 252};
@@ -239,6 +303,7 @@ struct palmas_platform_data {
239 */ 303 */
240 int mux_from_pdata; 304 int mux_from_pdata;
241 u8 pad1, pad2; 305 u8 pad1, pad2;
306 bool pm_off;
242 307
243 struct palmas_pmic_platform_data *pmic_pdata; 308 struct palmas_pmic_platform_data *pmic_pdata;
244 struct palmas_gpadc_platform_data *gpadc_pdata; 309 struct palmas_gpadc_platform_data *gpadc_pdata;
@@ -336,9 +401,9 @@ struct palmas_pmic {
336 int smps123; 401 int smps123;
337 int smps457; 402 int smps457;
338 403
339 int range[PALMAS_REG_SMPS10]; 404 int range[PALMAS_REG_SMPS10_OUT1];
340 unsigned int ramp_delay[PALMAS_REG_SMPS10]; 405 unsigned int ramp_delay[PALMAS_REG_SMPS10_OUT1];
341 unsigned int current_reg_mode[PALMAS_REG_SMPS10]; 406 unsigned int current_reg_mode[PALMAS_REG_SMPS10_OUT1];
342}; 407};
343 408
344struct palmas_resource { 409struct palmas_resource {
@@ -350,22 +415,17 @@ struct palmas_usb {
350 struct palmas *palmas; 415 struct palmas *palmas;
351 struct device *dev; 416 struct device *dev;
352 417
353 /* for vbus reporting with irqs disabled */ 418 struct extcon_dev edev;
354 spinlock_t lock;
355
356 struct regulator *vbus_reg;
357
358 /* used to set vbus, in atomic path */
359 struct work_struct set_vbus_work;
360 419
361 int irq1; 420 int id_otg_irq;
362 int irq2; 421 int id_irq;
363 int irq3; 422 int vbus_otg_irq;
364 int irq4; 423 int vbus_irq;
365 424
366 int vbus_enable; 425 enum palmas_usb_state linkstat;
367 426 int wakeup;
368 u8 linkstat; 427 bool enable_vbus_detection;
428 bool enable_id_detection;
369}; 429};
370 430
371#define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator) 431#define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator)
@@ -433,7 +493,7 @@ enum usb_irq_events {
433#define PALMAS_DVFS_BASE 0x180 493#define PALMAS_DVFS_BASE 0x180
434#define PALMAS_PMU_CONTROL_BASE 0x1A0 494#define PALMAS_PMU_CONTROL_BASE 0x1A0
435#define PALMAS_RESOURCE_BASE 0x1D4 495#define PALMAS_RESOURCE_BASE 0x1D4
436#define PALMAS_PU_PD_OD_BASE 0x1F4 496#define PALMAS_PU_PD_OD_BASE 0x1F0
437#define PALMAS_LED_BASE 0x200 497#define PALMAS_LED_BASE 0x200
438#define PALMAS_INTERRUPT_BASE 0x210 498#define PALMAS_INTERRUPT_BASE 0x210
439#define PALMAS_USB_OTG_BASE 0x250 499#define PALMAS_USB_OTG_BASE 0x250
@@ -1718,16 +1778,20 @@ enum usb_irq_events {
1718#define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0 1778#define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0
1719 1779
1720/* Registers for function PAD_CONTROL */ 1780/* Registers for function PAD_CONTROL */
1721#define PALMAS_PU_PD_INPUT_CTRL1 0x0 1781#define PALMAS_OD_OUTPUT_CTRL2 0x2
1722#define PALMAS_PU_PD_INPUT_CTRL2 0x1 1782#define PALMAS_POLARITY_CTRL2 0x3
1723#define PALMAS_PU_PD_INPUT_CTRL3 0x2 1783#define PALMAS_PU_PD_INPUT_CTRL1 0x4
1724#define PALMAS_OD_OUTPUT_CTRL 0x4 1784#define PALMAS_PU_PD_INPUT_CTRL2 0x5
1725#define PALMAS_POLARITY_CTRL 0x5 1785#define PALMAS_PU_PD_INPUT_CTRL3 0x6
1726#define PALMAS_PRIMARY_SECONDARY_PAD1 0x6 1786#define PALMAS_PU_PD_INPUT_CTRL5 0x7
1727#define PALMAS_PRIMARY_SECONDARY_PAD2 0x7 1787#define PALMAS_OD_OUTPUT_CTRL 0x8
1728#define PALMAS_I2C_SPI 0x8 1788#define PALMAS_POLARITY_CTRL 0x9
1729#define PALMAS_PU_PD_INPUT_CTRL4 0x9 1789#define PALMAS_PRIMARY_SECONDARY_PAD1 0xA
1730#define PALMAS_PRIMARY_SECONDARY_PAD3 0xA 1790#define PALMAS_PRIMARY_SECONDARY_PAD2 0xB
1791#define PALMAS_I2C_SPI 0xC
1792#define PALMAS_PU_PD_INPUT_CTRL4 0xD
1793#define PALMAS_PRIMARY_SECONDARY_PAD3 0xE
1794#define PALMAS_PRIMARY_SECONDARY_PAD4 0xF
1731 1795
1732/* Bit definitions for PU_PD_INPUT_CTRL1 */ 1796/* Bit definitions for PU_PD_INPUT_CTRL1 */
1733#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40 1797#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40
@@ -2485,6 +2549,15 @@ enum usb_irq_events {
2485#define PALMAS_PU_PD_GPIO_CTRL1 0x6 2549#define PALMAS_PU_PD_GPIO_CTRL1 0x6
2486#define PALMAS_PU_PD_GPIO_CTRL2 0x7 2550#define PALMAS_PU_PD_GPIO_CTRL2 0x7
2487#define PALMAS_OD_OUTPUT_GPIO_CTRL 0x8 2551#define PALMAS_OD_OUTPUT_GPIO_CTRL 0x8
2552#define PALMAS_GPIO_DATA_IN2 0x9
2553#define PALMAS_GPIO_DATA_DIR2 0x0A
2554#define PALMAS_GPIO_DATA_OUT2 0x0B
2555#define PALMAS_GPIO_DEBOUNCE_EN2 0x0C
2556#define PALMAS_GPIO_CLEAR_DATA_OUT2 0x0D
2557#define PALMAS_GPIO_SET_DATA_OUT2 0x0E
2558#define PALMAS_PU_PD_GPIO_CTRL3 0x0F
2559#define PALMAS_PU_PD_GPIO_CTRL4 0x10
2560#define PALMAS_OD_OUTPUT_GPIO_CTRL2 0x11
2488 2561
2489/* Bit definitions for GPIO_DATA_IN */ 2562/* Bit definitions for GPIO_DATA_IN */
2490#define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80 2563#define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80
@@ -2850,4 +2923,9 @@ static inline int palmas_irq_get_virq(struct palmas *palmas, int irq)
2850 return regmap_irq_get_virq(palmas->irq_data, irq); 2923 return regmap_irq_get_virq(palmas->irq_data, irq);
2851} 2924}
2852 2925
2926
2927int palmas_ext_control_req_config(struct palmas *palmas,
2928 enum palmas_external_requestor_id ext_control_req_id,
2929 int ext_ctrl, bool enable);
2930
2853#endif /* __LINUX_MFD_PALMAS_H */ 2931#endif /* __LINUX_MFD_PALMAS_H */
diff --git a/include/linux/mfd/rtsx_common.h b/include/linux/mfd/rtsx_common.h
index 2b13970596f5..443176ee1ab0 100644
--- a/include/linux/mfd/rtsx_common.h
+++ b/include/linux/mfd/rtsx_common.h
@@ -1,6 +1,6 @@
1/* Driver for Realtek driver-based card reader 1/* Driver for Realtek driver-based card reader
2 * 2 *
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved. 3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the 6 * under the terms of the GNU General Public License as published by the
@@ -17,7 +17,6 @@
17 * 17 *
18 * Author: 18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn> 19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21 */ 20 */
22 21
23#ifndef __RTSX_COMMON_H 22#ifndef __RTSX_COMMON_H
diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h
index 86bc635f8385..d1382dfbeff0 100644
--- a/include/linux/mfd/rtsx_pci.h
+++ b/include/linux/mfd/rtsx_pci.h
@@ -1,6 +1,6 @@
1/* Driver for Realtek PCI-Express card reader 1/* Driver for Realtek PCI-Express card reader
2 * 2 *
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved. 3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the 6 * under the terms of the GNU General Public License as published by the
@@ -17,7 +17,6 @@
17 * 17 *
18 * Author: 18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn> 19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21 */ 20 */
22 21
23#ifndef __RTSX_PCI_H 22#ifndef __RTSX_PCI_H
@@ -25,8 +24,7 @@
25 24
26#include <linux/sched.h> 25#include <linux/sched.h>
27#include <linux/pci.h> 26#include <linux/pci.h>
28 27#include <linux/mfd/rtsx_common.h>
29#include "rtsx_common.h"
30 28
31#define MAX_RW_REG_CNT 1024 29#define MAX_RW_REG_CNT 1024
32 30
@@ -184,11 +182,26 @@
184#define CARD_SHARE_BAROSSA_SD 0x01 182#define CARD_SHARE_BAROSSA_SD 0x01
185#define CARD_SHARE_BAROSSA_MS 0x02 183#define CARD_SHARE_BAROSSA_MS 0x02
186 184
185/* CARD_DRIVE_SEL */
186#define MS_DRIVE_8mA (0x01 << 6)
187#define MMC_DRIVE_8mA (0x01 << 4)
188#define XD_DRIVE_8mA (0x01 << 2)
189#define GPIO_DRIVE_8mA 0x01
190#define RTS5209_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | MMC_DRIVE_8mA |\
191 XD_DRIVE_8mA | GPIO_DRIVE_8mA)
192#define RTL8411_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | MMC_DRIVE_8mA |\
193 XD_DRIVE_8mA)
194#define RTSX_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | GPIO_DRIVE_8mA)
195
187/* SD30_DRIVE_SEL */ 196/* SD30_DRIVE_SEL */
188#define DRIVER_TYPE_A 0x05 197#define DRIVER_TYPE_A 0x05
189#define DRIVER_TYPE_B 0x03 198#define DRIVER_TYPE_B 0x03
190#define DRIVER_TYPE_C 0x02 199#define DRIVER_TYPE_C 0x02
191#define DRIVER_TYPE_D 0x01 200#define DRIVER_TYPE_D 0x01
201#define CFG_DRIVER_TYPE_A 0x02
202#define CFG_DRIVER_TYPE_B 0x03
203#define CFG_DRIVER_TYPE_C 0x01
204#define CFG_DRIVER_TYPE_D 0x00
192 205
193/* FPDCTL */ 206/* FPDCTL */
194#define SSC_POWER_DOWN 0x01 207#define SSC_POWER_DOWN 0x01
@@ -521,6 +534,10 @@
521#define SAMPLE_VAR_CLK0 (0x01 << 4) 534#define SAMPLE_VAR_CLK0 (0x01 << 4)
522#define SAMPLE_VAR_CLK1 (0x02 << 4) 535#define SAMPLE_VAR_CLK1 (0x02 << 4)
523 536
537/* HOST_SLEEP_STATE */
538#define HOST_ENTER_S1 1
539#define HOST_ENTER_S3 2
540
524#define MS_CFG 0xFD40 541#define MS_CFG 0xFD40
525#define MS_TPC 0xFD41 542#define MS_TPC 0xFD41
526#define MS_TRANS_CFG 0xFD42 543#define MS_TRANS_CFG 0xFD42
@@ -575,6 +592,7 @@
575 592
576#define CARD_PWR_CTL 0xFD50 593#define CARD_PWR_CTL 0xFD50
577#define CARD_CLK_SWITCH 0xFD51 594#define CARD_CLK_SWITCH 0xFD51
595#define RTL8411B_PACKAGE_MODE 0xFD51
578#define CARD_SHARE_MODE 0xFD52 596#define CARD_SHARE_MODE 0xFD52
579#define CARD_DRIVE_SEL 0xFD53 597#define CARD_DRIVE_SEL 0xFD53
580#define CARD_STOP 0xFD54 598#define CARD_STOP 0xFD54
@@ -668,6 +686,7 @@
668#define PME_FORCE_CTL 0xFE56 686#define PME_FORCE_CTL 0xFE56
669#define ASPM_FORCE_CTL 0xFE57 687#define ASPM_FORCE_CTL 0xFE57
670#define PM_CLK_FORCE_CTL 0xFE58 688#define PM_CLK_FORCE_CTL 0xFE58
689#define FUNC_FORCE_CTL 0xFE59
671#define PERST_GLITCH_WIDTH 0xFE5C 690#define PERST_GLITCH_WIDTH 0xFE5C
672#define CHANGE_LINK_STATE 0xFE5B 691#define CHANGE_LINK_STATE 0xFE5B
673#define RESET_LOAD_REG 0xFE5E 692#define RESET_LOAD_REG 0xFE5E
@@ -683,6 +702,13 @@
683 702
684#define DUMMY_REG_RESET_0 0xFE90 703#define DUMMY_REG_RESET_0 0xFE90
685 704
705#define AUTOLOAD_CFG_BASE 0xFF00
706
707#define PM_CTRL1 0xFF44
708#define PM_CTRL2 0xFF45
709#define PM_CTRL3 0xFF46
710#define PM_CTRL4 0xFF47
711
686/* Memory mapping */ 712/* Memory mapping */
687#define SRAM_BASE 0xE600 713#define SRAM_BASE 0xE600
688#define RBUF_BASE 0xF400 714#define RBUF_BASE 0xF400
@@ -725,6 +751,11 @@
725#define PHY_FLD4 0x1E 751#define PHY_FLD4 0x1E
726#define PHY_DUM_REG 0x1F 752#define PHY_DUM_REG 0x1F
727 753
754#define LCTLR 0x80
755#define PCR_SETTING_REG1 0x724
756#define PCR_SETTING_REG2 0x814
757#define PCR_SETTING_REG3 0x747
758
728#define rtsx_pci_init_cmd(pcr) ((pcr)->ci = 0) 759#define rtsx_pci_init_cmd(pcr) ((pcr)->ci = 0)
729 760
730struct rtsx_pcr; 761struct rtsx_pcr;
@@ -746,6 +777,8 @@ struct pcr_ops {
746 u8 voltage); 777 u8 voltage);
747 unsigned int (*cd_deglitch)(struct rtsx_pcr *pcr); 778 unsigned int (*cd_deglitch)(struct rtsx_pcr *pcr);
748 int (*conv_clk_and_div_n)(int clk, int dir); 779 int (*conv_clk_and_div_n)(int clk, int dir);
780 void (*fetch_vendor_settings)(struct rtsx_pcr *pcr);
781 void (*force_power_down)(struct rtsx_pcr *pcr, u8 pm_state);
749}; 782};
750 783
751enum PDEV_STAT {PDEV_STAT_IDLE, PDEV_STAT_RUN}; 784enum PDEV_STAT {PDEV_STAT_IDLE, PDEV_STAT_RUN};
@@ -787,7 +820,6 @@ struct rtsx_pcr {
787 struct completion *finish_me; 820 struct completion *finish_me;
788 821
789 unsigned int cur_clock; 822 unsigned int cur_clock;
790 bool ms_pmos;
791 bool remove_pci; 823 bool remove_pci;
792 bool msi_en; 824 bool msi_en;
793 825
@@ -805,6 +837,19 @@ struct rtsx_pcr {
805#define IC_VER_D 3 837#define IC_VER_D 3
806 u8 ic_version; 838 u8 ic_version;
807 839
840 u8 sd30_drive_sel_1v8;
841 u8 sd30_drive_sel_3v3;
842 u8 card_drive_sel;
843#define ASPM_L1_EN 0x02
844 u8 aspm_en;
845
846#define PCR_MS_PMOS (1 << 0)
847#define PCR_REVERSE_SOCKET (1 << 1)
848 u32 flags;
849
850 u32 tx_initial_phase;
851 u32 rx_initial_phase;
852
808 const u32 *sd_pull_ctl_enable_tbl; 853 const u32 *sd_pull_ctl_enable_tbl;
809 const u32 *sd_pull_ctl_disable_tbl; 854 const u32 *sd_pull_ctl_disable_tbl;
810 const u32 *ms_pull_ctl_enable_tbl; 855 const u32 *ms_pull_ctl_enable_tbl;
@@ -821,6 +866,18 @@ struct rtsx_pcr {
821#define PCI_VID(pcr) ((pcr)->pci->vendor) 866#define PCI_VID(pcr) ((pcr)->pci->vendor)
822#define PCI_PID(pcr) ((pcr)->pci->device) 867#define PCI_PID(pcr) ((pcr)->pci->device)
823 868
869#define SDR104_PHASE(val) ((val) & 0xFF)
870#define SDR50_PHASE(val) (((val) >> 8) & 0xFF)
871#define DDR50_PHASE(val) (((val) >> 16) & 0xFF)
872#define SDR104_TX_PHASE(pcr) SDR104_PHASE((pcr)->tx_initial_phase)
873#define SDR50_TX_PHASE(pcr) SDR50_PHASE((pcr)->tx_initial_phase)
874#define DDR50_TX_PHASE(pcr) DDR50_PHASE((pcr)->tx_initial_phase)
875#define SDR104_RX_PHASE(pcr) SDR104_PHASE((pcr)->rx_initial_phase)
876#define SDR50_RX_PHASE(pcr) SDR50_PHASE((pcr)->rx_initial_phase)
877#define DDR50_RX_PHASE(pcr) DDR50_PHASE((pcr)->rx_initial_phase)
878#define SET_CLOCK_PHASE(sdr104, sdr50, ddr50) \
879 (((ddr50) << 16) | ((sdr50) << 8) | (sdr104))
880
824void rtsx_pci_start_run(struct rtsx_pcr *pcr); 881void rtsx_pci_start_run(struct rtsx_pcr *pcr);
825int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data); 882int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data);
826int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data); 883int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data);
diff --git a/include/linux/mfd/samsung/core.h b/include/linux/mfd/samsung/core.h
index f0f4de3b4ccc..378ae8a04c6a 100644
--- a/include/linux/mfd/samsung/core.h
+++ b/include/linux/mfd/samsung/core.h
@@ -14,8 +14,6 @@
14#ifndef __LINUX_MFD_SEC_CORE_H 14#ifndef __LINUX_MFD_SEC_CORE_H
15#define __LINUX_MFD_SEC_CORE_H 15#define __LINUX_MFD_SEC_CORE_H
16 16
17#define NUM_IRQ_REGS 4
18
19enum sec_device_type { 17enum sec_device_type {
20 S5M8751X, 18 S5M8751X,
21 S5M8763X, 19 S5M8763X,
@@ -44,8 +42,6 @@ struct sec_pmic_dev {
44 struct regmap *regmap; 42 struct regmap *regmap;
45 struct i2c_client *i2c; 43 struct i2c_client *i2c;
46 struct i2c_client *rtc; 44 struct i2c_client *rtc;
47 struct mutex iolock;
48 struct mutex irqlock;
49 45
50 int device_type; 46 int device_type;
51 int irq_base; 47 int irq_base;
@@ -53,8 +49,6 @@ struct sec_pmic_dev {
53 struct regmap_irq_chip_data *irq_data; 49 struct regmap_irq_chip_data *irq_data;
54 50
55 int ono; 51 int ono;
56 u8 irq_masks_cur[NUM_IRQ_REGS];
57 u8 irq_masks_cache[NUM_IRQ_REGS];
58 int type; 52 int type;
59 bool wakeup; 53 bool wakeup;
60}; 54};
diff --git a/include/linux/mfd/samsung/s2mps11.h b/include/linux/mfd/samsung/s2mps11.h
index ad2252f239d7..b3ddf98dec37 100644
--- a/include/linux/mfd/samsung/s2mps11.h
+++ b/include/linux/mfd/samsung/s2mps11.h
@@ -167,11 +167,8 @@ enum s2mps11_regulators {
167 S2MPS11_BUCK8, 167 S2MPS11_BUCK8,
168 S2MPS11_BUCK9, 168 S2MPS11_BUCK9,
169 S2MPS11_BUCK10, 169 S2MPS11_BUCK10,
170 S2MPS11_AP_EN32KHZ,
171 S2MPS11_CP_EN32KHZ,
172 S2MPS11_BT_EN32KHZ,
173 170
174 S2MPS11_REG_MAX, 171 S2MPS11_REGULATOR_MAX,
175}; 172};
176 173
177#define S2MPS11_BUCK_MIN1 600000 174#define S2MPS11_BUCK_MIN1 600000
@@ -189,8 +186,19 @@ enum s2mps11_regulators {
189#define S2MPS11_ENABLE_SHIFT 0x06 186#define S2MPS11_ENABLE_SHIFT 0x06
190#define S2MPS11_LDO_N_VOLTAGES (S2MPS11_LDO_VSEL_MASK + 1) 187#define S2MPS11_LDO_N_VOLTAGES (S2MPS11_LDO_VSEL_MASK + 1)
191#define S2MPS11_BUCK_N_VOLTAGES (S2MPS11_BUCK_VSEL_MASK + 1) 188#define S2MPS11_BUCK_N_VOLTAGES (S2MPS11_BUCK_VSEL_MASK + 1)
189#define S2MPS11_RAMP_DELAY 25000 /* uV/us */
192 190
191
192#define S2MPS11_BUCK2_RAMP_SHIFT 6
193#define S2MPS11_BUCK34_RAMP_SHIFT 4
194#define S2MPS11_BUCK5_RAMP_SHIFT 6
195#define S2MPS11_BUCK16_RAMP_SHIFT 4
196#define S2MPS11_BUCK7810_RAMP_SHIFT 2
197#define S2MPS11_BUCK9_RAMP_SHIFT 0
198#define S2MPS11_BUCK2_RAMP_EN_SHIFT 3
199#define S2MPS11_BUCK3_RAMP_EN_SHIFT 2
200#define S2MPS11_BUCK4_RAMP_EN_SHIFT 1
201#define S2MPS11_BUCK6_RAMP_EN_SHIFT 0
193#define S2MPS11_PMIC_EN_SHIFT 6 202#define S2MPS11_PMIC_EN_SHIFT 6
194#define S2MPS11_REGULATOR_MAX (S2MPS11_REG_MAX - 3)
195 203
196#endif /* __LINUX_MFD_S2MPS11_H */ 204#endif /* __LINUX_MFD_S2MPS11_H */
diff --git a/include/linux/mfd/syscon/clps711x.h b/include/linux/mfd/syscon/clps711x.h
new file mode 100644
index 000000000000..26355abae515
--- /dev/null
+++ b/include/linux/mfd/syscon/clps711x.h
@@ -0,0 +1,94 @@
1/*
2 * CLPS711X system register bits definitions
3 *
4 * Copyright (C) 2013 Alexander Shiyan <shc_work@mail.ru>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#ifndef _LINUX_MFD_SYSCON_CLPS711X_H_
13#define _LINUX_MFD_SYSCON_CLPS711X_H_
14
15#define SYSCON_OFFSET (0x00)
16#define SYSFLG_OFFSET (0x40)
17
18#define SYSCON1_KBDSCAN(x) ((x) & 15)
19#define SYSCON1_KBDSCAN_MASK (15)
20#define SYSCON1_TC1M (1 << 4)
21#define SYSCON1_TC1S (1 << 5)
22#define SYSCON1_TC2M (1 << 6)
23#define SYSCON1_TC2S (1 << 7)
24#define SYSCON1_BZTOG (1 << 9)
25#define SYSCON1_BZMOD (1 << 10)
26#define SYSCON1_DBGEN (1 << 11)
27#define SYSCON1_LCDEN (1 << 12)
28#define SYSCON1_CDENTX (1 << 13)
29#define SYSCON1_CDENRX (1 << 14)
30#define SYSCON1_SIREN (1 << 15)
31#define SYSCON1_ADCKSEL(x) (((x) & 3) << 16)
32#define SYSCON1_ADCKSEL_MASK (3 << 16)
33#define SYSCON1_EXCKEN (1 << 18)
34#define SYSCON1_WAKEDIS (1 << 19)
35#define SYSCON1_IRTXM (1 << 20)
36
37#define SYSCON2_SERSEL (1 << 0)
38#define SYSCON2_KBD6 (1 << 1)
39#define SYSCON2_DRAMZ (1 << 2)
40#define SYSCON2_KBWEN (1 << 3)
41#define SYSCON2_SS2TXEN (1 << 4)
42#define SYSCON2_PCCARD1 (1 << 5)
43#define SYSCON2_PCCARD2 (1 << 6)
44#define SYSCON2_SS2RXEN (1 << 7)
45#define SYSCON2_SS2MAEN (1 << 9)
46#define SYSCON2_OSTB (1 << 12)
47#define SYSCON2_CLKENSL (1 << 13)
48#define SYSCON2_BUZFREQ (1 << 14)
49
50#define SYSCON3_ADCCON (1 << 0)
51#define SYSCON3_CLKCTL0 (1 << 1)
52#define SYSCON3_CLKCTL1 (1 << 2)
53#define SYSCON3_DAISEL (1 << 3)
54#define SYSCON3_ADCCKNSEN (1 << 4)
55#define SYSCON3_VERSN(x) (((x) >> 5) & 7)
56#define SYSCON3_VERSN_MASK (7 << 5)
57#define SYSCON3_FASTWAKE (1 << 8)
58#define SYSCON3_DAIEN (1 << 9)
59#define SYSCON3_128FS SYSCON3_DAIEN
60#define SYSCON3_ENPD67 (1 << 10)
61
62#define SYSCON_UARTEN (1 << 8)
63
64#define SYSFLG1_MCDR (1 << 0)
65#define SYSFLG1_DCDET (1 << 1)
66#define SYSFLG1_WUDR (1 << 2)
67#define SYSFLG1_WUON (1 << 3)
68#define SYSFLG1_CTS (1 << 8)
69#define SYSFLG1_DSR (1 << 9)
70#define SYSFLG1_DCD (1 << 10)
71#define SYSFLG1_NBFLG (1 << 12)
72#define SYSFLG1_RSTFLG (1 << 13)
73#define SYSFLG1_PFFLG (1 << 14)
74#define SYSFLG1_CLDFLG (1 << 15)
75#define SYSFLG1_CRXFE (1 << 24)
76#define SYSFLG1_CTXFF (1 << 25)
77#define SYSFLG1_SSIBUSY (1 << 26)
78#define SYSFLG1_ID (1 << 29)
79#define SYSFLG1_VERID(x) (((x) >> 30) & 3)
80#define SYSFLG1_VERID_MASK (3 << 30)
81
82#define SYSFLG2_SSRXOF (1 << 0)
83#define SYSFLG2_RESVAL (1 << 1)
84#define SYSFLG2_RESFRM (1 << 2)
85#define SYSFLG2_SS2RXFE (1 << 3)
86#define SYSFLG2_SS2TXFF (1 << 4)
87#define SYSFLG2_SS2TXUF (1 << 5)
88#define SYSFLG2_CKMODE (1 << 6)
89
90#define SYSFLG_UBUSY (1 << 11)
91#define SYSFLG_URXFE (1 << 22)
92#define SYSFLG_UTXFF (1 << 23)
93
94#endif
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
index dab34a1deb2c..b6bdcd66c07d 100644
--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -103,15 +103,15 @@
103#define IMX6Q_GPR1_EXC_MON_MASK BIT(22) 103#define IMX6Q_GPR1_EXC_MON_MASK BIT(22)
104#define IMX6Q_GPR1_EXC_MON_OKAY 0x0 104#define IMX6Q_GPR1_EXC_MON_OKAY 0x0
105#define IMX6Q_GPR1_EXC_MON_SLVE BIT(22) 105#define IMX6Q_GPR1_EXC_MON_SLVE BIT(22)
106#define IMX6Q_GPR1_MIPI_IPU2_SEL_MASK BIT(21) 106#define IMX6Q_GPR1_ENET_CLK_SEL_MASK BIT(21)
107#define IMX6Q_GPR1_MIPI_IPU2_SEL_GASKET 0x0 107#define IMX6Q_GPR1_ENET_CLK_SEL_PAD 0
108#define IMX6Q_GPR1_MIPI_IPU2_SEL_IOMUX BIT(21) 108#define IMX6Q_GPR1_ENET_CLK_SEL_ANATOP BIT(21)
109#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK BIT(20) 109#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK BIT(20)
110#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET 0x0
111#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX BIT(20)
112#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK BIT(19)
113#define IMX6Q_GPR1_MIPI_IPU2_MUX_GASKET 0x0 110#define IMX6Q_GPR1_MIPI_IPU2_MUX_GASKET 0x0
114#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX BIT(19) 111#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20)
112#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK BIT(19)
113#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET 0x0
114#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19)
115#define IMX6Q_GPR1_PCIE_TEST_PD BIT(18) 115#define IMX6Q_GPR1_PCIE_TEST_PD BIT(18)
116#define IMX6Q_GPR1_IPU_VPU_MUX_MASK BIT(17) 116#define IMX6Q_GPR1_IPU_VPU_MUX_MASK BIT(17)
117#define IMX6Q_GPR1_IPU_VPU_MUX_IPU1 0x0 117#define IMX6Q_GPR1_IPU_VPU_MUX_IPU1 0x0
@@ -279,41 +279,88 @@
279#define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29) 279#define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29)
280#define IMX6Q_GPR13_CAN1_STOP_REQ BIT(28) 280#define IMX6Q_GPR13_CAN1_STOP_REQ BIT(28)
281#define IMX6Q_GPR13_ENET_STOP_REQ BIT(27) 281#define IMX6Q_GPR13_ENET_STOP_REQ BIT(27)
282#define IMX6Q_GPR13_SATA_PHY_8_MASK (0x7 << 24) 282#define IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK (0x7 << 24)
283#define IMX6Q_GPR13_SATA_PHY_8_0_5_DB (0x0 << 24) 283#define IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB (0x0 << 24)
284#define IMX6Q_GPR13_SATA_PHY_8_1_0_DB (0x1 << 24) 284#define IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB (0x1 << 24)
285#define IMX6Q_GPR13_SATA_PHY_8_1_5_DB (0x2 << 24) 285#define IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB (0x2 << 24)
286#define IMX6Q_GPR13_SATA_PHY_8_2_0_DB (0x3 << 24) 286#define IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB (0x3 << 24)
287#define IMX6Q_GPR13_SATA_PHY_8_2_5_DB (0x4 << 24) 287#define IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB (0x4 << 24)
288#define IMX6Q_GPR13_SATA_PHY_8_3_0_DB (0x5 << 24) 288#define IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB (0x5 << 24)
289#define IMX6Q_GPR13_SATA_PHY_8_3_5_DB (0x6 << 24) 289#define IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB (0x6 << 24)
290#define IMX6Q_GPR13_SATA_PHY_8_4_0_DB (0x7 << 24) 290#define IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB (0x7 << 24)
291#define IMX6Q_GPR13_SATA_PHY_7_MASK (0x1f << 19) 291#define IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK (0x1f << 19)
292#define IMX6Q_GPR13_SATA_PHY_7_SATA1I (0x10 << 19) 292#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1I (0x10 << 19)
293#define IMX6Q_GPR13_SATA_PHY_7_SATA1M (0x10 << 19) 293#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1M (0x10 << 19)
294#define IMX6Q_GPR13_SATA_PHY_7_SATA1X (0x1a << 19) 294#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1X (0x1a << 19)
295#define IMX6Q_GPR13_SATA_PHY_7_SATA2I (0x12 << 19) 295#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2I (0x12 << 19)
296#define IMX6Q_GPR13_SATA_PHY_7_SATA2M (0x12 << 19) 296#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M (0x12 << 19)
297#define IMX6Q_GPR13_SATA_PHY_7_SATA2X (0x1a << 19) 297#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2X (0x1a << 19)
298#define IMX6Q_GPR13_SATA_PHY_6_MASK (0x7 << 16) 298#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK (0x7 << 16)
299#define IMX6Q_GPR13_SATA_SPEED_MASK BIT(15) 299#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_1F (0x0 << 16)
300#define IMX6Q_GPR13_SATA_SPEED_1P5G 0x0 300#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_2F (0x1 << 16)
301#define IMX6Q_GPR13_SATA_SPEED_3P0G BIT(15) 301#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_4F (0x2 << 16)
302#define IMX6Q_GPR13_SATA_PHY_5 BIT(14) 302#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F (0x3 << 16)
303#define IMX6Q_GPR13_SATA_PHY_4_MASK (0x7 << 11) 303#define IMX6Q_GPR13_SATA_SPD_MODE_MASK BIT(15)
304#define IMX6Q_GPR13_SATA_PHY_4_16_16 (0x0 << 11) 304#define IMX6Q_GPR13_SATA_SPD_MODE_1P5G 0x0
305#define IMX6Q_GPR13_SATA_PHY_4_14_16 (0x1 << 11) 305#define IMX6Q_GPR13_SATA_SPD_MODE_3P0G BIT(15)
306#define IMX6Q_GPR13_SATA_PHY_4_12_16 (0x2 << 11) 306#define IMX6Q_GPR13_SATA_MPLL_SS_EN BIT(14)
307#define IMX6Q_GPR13_SATA_PHY_4_10_16 (0x3 << 11) 307#define IMX6Q_GPR13_SATA_TX_ATTEN_MASK (0x7 << 11)
308#define IMX6Q_GPR13_SATA_PHY_4_9_16 (0x4 << 11) 308#define IMX6Q_GPR13_SATA_TX_ATTEN_16_16 (0x0 << 11)
309#define IMX6Q_GPR13_SATA_PHY_4_8_16 (0x5 << 11) 309#define IMX6Q_GPR13_SATA_TX_ATTEN_14_16 (0x1 << 11)
310#define IMX6Q_GPR13_SATA_PHY_3_MASK (0xf << 7) 310#define IMX6Q_GPR13_SATA_TX_ATTEN_12_16 (0x2 << 11)
311#define IMX6Q_GPR13_SATA_PHY_3_OFF 0x7 311#define IMX6Q_GPR13_SATA_TX_ATTEN_10_16 (0x3 << 11)
312#define IMX6Q_GPR13_SATA_PHY_2_MASK (0x1f << 2) 312#define IMX6Q_GPR13_SATA_TX_ATTEN_9_16 (0x4 << 11)
313#define IMX6Q_GPR13_SATA_PHY_2_OFF 0x2 313#define IMX6Q_GPR13_SATA_TX_ATTEN_8_16 (0x5 << 11)
314#define IMX6Q_GPR13_SATA_PHY_1_MASK (0x3 << 0) 314#define IMX6Q_GPR13_SATA_TX_BOOST_MASK (0xf << 7)
315#define IMX6Q_GPR13_SATA_PHY_1_FAST (0x0 << 0) 315#define IMX6Q_GPR13_SATA_TX_BOOST_0_00_DB (0x0 << 7)
316#define IMX6Q_GPR13_SATA_PHY_1_MED (0x1 << 0) 316#define IMX6Q_GPR13_SATA_TX_BOOST_0_37_DB (0x1 << 7)
317#define IMX6Q_GPR13_SATA_PHY_1_SLOW (0x2 << 0) 317#define IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB (0x2 << 7)
318 318#define IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB (0x3 << 7)
319#define IMX6Q_GPR13_SATA_TX_BOOST_1_48_DB (0x4 << 7)
320#define IMX6Q_GPR13_SATA_TX_BOOST_1_85_DB (0x5 << 7)
321#define IMX6Q_GPR13_SATA_TX_BOOST_2_22_DB (0x6 << 7)
322#define IMX6Q_GPR13_SATA_TX_BOOST_2_59_DB (0x7 << 7)
323#define IMX6Q_GPR13_SATA_TX_BOOST_2_96_DB (0x8 << 7)
324#define IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB (0x9 << 7)
325#define IMX6Q_GPR13_SATA_TX_BOOST_3_70_DB (0xa << 7)
326#define IMX6Q_GPR13_SATA_TX_BOOST_4_07_DB (0xb << 7)
327#define IMX6Q_GPR13_SATA_TX_BOOST_4_44_DB (0xc << 7)
328#define IMX6Q_GPR13_SATA_TX_BOOST_4_81_DB (0xd << 7)
329#define IMX6Q_GPR13_SATA_TX_BOOST_5_28_DB (0xe << 7)
330#define IMX6Q_GPR13_SATA_TX_BOOST_5_75_DB (0xf << 7)
331#define IMX6Q_GPR13_SATA_TX_LVL_MASK (0x1f << 2)
332#define IMX6Q_GPR13_SATA_TX_LVL_0_937_V (0x00 << 2)
333#define IMX6Q_GPR13_SATA_TX_LVL_0_947_V (0x01 << 2)
334#define IMX6Q_GPR13_SATA_TX_LVL_0_957_V (0x02 << 2)
335#define IMX6Q_GPR13_SATA_TX_LVL_0_966_V (0x03 << 2)
336#define IMX6Q_GPR13_SATA_TX_LVL_0_976_V (0x04 << 2)
337#define IMX6Q_GPR13_SATA_TX_LVL_0_986_V (0x05 << 2)
338#define IMX6Q_GPR13_SATA_TX_LVL_0_996_V (0x06 << 2)
339#define IMX6Q_GPR13_SATA_TX_LVL_1_005_V (0x07 << 2)
340#define IMX6Q_GPR13_SATA_TX_LVL_1_015_V (0x08 << 2)
341#define IMX6Q_GPR13_SATA_TX_LVL_1_025_V (0x09 << 2)
342#define IMX6Q_GPR13_SATA_TX_LVL_1_035_V (0x0a << 2)
343#define IMX6Q_GPR13_SATA_TX_LVL_1_045_V (0x0b << 2)
344#define IMX6Q_GPR13_SATA_TX_LVL_1_054_V (0x0c << 2)
345#define IMX6Q_GPR13_SATA_TX_LVL_1_064_V (0x0d << 2)
346#define IMX6Q_GPR13_SATA_TX_LVL_1_074_V (0x0e << 2)
347#define IMX6Q_GPR13_SATA_TX_LVL_1_084_V (0x0f << 2)
348#define IMX6Q_GPR13_SATA_TX_LVL_1_094_V (0x10 << 2)
349#define IMX6Q_GPR13_SATA_TX_LVL_1_104_V (0x11 << 2)
350#define IMX6Q_GPR13_SATA_TX_LVL_1_113_V (0x12 << 2)
351#define IMX6Q_GPR13_SATA_TX_LVL_1_123_V (0x13 << 2)
352#define IMX6Q_GPR13_SATA_TX_LVL_1_133_V (0x14 << 2)
353#define IMX6Q_GPR13_SATA_TX_LVL_1_143_V (0x15 << 2)
354#define IMX6Q_GPR13_SATA_TX_LVL_1_152_V (0x16 << 2)
355#define IMX6Q_GPR13_SATA_TX_LVL_1_162_V (0x17 << 2)
356#define IMX6Q_GPR13_SATA_TX_LVL_1_172_V (0x18 << 2)
357#define IMX6Q_GPR13_SATA_TX_LVL_1_182_V (0x19 << 2)
358#define IMX6Q_GPR13_SATA_TX_LVL_1_191_V (0x1a << 2)
359#define IMX6Q_GPR13_SATA_TX_LVL_1_201_V (0x1b << 2)
360#define IMX6Q_GPR13_SATA_TX_LVL_1_211_V (0x1c << 2)
361#define IMX6Q_GPR13_SATA_TX_LVL_1_221_V (0x1d << 2)
362#define IMX6Q_GPR13_SATA_TX_LVL_1_230_V (0x1e << 2)
363#define IMX6Q_GPR13_SATA_TX_LVL_1_240_V (0x1f << 2)
364#define IMX6Q_GPR13_SATA_MPLL_CLK_EN BIT(1)
365#define IMX6Q_GPR13_SATA_TX_EDGE_RATE BIT(0)
319#endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */ 366#endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */
diff --git a/include/linux/mfd/ti_am335x_tscadc.h b/include/linux/mfd/ti_am335x_tscadc.h
index c79ad5d2f271..25f2c611ab01 100644
--- a/include/linux/mfd/ti_am335x_tscadc.h
+++ b/include/linux/mfd/ti_am335x_tscadc.h
@@ -30,8 +30,8 @@
30#define REG_IDLECONFIG 0x058 30#define REG_IDLECONFIG 0x058
31#define REG_CHARGECONFIG 0x05C 31#define REG_CHARGECONFIG 0x05C
32#define REG_CHARGEDELAY 0x060 32#define REG_CHARGEDELAY 0x060
33#define REG_STEPCONFIG(n) (0x64 + ((n - 1) * 8)) 33#define REG_STEPCONFIG(n) (0x64 + ((n) * 8))
34#define REG_STEPDELAY(n) (0x68 + ((n - 1) * 8)) 34#define REG_STEPDELAY(n) (0x68 + ((n) * 8))
35#define REG_FIFO0CNT 0xE4 35#define REG_FIFO0CNT 0xE4
36#define REG_FIFO0THR 0xE8 36#define REG_FIFO0THR 0xE8
37#define REG_FIFO1CNT 0xF0 37#define REG_FIFO1CNT 0xF0
@@ -46,8 +46,6 @@
46/* Step Enable */ 46/* Step Enable */
47#define STEPENB_MASK (0x1FFFF << 0) 47#define STEPENB_MASK (0x1FFFF << 0)
48#define STEPENB(val) ((val) << 0) 48#define STEPENB(val) ((val) << 0)
49#define STPENB_STEPENB STEPENB(0x1FFFF)
50#define STPENB_STEPENB_TC STEPENB(0x1FFF)
51 49
52/* IRQ enable */ 50/* IRQ enable */
53#define IRQENB_HW_PEN BIT(0) 51#define IRQENB_HW_PEN BIT(0)
@@ -73,8 +71,6 @@
73#define STEPCONFIG_INM_ADCREFM STEPCONFIG_INM(8) 71#define STEPCONFIG_INM_ADCREFM STEPCONFIG_INM(8)
74#define STEPCONFIG_INP_MASK (0xF << 19) 72#define STEPCONFIG_INP_MASK (0xF << 19)
75#define STEPCONFIG_INP(val) ((val) << 19) 73#define STEPCONFIG_INP(val) ((val) << 19)
76#define STEPCONFIG_INP_AN2 STEPCONFIG_INP(2)
77#define STEPCONFIG_INP_AN3 STEPCONFIG_INP(3)
78#define STEPCONFIG_INP_AN4 STEPCONFIG_INP(4) 74#define STEPCONFIG_INP_AN4 STEPCONFIG_INP(4)
79#define STEPCONFIG_INP_ADCREFM STEPCONFIG_INP(8) 75#define STEPCONFIG_INP_ADCREFM STEPCONFIG_INP(8)
80#define STEPCONFIG_FIFO1 BIT(26) 76#define STEPCONFIG_FIFO1 BIT(26)
@@ -96,7 +92,6 @@
96#define STEPCHARGE_INM_AN1 STEPCHARGE_INM(1) 92#define STEPCHARGE_INM_AN1 STEPCHARGE_INM(1)
97#define STEPCHARGE_INP_MASK (0xF << 19) 93#define STEPCHARGE_INP_MASK (0xF << 19)
98#define STEPCHARGE_INP(val) ((val) << 19) 94#define STEPCHARGE_INP(val) ((val) << 19)
99#define STEPCHARGE_INP_AN1 STEPCHARGE_INP(1)
100#define STEPCHARGE_RFM_MASK (3 << 23) 95#define STEPCHARGE_RFM_MASK (3 << 23)
101#define STEPCHARGE_RFM(val) ((val) << 23) 96#define STEPCHARGE_RFM(val) ((val) << 23)
102#define STEPCHARGE_RFM_XNUR STEPCHARGE_RFM(1) 97#define STEPCHARGE_RFM_XNUR STEPCHARGE_RFM(1)
@@ -118,29 +113,39 @@
118#define CNTRLREG_8WIRE CNTRLREG_AFE_CTRL(3) 113#define CNTRLREG_8WIRE CNTRLREG_AFE_CTRL(3)
119#define CNTRLREG_TSCENB BIT(7) 114#define CNTRLREG_TSCENB BIT(7)
120 115
116/* FIFO READ Register */
117#define FIFOREAD_DATA_MASK (0xfff << 0)
118#define FIFOREAD_CHNLID_MASK (0xf << 16)
119
120/* Sequencer Status */
121#define SEQ_STATUS BIT(5)
122
121#define ADC_CLK 3000000 123#define ADC_CLK 3000000
122#define MAX_CLK_DIV 7
123#define TOTAL_STEPS 16 124#define TOTAL_STEPS 16
124#define TOTAL_CHANNELS 8 125#define TOTAL_CHANNELS 8
125 126
126#define TSCADC_CELLS 2 127/*
127 128* ADC runs at 3MHz, and it takes
128enum tscadc_cells { 129* 15 cycles to latch one data output.
129 TSC_CELL, 130* Hence the idle time for ADC to
130 ADC_CELL, 131* process one sample data would be
131}; 132* around 5 micro seconds.
133*/
134#define IDLE_TIMEOUT 5 /* microsec */
132 135
133struct mfd_tscadc_board { 136#define TSCADC_CELLS 2
134 struct tsc_data *tsc_init;
135 struct adc_data *adc_init;
136};
137 137
138struct ti_tscadc_dev { 138struct ti_tscadc_dev {
139 struct device *dev; 139 struct device *dev;
140 struct regmap *regmap_tscadc; 140 struct regmap *regmap_tscadc;
141 void __iomem *tscadc_base; 141 void __iomem *tscadc_base;
142 int irq; 142 int irq;
143 int used_cells; /* 1-2 */
144 int tsc_cell; /* -1 if not used */
145 int adc_cell; /* -1 if not used */
143 struct mfd_cell cells[TSCADC_CELLS]; 146 struct mfd_cell cells[TSCADC_CELLS];
147 u32 reg_se_cache;
148 spinlock_t reg_lock;
144 149
145 /* tsc device */ 150 /* tsc device */
146 struct titsc *tsc; 151 struct titsc *tsc;
@@ -149,4 +154,15 @@ struct ti_tscadc_dev {
149 struct adc_device *adc; 154 struct adc_device *adc;
150}; 155};
151 156
157static inline struct ti_tscadc_dev *ti_tscadc_dev_get(struct platform_device *p)
158{
159 struct ti_tscadc_dev **tscadc_dev = p->dev.platform_data;
160
161 return *tscadc_dev;
162}
163
164void am335x_tsc_se_update(struct ti_tscadc_dev *tsadc);
165void am335x_tsc_se_set(struct ti_tscadc_dev *tsadc, u32 val);
166void am335x_tsc_se_clr(struct ti_tscadc_dev *tsadc, u32 val);
167
152#endif 168#endif
diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h
index 99bf3e665997..b22883d60500 100644
--- a/include/linux/mfd/tmio.h
+++ b/include/linux/mfd/tmio.h
@@ -81,10 +81,15 @@ int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
81void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state); 81void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state);
82void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state); 82void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state);
83 83
84struct dma_chan;
85
84struct tmio_mmc_dma { 86struct tmio_mmc_dma {
85 void *chan_priv_tx; 87 void *chan_priv_tx;
86 void *chan_priv_rx; 88 void *chan_priv_rx;
89 int slave_id_tx;
90 int slave_id_rx;
87 int alignment_shift; 91 int alignment_shift;
92 bool (*filter)(struct dma_chan *chan, void *arg);
88}; 93};
89 94
90struct tmio_mmc_host; 95struct tmio_mmc_host;
@@ -103,7 +108,6 @@ struct tmio_mmc_data {
103 unsigned int cd_gpio; 108 unsigned int cd_gpio;
104 void (*set_pwr)(struct platform_device *host, int state); 109 void (*set_pwr)(struct platform_device *host, int state);
105 void (*set_clk_div)(struct platform_device *host, int state); 110 void (*set_clk_div)(struct platform_device *host, int state);
106 int (*get_cd)(struct platform_device *host);
107 int (*write16_hook)(struct tmio_mmc_host *host, int addr); 111 int (*write16_hook)(struct tmio_mmc_host *host, int addr);
108 /* clock management callbacks */ 112 /* clock management callbacks */
109 int (*clk_enable)(struct platform_device *pdev, unsigned int *f); 113 int (*clk_enable)(struct platform_device *pdev, unsigned int *f);
diff --git a/include/linux/mfd/tps65217.h b/include/linux/mfd/tps65217.h
index 29eab2bd3dfa..a5a7f0130e96 100644
--- a/include/linux/mfd/tps65217.h
+++ b/include/linux/mfd/tps65217.h
@@ -244,24 +244,6 @@ struct tps65217_board {
244}; 244};
245 245
246/** 246/**
247 * struct tps_info - packages regulator constraints
248 * @name: Voltage regulator name
249 * @min_uV: minimum micro volts
250 * @max_uV: minimum micro volts
251 * @vsel_to_uv: Function pointer to get voltage from selector
252 * @uv_to_vsel: Function pointer to get selector from voltage
253 *
254 * This data is used to check the regualtor voltage limits while setting.
255 */
256struct tps_info {
257 const char *name;
258 int min_uV;
259 int max_uV;
260 int (*vsel_to_uv)(unsigned int vsel);
261 int (*uv_to_vsel)(int uV, unsigned int *vsel);
262};
263
264/**
265 * struct tps65217 - tps65217 sub-driver chip access routines 247 * struct tps65217 - tps65217 sub-driver chip access routines
266 * 248 *
267 * Device data may be used to access the TPS65217 chip 249 * Device data may be used to access the TPS65217 chip
@@ -273,7 +255,6 @@ struct tps65217 {
273 unsigned int id; 255 unsigned int id;
274 struct regulator_desc desc[TPS65217_NUM_REGULATOR]; 256 struct regulator_desc desc[TPS65217_NUM_REGULATOR];
275 struct regulator_dev *rdev[TPS65217_NUM_REGULATOR]; 257 struct regulator_dev *rdev[TPS65217_NUM_REGULATOR];
276 struct tps_info *info[TPS65217_NUM_REGULATOR];
277 struct regmap *regmap; 258 struct regmap *regmap;
278}; 259};
279 260
diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h
index 94ac944d12f0..81f639bc1ae6 100644
--- a/include/linux/mfd/twl6040.h
+++ b/include/linux/mfd/twl6040.h
@@ -125,8 +125,15 @@
125 125
126#define TWL6040_HSDACENA (1 << 0) 126#define TWL6040_HSDACENA (1 << 0)
127#define TWL6040_HSDACMODE (1 << 1) 127#define TWL6040_HSDACMODE (1 << 1)
128#define TWL6040_HSDRVENA (1 << 2)
128#define TWL6040_HSDRVMODE (1 << 3) 129#define TWL6040_HSDRVMODE (1 << 3)
129 130
131/* HFLCTL/R (0x14/0x16) fields */
132
133#define TWL6040_HFDACENA (1 << 0)
134#define TWL6040_HFPGAENA (1 << 1)
135#define TWL6040_HFDRVENA (1 << 4)
136
130/* VIBCTLL/R (0x18/0x1A) fields */ 137/* VIBCTLL/R (0x18/0x1A) fields */
131 138
132#define TWL6040_VIBENA (1 << 0) 139#define TWL6040_VIBENA (1 << 0)
@@ -178,6 +185,7 @@
178 185
179#define TWL6040_GPO_MAX 3 186#define TWL6040_GPO_MAX 3
180 187
188/* TODO: All platform data struct can be removed */
181struct twl6040_codec_data { 189struct twl6040_codec_data {
182 u16 hs_left_step; 190 u16 hs_left_step;
183 u16 hs_right_step; 191 u16 hs_right_step;
@@ -222,7 +230,6 @@ struct twl6040 {
222 int audpwron; 230 int audpwron;
223 int power_count; 231 int power_count;
224 int rev; 232 int rev;
225 u8 vibra_ctrl_cache[2];
226 233
227 /* PLL configuration */ 234 /* PLL configuration */
228 int pll; 235 int pll;
diff --git a/include/linux/mfd/ucb1x00.h b/include/linux/mfd/ucb1x00.h
index 28af41756360..88f90cbf8e6a 100644
--- a/include/linux/mfd/ucb1x00.h
+++ b/include/linux/mfd/ucb1x00.h
@@ -10,6 +10,7 @@
10#ifndef UCB1200_H 10#ifndef UCB1200_H
11#define UCB1200_H 11#define UCB1200_H
12 12
13#include <linux/device.h>
13#include <linux/mfd/mcp.h> 14#include <linux/mfd/mcp.h>
14#include <linux/gpio.h> 15#include <linux/gpio.h>
15#include <linux/mutex.h> 16#include <linux/mutex.h>
diff --git a/include/linux/mfd/wm8994/core.h b/include/linux/mfd/wm8994/core.h
index ae5c249530b4..40854ac0ba3d 100644
--- a/include/linux/mfd/wm8994/core.h
+++ b/include/linux/mfd/wm8994/core.h
@@ -29,6 +29,7 @@ enum wm8994_type {
29 29
30struct regulator_dev; 30struct regulator_dev;
31struct regulator_bulk_data; 31struct regulator_bulk_data;
32struct irq_domain;
32 33
33#define WM8994_NUM_GPIO_REGS 11 34#define WM8994_NUM_GPIO_REGS 11
34#define WM8994_NUM_LDO_REGS 2 35#define WM8994_NUM_LDO_REGS 2
@@ -73,6 +74,7 @@ struct wm8994 {
73 74
74 int irq; 75 int irq;
75 struct regmap_irq_chip_data *irq_data; 76 struct regmap_irq_chip_data *irq_data;
77 struct irq_domain *edge_irq;
76 78
77 /* Used over suspend/resume */ 79 /* Used over suspend/resume */
78 bool suspended; 80 bool suspended;
diff --git a/include/linux/mfd/wm8994/pdata.h b/include/linux/mfd/wm8994/pdata.h
index 68e776594889..90c60524a496 100644
--- a/include/linux/mfd/wm8994/pdata.h
+++ b/include/linux/mfd/wm8994/pdata.h
@@ -182,6 +182,11 @@ struct wm8994_pdata {
182 */ 182 */
183 int micdet_delay; 183 int micdet_delay;
184 184
185 /* Delay between microphone detect completing and reporting on
186 * insert (specified in ms)
187 */
188 int mic_id_delay;
189
185 /* IRQ for microphone detection if brought out directly as a 190 /* IRQ for microphone detection if brought out directly as a
186 * signal. 191 * signal.
187 */ 192 */
@@ -223,6 +228,11 @@ struct wm8994_pdata {
223 * lines is mastered. 228 * lines is mastered.
224 */ 229 */
225 int max_channels_clocked[WM8994_NUM_AIF]; 230 int max_channels_clocked[WM8994_NUM_AIF];
231
232 /**
233 * GPIO for the IRQ pin if host only supports edge triggering
234 */
235 int irq_gpio;
226}; 236};
227 237
228#endif 238#endif
diff --git a/include/linux/mfd/wm8994/registers.h b/include/linux/mfd/wm8994/registers.h
index 053548961c15..db8cef3d5321 100644
--- a/include/linux/mfd/wm8994/registers.h
+++ b/include/linux/mfd/wm8994/registers.h
@@ -2668,6 +2668,10 @@
2668/* 2668/*
2669 * R772 (0x304) - AIF1ADC LRCLK 2669 * R772 (0x304) - AIF1ADC LRCLK
2670 */ 2670 */
2671#define WM8958_AIF1_LRCLK_INV 0x1000 /* AIF1_LRCLK_INV */
2672#define WM8958_AIF1_LRCLK_INV_MASK 0x1000 /* AIF1_LRCLK_INV */
2673#define WM8958_AIF1_LRCLK_INV_SHIFT 12 /* AIF1_LRCLK_INV */
2674#define WM8958_AIF1_LRCLK_INV_WIDTH 1 /* AIF1_LRCLK_INV */
2671#define WM8994_AIF1ADC_LRCLK_DIR 0x0800 /* AIF1ADC_LRCLK_DIR */ 2675#define WM8994_AIF1ADC_LRCLK_DIR 0x0800 /* AIF1ADC_LRCLK_DIR */
2672#define WM8994_AIF1ADC_LRCLK_DIR_MASK 0x0800 /* AIF1ADC_LRCLK_DIR */ 2676#define WM8994_AIF1ADC_LRCLK_DIR_MASK 0x0800 /* AIF1ADC_LRCLK_DIR */
2673#define WM8994_AIF1ADC_LRCLK_DIR_SHIFT 11 /* AIF1ADC_LRCLK_DIR */ 2677#define WM8994_AIF1ADC_LRCLK_DIR_SHIFT 11 /* AIF1ADC_LRCLK_DIR */
@@ -2679,6 +2683,10 @@
2679/* 2683/*
2680 * R773 (0x305) - AIF1DAC LRCLK 2684 * R773 (0x305) - AIF1DAC LRCLK
2681 */ 2685 */
2686#define WM8958_AIF1_LRCLK_INV 0x1000 /* AIF1_LRCLK_INV */
2687#define WM8958_AIF1_LRCLK_INV_MASK 0x1000 /* AIF1_LRCLK_INV */
2688#define WM8958_AIF1_LRCLK_INV_SHIFT 12 /* AIF1_LRCLK_INV */
2689#define WM8958_AIF1_LRCLK_INV_WIDTH 1 /* AIF1_LRCLK_INV */
2682#define WM8994_AIF1DAC_LRCLK_DIR 0x0800 /* AIF1DAC_LRCLK_DIR */ 2690#define WM8994_AIF1DAC_LRCLK_DIR 0x0800 /* AIF1DAC_LRCLK_DIR */
2683#define WM8994_AIF1DAC_LRCLK_DIR_MASK 0x0800 /* AIF1DAC_LRCLK_DIR */ 2691#define WM8994_AIF1DAC_LRCLK_DIR_MASK 0x0800 /* AIF1DAC_LRCLK_DIR */
2684#define WM8994_AIF1DAC_LRCLK_DIR_SHIFT 11 /* AIF1DAC_LRCLK_DIR */ 2692#define WM8994_AIF1DAC_LRCLK_DIR_SHIFT 11 /* AIF1DAC_LRCLK_DIR */
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-06 06:36:25 -0400