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authorLinus Torvalds <torvalds@linux-foundation.org>2012-12-16 21:55:20 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2012-12-16 21:55:20 -0500
commit2dfea3803dcf70983d14ce1dcbb3e97a7459a28b (patch)
tree59bffc7389ff554585f79d7cc06021790dc2b317 /include/linux/mfd
parentaed606e3bc1f10753254db308d3fd8c053c41328 (diff)
parent1881b68b8961a86d40c3c5c205e533515a2dc9c6 (diff)
Merge tag 'mfd-3.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6
Pull MFS update from Samuel Ortiz: "This is the MFD patch set for the 3.8 merge window. We have several new drivers, most of the time coming with their sub devices drivers: - Austria Microsystem's AS3711 - Nano River's viperboard - TI's TPS80031, AM335x TS/ADC, - Realtek's MMC/memstick card reader - Nokia's retu We also got some notable cleanups and improvements: - tps6586x got converted to IRQ domains. - tps65910 and tps65090 moved to the regmap IRQ API. - STMPE is now Device Tree aware. - A general twl6040 and twl-core cleanup, with moves to the regmap I/O and IRQ APIs and a conversion to the recently added PWM framework. - sta2x11 gained regmap support. Then the rest is mostly tiny cleanups and fixes, among which we have Mark's wm5xxx and wm8xxx patchset." Far amount of annoying but largely trivial conflicts. Many due to __devinit/exit removal, others due to one or two of the new drivers also having come in through another tree. * tag 'mfd-3.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6: (119 commits) mfd: tps6507x: Convert to devm_kzalloc mfd: stmpe: Update DT support for stmpe driver mfd: wm5102: Add readback of DSP status 3 register mfd: arizona: Log if we fail to create the primary IRQ domain mfd: tps80031: MFD_TPS80031 needs to select REGMAP_IRQ mfd: tps80031: Add terminating entry for tps80031_id_table mfd: sta2x11: Fix potential NULL pointer dereference in __sta2x11_mfd_mask() mfd: wm5102: Add tuning for revision B mfd: arizona: Defer patch initialistation until after first device boot mfd: tps65910: Fix wrong ack_base register mfd: tps65910: Remove unused data mfd: stmpe: Get rid of irq_invert_polarity mfd: ab8500-core: Fix invalid free of devm_ allocated data mfd: wm5102: Mark DSP memory regions as volatile mfd: wm5102: Correct default for LDO1_CONTROL_2 mfd: arizona: Register haptics devices mfd: wm8994: Make current device behaviour the default mfd: tps65090: MFD_TPS65090 needs to select REGMAP_IRQ mfd: Fix stmpe.c build when OF is not enabled mfd: jz4740-adc: Use devm_kzalloc ...
Diffstat (limited to 'include/linux/mfd')
-rw-r--r--include/linux/mfd/arizona/registers.h1
-rw-r--r--include/linux/mfd/as3711.h126
-rw-r--r--include/linux/mfd/da9052/da9052.h10
-rw-r--r--include/linux/mfd/da9055/core.h2
-rw-r--r--include/linux/mfd/da9055/pdata.h2
-rw-r--r--include/linux/mfd/da9055/reg.h2
-rw-r--r--include/linux/mfd/rc5t583.h3
-rw-r--r--include/linux/mfd/retu.h22
-rw-r--r--include/linux/mfd/sta2x11-mfd.h198
-rw-r--r--include/linux/mfd/stmpe.h4
-rw-r--r--include/linux/mfd/ti_am335x_tscadc.h152
-rw-r--r--include/linux/mfd/tps65090.h73
-rw-r--r--include/linux/mfd/tps6586x.h1
-rw-r--r--include/linux/mfd/tps65910.h145
-rw-r--r--include/linux/mfd/tps80031.h637
-rw-r--r--include/linux/mfd/twl6040.h10
-rw-r--r--include/linux/mfd/viperboard.h110
17 files changed, 1421 insertions, 77 deletions
diff --git a/include/linux/mfd/arizona/registers.h b/include/linux/mfd/arizona/registers.h
index ba26e99c388d..1f6fe31a4d5c 100644
--- a/include/linux/mfd/arizona/registers.h
+++ b/include/linux/mfd/arizona/registers.h
@@ -981,6 +981,7 @@
981#define ARIZONA_DSP1_CLOCKING_1 0x1101 981#define ARIZONA_DSP1_CLOCKING_1 0x1101
982#define ARIZONA_DSP1_STATUS_1 0x1104 982#define ARIZONA_DSP1_STATUS_1 0x1104
983#define ARIZONA_DSP1_STATUS_2 0x1105 983#define ARIZONA_DSP1_STATUS_2 0x1105
984#define ARIZONA_DSP1_STATUS_3 0x1106
984#define ARIZONA_DSP2_CONTROL_1 0x1200 985#define ARIZONA_DSP2_CONTROL_1 0x1200
985#define ARIZONA_DSP2_CLOCKING_1 0x1201 986#define ARIZONA_DSP2_CLOCKING_1 0x1201
986#define ARIZONA_DSP2_STATUS_1 0x1204 987#define ARIZONA_DSP2_STATUS_1 0x1204
diff --git a/include/linux/mfd/as3711.h b/include/linux/mfd/as3711.h
new file mode 100644
index 000000000000..38452ce1e892
--- /dev/null
+++ b/include/linux/mfd/as3711.h
@@ -0,0 +1,126 @@
1/*
2 * AS3711 PMIC MFC driver header
3 *
4 * Copyright (C) 2012 Renesas Electronics Corporation
5 * Author: Guennadi Liakhovetski, <g.liakhovetski@gmx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the version 2 of the GNU General Public License as
9 * published by the Free Software Foundation
10 */
11
12#ifndef MFD_AS3711_H
13#define MFD_AS3711_H
14
15/*
16 * Client data
17 */
18
19/* Register addresses */
20#define AS3711_SD_1_VOLTAGE 0 /* Digital Step-Down */
21#define AS3711_SD_2_VOLTAGE 1
22#define AS3711_SD_3_VOLTAGE 2
23#define AS3711_SD_4_VOLTAGE 3
24#define AS3711_LDO_1_VOLTAGE 4 /* Analog LDO */
25#define AS3711_LDO_2_VOLTAGE 5
26#define AS3711_LDO_3_VOLTAGE 6 /* Digital LDO */
27#define AS3711_LDO_4_VOLTAGE 7
28#define AS3711_LDO_5_VOLTAGE 8
29#define AS3711_LDO_6_VOLTAGE 9
30#define AS3711_LDO_7_VOLTAGE 0xa
31#define AS3711_LDO_8_VOLTAGE 0xb
32#define AS3711_SD_CONTROL 0x10
33#define AS3711_GPIO_SIGNAL_OUT 0x20
34#define AS3711_GPIO_SIGNAL_IN 0x21
35#define AS3711_SD_CONTROL_1 0x30
36#define AS3711_SD_CONTROL_2 0x31
37#define AS3711_CURR_CONTROL 0x40
38#define AS3711_CURR1_VALUE 0x43
39#define AS3711_CURR2_VALUE 0x44
40#define AS3711_CURR3_VALUE 0x45
41#define AS3711_STEPUP_CONTROL_1 0x50
42#define AS3711_STEPUP_CONTROL_2 0x51
43#define AS3711_STEPUP_CONTROL_4 0x53
44#define AS3711_STEPUP_CONTROL_5 0x54
45#define AS3711_REG_STATUS 0x73
46#define AS3711_INTERRUPT_STATUS_1 0x77
47#define AS3711_INTERRUPT_STATUS_2 0x78
48#define AS3711_INTERRUPT_STATUS_3 0x79
49#define AS3711_CHARGER_STATUS_1 0x86
50#define AS3711_CHARGER_STATUS_2 0x87
51#define AS3711_ASIC_ID_1 0x90
52#define AS3711_ASIC_ID_2 0x91
53
54#define AS3711_MAX_REGS 0x92
55
56/* Regulators */
57enum {
58 AS3711_REGULATOR_SD_1,
59 AS3711_REGULATOR_SD_2,
60 AS3711_REGULATOR_SD_3,
61 AS3711_REGULATOR_SD_4,
62 AS3711_REGULATOR_LDO_1,
63 AS3711_REGULATOR_LDO_2,
64 AS3711_REGULATOR_LDO_3,
65 AS3711_REGULATOR_LDO_4,
66 AS3711_REGULATOR_LDO_5,
67 AS3711_REGULATOR_LDO_6,
68 AS3711_REGULATOR_LDO_7,
69 AS3711_REGULATOR_LDO_8,
70
71 AS3711_REGULATOR_MAX,
72};
73
74struct device;
75struct regmap;
76
77struct as3711 {
78 struct device *dev;
79 struct regmap *regmap;
80};
81
82#define AS3711_MAX_STEPDOWN 4
83#define AS3711_MAX_STEPUP 2
84#define AS3711_MAX_LDO 8
85
86enum as3711_su2_feedback {
87 AS3711_SU2_VOLTAGE,
88 AS3711_SU2_CURR1,
89 AS3711_SU2_CURR2,
90 AS3711_SU2_CURR3,
91 AS3711_SU2_CURR_AUTO,
92};
93
94enum as3711_su2_fbprot {
95 AS3711_SU2_LX_SD4,
96 AS3711_SU2_GPIO2,
97 AS3711_SU2_GPIO3,
98 AS3711_SU2_GPIO4,
99};
100
101/*
102 * Platform data
103 */
104
105struct as3711_regulator_pdata {
106 struct regulator_init_data *init_data[AS3711_REGULATOR_MAX];
107};
108
109struct as3711_bl_pdata {
110 const char *su1_fb;
111 int su1_max_uA;
112 const char *su2_fb;
113 int su2_max_uA;
114 enum as3711_su2_feedback su2_feedback;
115 enum as3711_su2_fbprot su2_fbprot;
116 bool su2_auto_curr1;
117 bool su2_auto_curr2;
118 bool su2_auto_curr3;
119};
120
121struct as3711_platform_data {
122 struct as3711_regulator_pdata regulator;
123 struct as3711_bl_pdata backlight;
124};
125
126#endif
diff --git a/include/linux/mfd/da9052/da9052.h b/include/linux/mfd/da9052/da9052.h
index 0507c4c21a7d..86dd93de6ff2 100644
--- a/include/linux/mfd/da9052/da9052.h
+++ b/include/linux/mfd/da9052/da9052.h
@@ -146,4 +146,14 @@ void da9052_device_exit(struct da9052 *da9052);
146 146
147extern struct regmap_config da9052_regmap_config; 147extern struct regmap_config da9052_regmap_config;
148 148
149int da9052_irq_init(struct da9052 *da9052);
150int da9052_irq_exit(struct da9052 *da9052);
151int da9052_request_irq(struct da9052 *da9052, int irq, char *name,
152 irq_handler_t handler, void *data);
153void da9052_free_irq(struct da9052 *da9052, int irq, void *data);
154
155int da9052_enable_irq(struct da9052 *da9052, int irq);
156int da9052_disable_irq(struct da9052 *da9052, int irq);
157int da9052_disable_irq_nosync(struct da9052 *da9052, int irq);
158
149#endif /* __MFD_DA9052_DA9052_H */ 159#endif /* __MFD_DA9052_DA9052_H */
diff --git a/include/linux/mfd/da9055/core.h b/include/linux/mfd/da9055/core.h
index c96ad682c59e..956afa445998 100644
--- a/include/linux/mfd/da9055/core.h
+++ b/include/linux/mfd/da9055/core.h
@@ -1,4 +1,4 @@
1/* 1/*
2 * da9055 declarations for DA9055 PMICs. 2 * da9055 declarations for DA9055 PMICs.
3 * 3 *
4 * Copyright(c) 2012 Dialog Semiconductor Ltd. 4 * Copyright(c) 2012 Dialog Semiconductor Ltd.
diff --git a/include/linux/mfd/da9055/pdata.h b/include/linux/mfd/da9055/pdata.h
index f87a6c172a91..04e092be4b07 100644
--- a/include/linux/mfd/da9055/pdata.h
+++ b/include/linux/mfd/da9055/pdata.h
@@ -1,4 +1,4 @@
1/* Copyright (C) 2012 Dialog Semiconductor Ltd. 1/* Copyright (C) 2012 Dialog Semiconductor Ltd.
2 * 2 *
3 * This program is free software; you can redistribute it and/or modify 3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by 4 * it under the terms of the GNU General Public License as published by
diff --git a/include/linux/mfd/da9055/reg.h b/include/linux/mfd/da9055/reg.h
index df237ee54803..2b592e072dbf 100644
--- a/include/linux/mfd/da9055/reg.h
+++ b/include/linux/mfd/da9055/reg.h
@@ -1,4 +1,4 @@
1/* 1/*
2 * DA9055 declarations for DA9055 PMICs. 2 * DA9055 declarations for DA9055 PMICs.
3 * 3 *
4 * Copyright(c) 2012 Dialog Semiconductor Ltd. 4 * Copyright(c) 2012 Dialog Semiconductor Ltd.
diff --git a/include/linux/mfd/rc5t583.h b/include/linux/mfd/rc5t583.h
index 36c242e52ef1..fd413ccab915 100644
--- a/include/linux/mfd/rc5t583.h
+++ b/include/linux/mfd/rc5t583.h
@@ -33,6 +33,7 @@
33/* Maximum number of main interrupts */ 33/* Maximum number of main interrupts */
34#define MAX_MAIN_INTERRUPT 5 34#define MAX_MAIN_INTERRUPT 5
35#define RC5T583_MAX_GPEDGE_REG 2 35#define RC5T583_MAX_GPEDGE_REG 2
36#define RC5T583_MAX_INTERRUPT_EN_REGS 8
36#define RC5T583_MAX_INTERRUPT_MASK_REGS 9 37#define RC5T583_MAX_INTERRUPT_MASK_REGS 9
37 38
38/* Interrupt enable register */ 39/* Interrupt enable register */
@@ -304,7 +305,7 @@ struct rc5t583 {
304 uint8_t intc_inten_reg; 305 uint8_t intc_inten_reg;
305 306
306 /* For group interrupt bits and address */ 307 /* For group interrupt bits and address */
307 uint8_t irq_en_reg[RC5T583_MAX_INTERRUPT_MASK_REGS]; 308 uint8_t irq_en_reg[RC5T583_MAX_INTERRUPT_EN_REGS];
308 309
309 /* For gpio edge */ 310 /* For gpio edge */
310 uint8_t gpedge_reg[RC5T583_MAX_GPEDGE_REG]; 311 uint8_t gpedge_reg[RC5T583_MAX_GPEDGE_REG];
diff --git a/include/linux/mfd/retu.h b/include/linux/mfd/retu.h
new file mode 100644
index 000000000000..1e2715d5b836
--- /dev/null
+++ b/include/linux/mfd/retu.h
@@ -0,0 +1,22 @@
1/*
2 * Retu MFD driver interface
3 *
4 * This file is subject to the terms and conditions of the GNU General
5 * Public License. See the file "COPYING" in the main directory of this
6 * archive for more details.
7 */
8
9#ifndef __LINUX_MFD_RETU_H
10#define __LINUX_MFD_RETU_H
11
12struct retu_dev;
13
14int retu_read(struct retu_dev *, u8);
15int retu_write(struct retu_dev *, u8, u16);
16
17/* Registers */
18#define RETU_REG_WATCHDOG 0x17 /* Watchdog */
19#define RETU_REG_CC1 0x0d /* Common control register 1 */
20#define RETU_REG_STATUS 0x16 /* Status register */
21
22#endif /* __LINUX_MFD_RETU_H */
diff --git a/include/linux/mfd/sta2x11-mfd.h b/include/linux/mfd/sta2x11-mfd.h
index d179227e866f..9a855ac11cbf 100644
--- a/include/linux/mfd/sta2x11-mfd.h
+++ b/include/linux/mfd/sta2x11-mfd.h
@@ -26,6 +26,28 @@
26#include <linux/types.h> 26#include <linux/types.h>
27#include <linux/pci.h> 27#include <linux/pci.h>
28 28
29enum sta2x11_mfd_plat_dev {
30 sta2x11_sctl = 0,
31 sta2x11_gpio,
32 sta2x11_scr,
33 sta2x11_time,
34 sta2x11_apbreg,
35 sta2x11_apb_soc_regs,
36 sta2x11_vic,
37 sta2x11_n_mfd_plat_devs,
38};
39
40#define STA2X11_MFD_SCTL_NAME "sta2x11-sctl"
41#define STA2X11_MFD_GPIO_NAME "sta2x11-gpio"
42#define STA2X11_MFD_SCR_NAME "sta2x11-scr"
43#define STA2X11_MFD_TIME_NAME "sta2x11-time"
44#define STA2X11_MFD_APBREG_NAME "sta2x11-apbreg"
45#define STA2X11_MFD_APB_SOC_REGS_NAME "sta2x11-apb-soc-regs"
46#define STA2X11_MFD_VIC_NAME "sta2x11-vic"
47
48extern u32
49__sta2x11_mfd_mask(struct pci_dev *, u32, u32, u32, enum sta2x11_mfd_plat_dev);
50
29/* 51/*
30 * The MFD PCI block includes the GPIO peripherals and other register blocks. 52 * The MFD PCI block includes the GPIO peripherals and other register blocks.
31 * For GPIO, we have 32*4 bits (I use "gsta" for "gpio sta2x11".) 53 * For GPIO, we have 32*4 bits (I use "gsta" for "gpio sta2x11".)
@@ -182,7 +204,11 @@ struct sta2x11_gpio_pdata {
182 * The APB bridge has its own registers, needed by our users as well. 204 * The APB bridge has its own registers, needed by our users as well.
183 * They are accessed with the following read/mask/write function. 205 * They are accessed with the following read/mask/write function.
184 */ 206 */
185u32 sta2x11_apbreg_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val); 207static inline u32
208sta2x11_apbreg_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val)
209{
210 return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_apbreg);
211}
186 212
187/* CAN and MLB */ 213/* CAN and MLB */
188#define APBREG_BSR 0x00 /* Bridge Status Reg */ 214#define APBREG_BSR 0x00 /* Bridge Status Reg */
@@ -211,19 +237,45 @@ u32 sta2x11_apbreg_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val);
211 * The system controller has its own registers. Some of these are accessed 237 * The system controller has its own registers. Some of these are accessed
212 * by out users as well, using the following read/mask/write/function 238 * by out users as well, using the following read/mask/write/function
213 */ 239 */
214u32 sta2x11_sctl_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val); 240static inline
241u32 sta2x11_sctl_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val)
242{
243 return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_sctl);
244}
215 245
216#define SCTL_SCCTL 0x00 /* System controller control register */ 246#define SCTL_SCCTL 0x00 /* System controller control register */
217#define SCTL_ARMCFG 0x04 /* ARM configuration register */ 247#define SCTL_ARMCFG 0x04 /* ARM configuration register */
218#define SCTL_SCPLLCTL 0x08 /* PLL control status register */ 248#define SCTL_SCPLLCTL 0x08 /* PLL control status register */
249
250#define SCTL_SCPLLCTL_AUDIO_PLL_PD BIT(1)
251#define SCTL_SCPLLCTL_FRAC_CONTROL BIT(3)
252#define SCTL_SCPLLCTL_STRB_BYPASS BIT(6)
253#define SCTL_SCPLLCTL_STRB_INPUT BIT(8)
254
219#define SCTL_SCPLLFCTRL 0x0c /* PLL frequency control register */ 255#define SCTL_SCPLLFCTRL 0x0c /* PLL frequency control register */
256
257#define SCTL_SCPLLFCTRL_AUDIO_PLL_NDIV_MASK 0xff
258#define SCTL_SCPLLFCTRL_AUDIO_PLL_NDIV_SHIFT 10
259#define SCTL_SCPLLFCTRL_AUDIO_PLL_IDF_MASK 7
260#define SCTL_SCPLLFCTRL_AUDIO_PLL_IDF_SHIFT 21
261#define SCTL_SCPLLFCTRL_AUDIO_PLL_ODF_MASK 7
262#define SCTL_SCPLLFCTRL_AUDIO_PLL_ODF_SHIFT 18
263#define SCTL_SCPLLFCTRL_DITHER_DISABLE_MASK 0x03
264#define SCTL_SCPLLFCTRL_DITHER_DISABLE_SHIFT 4
265
266
220#define SCTL_SCRESFRACT 0x10 /* PLL fractional input register */ 267#define SCTL_SCRESFRACT 0x10 /* PLL fractional input register */
268
269#define SCTL_SCRESFRACT_MASK 0x0000ffff
270
271
221#define SCTL_SCRESCTRL1 0x14 /* Peripheral reset control 1 */ 272#define SCTL_SCRESCTRL1 0x14 /* Peripheral reset control 1 */
222#define SCTL_SCRESXTRL2 0x18 /* Peripheral reset control 2 */ 273#define SCTL_SCRESXTRL2 0x18 /* Peripheral reset control 2 */
223#define SCTL_SCPEREN0 0x1c /* Peripheral clock enable register 0 */ 274#define SCTL_SCPEREN0 0x1c /* Peripheral clock enable register 0 */
224#define SCTL_SCPEREN1 0x20 /* Peripheral clock enable register 1 */ 275#define SCTL_SCPEREN1 0x20 /* Peripheral clock enable register 1 */
225#define SCTL_SCPEREN2 0x24 /* Peripheral clock enable register 2 */ 276#define SCTL_SCPEREN2 0x24 /* Peripheral clock enable register 2 */
226#define SCTL_SCGRST 0x28 /* Peripheral global reset */ 277#define SCTL_SCGRST 0x28 /* Peripheral global reset */
278#define SCTL_SCPCIECSBRST 0x2c /* PCIe PAB CSB reset status register */
227#define SCTL_SCPCIPMCR1 0x30 /* PCI power management control 1 */ 279#define SCTL_SCPCIPMCR1 0x30 /* PCI power management control 1 */
228#define SCTL_SCPCIPMCR2 0x34 /* PCI power management control 2 */ 280#define SCTL_SCPCIPMCR2 0x34 /* PCI power management control 2 */
229#define SCTL_SCPCIPMSR1 0x38 /* PCI power management status 1 */ 281#define SCTL_SCPCIPMSR1 0x38 /* PCI power management status 1 */
@@ -321,4 +373,146 @@ u32 sta2x11_sctl_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val);
321#define SCTL_SCPEREN1_I2C3 (1 << 16) 373#define SCTL_SCPEREN1_I2C3 (1 << 16)
322#define SCTL_SCPEREN1_USB_PHY (1 << 17) 374#define SCTL_SCPEREN1_USB_PHY (1 << 17)
323 375
376/*
377 * APB-SOC registers
378 */
379static inline
380u32 sta2x11_apb_soc_regs_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val)
381{
382 return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_apb_soc_regs);
383}
384
385#define PCIE_EP1_FUNC3_0_INTR_REG 0x000
386#define PCIE_EP1_FUNC7_4_INTR_REG 0x004
387#define PCIE_EP2_FUNC3_0_INTR_REG 0x008
388#define PCIE_EP2_FUNC7_4_INTR_REG 0x00c
389#define PCIE_EP3_FUNC3_0_INTR_REG 0x010
390#define PCIE_EP3_FUNC7_4_INTR_REG 0x014
391#define PCIE_EP4_FUNC3_0_INTR_REG 0x018
392#define PCIE_EP4_FUNC7_4_INTR_REG 0x01c
393#define PCIE_INTR_ENABLE0_REG 0x020
394#define PCIE_INTR_ENABLE1_REG 0x024
395#define PCIE_EP1_FUNC_TC_REG 0x028
396#define PCIE_EP2_FUNC_TC_REG 0x02c
397#define PCIE_EP3_FUNC_TC_REG 0x030
398#define PCIE_EP4_FUNC_TC_REG 0x034
399#define PCIE_EP1_FUNC_F_REG 0x038
400#define PCIE_EP2_FUNC_F_REG 0x03c
401#define PCIE_EP3_FUNC_F_REG 0x040
402#define PCIE_EP4_FUNC_F_REG 0x044
403#define PCIE_PAB_AMBA_SW_RST_REG 0x048
404#define PCIE_PM_STATUS_0_PORT_0_4 0x04c
405#define PCIE_PM_STATUS_7_0_EP1 0x050
406#define PCIE_PM_STATUS_7_0_EP2 0x054
407#define PCIE_PM_STATUS_7_0_EP3 0x058
408#define PCIE_PM_STATUS_7_0_EP4 0x05c
409#define PCIE_DEV_ID_0_EP1_REG 0x060
410#define PCIE_CC_REV_ID_0_EP1_REG 0x064
411#define PCIE_DEV_ID_1_EP1_REG 0x068
412#define PCIE_CC_REV_ID_1_EP1_REG 0x06c
413#define PCIE_DEV_ID_2_EP1_REG 0x070
414#define PCIE_CC_REV_ID_2_EP1_REG 0x074
415#define PCIE_DEV_ID_3_EP1_REG 0x078
416#define PCIE_CC_REV_ID_3_EP1_REG 0x07c
417#define PCIE_DEV_ID_4_EP1_REG 0x080
418#define PCIE_CC_REV_ID_4_EP1_REG 0x084
419#define PCIE_DEV_ID_5_EP1_REG 0x088
420#define PCIE_CC_REV_ID_5_EP1_REG 0x08c
421#define PCIE_DEV_ID_6_EP1_REG 0x090
422#define PCIE_CC_REV_ID_6_EP1_REG 0x094
423#define PCIE_DEV_ID_7_EP1_REG 0x098
424#define PCIE_CC_REV_ID_7_EP1_REG 0x09c
425#define PCIE_DEV_ID_0_EP2_REG 0x0a0
426#define PCIE_CC_REV_ID_0_EP2_REG 0x0a4
427#define PCIE_DEV_ID_1_EP2_REG 0x0a8
428#define PCIE_CC_REV_ID_1_EP2_REG 0x0ac
429#define PCIE_DEV_ID_2_EP2_REG 0x0b0
430#define PCIE_CC_REV_ID_2_EP2_REG 0x0b4
431#define PCIE_DEV_ID_3_EP2_REG 0x0b8
432#define PCIE_CC_REV_ID_3_EP2_REG 0x0bc
433#define PCIE_DEV_ID_4_EP2_REG 0x0c0
434#define PCIE_CC_REV_ID_4_EP2_REG 0x0c4
435#define PCIE_DEV_ID_5_EP2_REG 0x0c8
436#define PCIE_CC_REV_ID_5_EP2_REG 0x0cc
437#define PCIE_DEV_ID_6_EP2_REG 0x0d0
438#define PCIE_CC_REV_ID_6_EP2_REG 0x0d4
439#define PCIE_DEV_ID_7_EP2_REG 0x0d8
440#define PCIE_CC_REV_ID_7_EP2_REG 0x0dC
441#define PCIE_DEV_ID_0_EP3_REG 0x0e0
442#define PCIE_CC_REV_ID_0_EP3_REG 0x0e4
443#define PCIE_DEV_ID_1_EP3_REG 0x0e8
444#define PCIE_CC_REV_ID_1_EP3_REG 0x0ec
445#define PCIE_DEV_ID_2_EP3_REG 0x0f0
446#define PCIE_CC_REV_ID_2_EP3_REG 0x0f4
447#define PCIE_DEV_ID_3_EP3_REG 0x0f8
448#define PCIE_CC_REV_ID_3_EP3_REG 0x0fc
449#define PCIE_DEV_ID_4_EP3_REG 0x100
450#define PCIE_CC_REV_ID_4_EP3_REG 0x104
451#define PCIE_DEV_ID_5_EP3_REG 0x108
452#define PCIE_CC_REV_ID_5_EP3_REG 0x10c
453#define PCIE_DEV_ID_6_EP3_REG 0x110
454#define PCIE_CC_REV_ID_6_EP3_REG 0x114
455#define PCIE_DEV_ID_7_EP3_REG 0x118
456#define PCIE_CC_REV_ID_7_EP3_REG 0x11c
457#define PCIE_DEV_ID_0_EP4_REG 0x120
458#define PCIE_CC_REV_ID_0_EP4_REG 0x124
459#define PCIE_DEV_ID_1_EP4_REG 0x128
460#define PCIE_CC_REV_ID_1_EP4_REG 0x12c
461#define PCIE_DEV_ID_2_EP4_REG 0x130
462#define PCIE_CC_REV_ID_2_EP4_REG 0x134
463#define PCIE_DEV_ID_3_EP4_REG 0x138
464#define PCIE_CC_REV_ID_3_EP4_REG 0x13c
465#define PCIE_DEV_ID_4_EP4_REG 0x140
466#define PCIE_CC_REV_ID_4_EP4_REG 0x144
467#define PCIE_DEV_ID_5_EP4_REG 0x148
468#define PCIE_CC_REV_ID_5_EP4_REG 0x14c
469#define PCIE_DEV_ID_6_EP4_REG 0x150
470#define PCIE_CC_REV_ID_6_EP4_REG 0x154
471#define PCIE_DEV_ID_7_EP4_REG 0x158
472#define PCIE_CC_REV_ID_7_EP4_REG 0x15c
473#define PCIE_SUBSYS_VEN_ID_REG 0x160
474#define PCIE_COMMON_CLOCK_CONFIG_0_4_0 0x164
475#define PCIE_MIPHYP_SSC_EN_REG 0x168
476#define PCIE_MIPHYP_ADDR_REG 0x16c
477#define PCIE_L1_ASPM_READY_REG 0x170
478#define PCIE_EXT_CFG_RDY_REG 0x174
479#define PCIE_SoC_INT_ROUTER_STATUS0_REG 0x178
480#define PCIE_SoC_INT_ROUTER_STATUS1_REG 0x17c
481#define PCIE_SoC_INT_ROUTER_STATUS2_REG 0x180
482#define PCIE_SoC_INT_ROUTER_STATUS3_REG 0x184
483#define DMA_IP_CTRL_REG 0x324
484#define DISP_BRIDGE_PU_PD_CTRL_REG 0x328
485#define VIP_PU_PD_CTRL_REG 0x32c
486#define USB_MLB_PU_PD_CTRL_REG 0x330
487#define SDIO_PU_PD_MISCFUNC_CTRL_REG1 0x334
488#define SDIO_PU_PD_MISCFUNC_CTRL_REG2 0x338
489#define UART_PU_PD_CTRL_REG 0x33c
490#define ARM_Lock 0x340
491#define SYS_IO_CHAR_REG1 0x344
492#define SYS_IO_CHAR_REG2 0x348
493#define SATA_CORE_ID_REG 0x34c
494#define SATA_CTRL_REG 0x350
495#define I2C_HSFIX_MISC_REG 0x354
496#define SPARE2_RESERVED 0x358
497#define SPARE3_RESERVED 0x35c
498#define MASTER_LOCK_REG 0x368
499#define SYSTEM_CONFIG_STATUS_REG 0x36c
500#define MSP_CLK_CTRL_REG 0x39c
501#define COMPENSATION_REG1 0x3c4
502#define COMPENSATION_REG2 0x3c8
503#define COMPENSATION_REG3 0x3cc
504#define TEST_CTL_REG 0x3d0
505
506/*
507 * SECR (OTP) registers
508 */
509#define STA2X11_SECR_CR 0x00
510#define STA2X11_SECR_FVR0 0x10
511#define STA2X11_SECR_FVR1 0x14
512
513extern int sta2x11_mfd_get_regs_data(struct platform_device *pdev,
514 enum sta2x11_mfd_plat_dev index,
515 void __iomem **regs,
516 spinlock_t **lock);
517
324#endif /* __STA2X11_MFD_H */ 518#endif /* __STA2X11_MFD_H */
diff --git a/include/linux/mfd/stmpe.h b/include/linux/mfd/stmpe.h
index f8d5b4d5843f..383ac1512a39 100644
--- a/include/linux/mfd/stmpe.h
+++ b/include/linux/mfd/stmpe.h
@@ -62,6 +62,7 @@ struct stmpe_client_info;
62 * @lock: lock protecting I/O operations 62 * @lock: lock protecting I/O operations
63 * @irq_lock: IRQ bus lock 63 * @irq_lock: IRQ bus lock
64 * @dev: device, mostly for dev_dbg() 64 * @dev: device, mostly for dev_dbg()
65 * @irq_domain: IRQ domain
65 * @client: client - i2c or spi 66 * @client: client - i2c or spi
66 * @ci: client specific information 67 * @ci: client specific information
67 * @partnum: part number 68 * @partnum: part number
@@ -79,6 +80,7 @@ struct stmpe {
79 struct mutex lock; 80 struct mutex lock;
80 struct mutex irq_lock; 81 struct mutex irq_lock;
81 struct device *dev; 82 struct device *dev;
83 struct irq_domain *domain;
82 void *client; 84 void *client;
83 struct stmpe_client_info *ci; 85 struct stmpe_client_info *ci;
84 enum stmpe_partnum partnum; 86 enum stmpe_partnum partnum;
@@ -188,7 +190,6 @@ struct stmpe_ts_platform_data {
188 * @id: device id to distinguish between multiple STMPEs on the same board 190 * @id: device id to distinguish between multiple STMPEs on the same board
189 * @blocks: bitmask of blocks to enable (use STMPE_BLOCK_*) 191 * @blocks: bitmask of blocks to enable (use STMPE_BLOCK_*)
190 * @irq_trigger: IRQ trigger to use for the interrupt to the host 192 * @irq_trigger: IRQ trigger to use for the interrupt to the host
191 * @irq_invert_polarity: IRQ line is connected with reversed polarity
192 * @autosleep: bool to enable/disable stmpe autosleep 193 * @autosleep: bool to enable/disable stmpe autosleep
193 * @autosleep_timeout: inactivity timeout in milliseconds for autosleep 194 * @autosleep_timeout: inactivity timeout in milliseconds for autosleep
194 * @irq_base: base IRQ number. %STMPE_NR_IRQS irqs will be used, or 195 * @irq_base: base IRQ number. %STMPE_NR_IRQS irqs will be used, or
@@ -205,7 +206,6 @@ struct stmpe_platform_data {
205 unsigned int blocks; 206 unsigned int blocks;
206 int irq_base; 207 int irq_base;
207 unsigned int irq_trigger; 208 unsigned int irq_trigger;
208 bool irq_invert_polarity;
209 bool autosleep; 209 bool autosleep;
210 bool irq_over_gpio; 210 bool irq_over_gpio;
211 int irq_gpio; 211 int irq_gpio;
diff --git a/include/linux/mfd/ti_am335x_tscadc.h b/include/linux/mfd/ti_am335x_tscadc.h
new file mode 100644
index 000000000000..c79ad5d2f271
--- /dev/null
+++ b/include/linux/mfd/ti_am335x_tscadc.h
@@ -0,0 +1,152 @@
1#ifndef __LINUX_TI_AM335X_TSCADC_MFD_H
2#define __LINUX_TI_AM335X_TSCADC_MFD_H
3
4/*
5 * TI Touch Screen / ADC MFD driver
6 *
7 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation version 2.
12 *
13 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
14 * kind, whether express or implied; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/mfd/core.h>
20
21#define REG_RAWIRQSTATUS 0x024
22#define REG_IRQSTATUS 0x028
23#define REG_IRQENABLE 0x02C
24#define REG_IRQCLR 0x030
25#define REG_IRQWAKEUP 0x034
26#define REG_CTRL 0x040
27#define REG_ADCFSM 0x044
28#define REG_CLKDIV 0x04C
29#define REG_SE 0x054
30#define REG_IDLECONFIG 0x058
31#define REG_CHARGECONFIG 0x05C
32#define REG_CHARGEDELAY 0x060
33#define REG_STEPCONFIG(n) (0x64 + ((n - 1) * 8))
34#define REG_STEPDELAY(n) (0x68 + ((n - 1) * 8))
35#define REG_FIFO0CNT 0xE4
36#define REG_FIFO0THR 0xE8
37#define REG_FIFO1CNT 0xF0
38#define REG_FIFO1THR 0xF4
39#define REG_FIFO0 0x100
40#define REG_FIFO1 0x200
41
42/* Register Bitfields */
43/* IRQ wakeup enable */
44#define IRQWKUP_ENB BIT(0)
45
46/* Step Enable */
47#define STEPENB_MASK (0x1FFFF << 0)
48#define STEPENB(val) ((val) << 0)
49#define STPENB_STEPENB STEPENB(0x1FFFF)
50#define STPENB_STEPENB_TC STEPENB(0x1FFF)
51
52/* IRQ enable */
53#define IRQENB_HW_PEN BIT(0)
54#define IRQENB_FIFO0THRES BIT(2)
55#define IRQENB_FIFO1THRES BIT(5)
56#define IRQENB_PENUP BIT(9)
57
58/* Step Configuration */
59#define STEPCONFIG_MODE_MASK (3 << 0)
60#define STEPCONFIG_MODE(val) ((val) << 0)
61#define STEPCONFIG_MODE_HWSYNC STEPCONFIG_MODE(2)
62#define STEPCONFIG_AVG_MASK (7 << 2)
63#define STEPCONFIG_AVG(val) ((val) << 2)
64#define STEPCONFIG_AVG_16 STEPCONFIG_AVG(4)
65#define STEPCONFIG_XPP BIT(5)
66#define STEPCONFIG_XNN BIT(6)
67#define STEPCONFIG_YPP BIT(7)
68#define STEPCONFIG_YNN BIT(8)
69#define STEPCONFIG_XNP BIT(9)
70#define STEPCONFIG_YPN BIT(10)
71#define STEPCONFIG_INM_MASK (0xF << 15)
72#define STEPCONFIG_INM(val) ((val) << 15)
73#define STEPCONFIG_INM_ADCREFM STEPCONFIG_INM(8)
74#define STEPCONFIG_INP_MASK (0xF << 19)
75#define STEPCONFIG_INP(val) ((val) << 19)
76#define STEPCONFIG_INP_AN2 STEPCONFIG_INP(2)
77#define STEPCONFIG_INP_AN3 STEPCONFIG_INP(3)
78#define STEPCONFIG_INP_AN4 STEPCONFIG_INP(4)
79#define STEPCONFIG_INP_ADCREFM STEPCONFIG_INP(8)
80#define STEPCONFIG_FIFO1 BIT(26)
81
82/* Delay register */
83#define STEPDELAY_OPEN_MASK (0x3FFFF << 0)
84#define STEPDELAY_OPEN(val) ((val) << 0)
85#define STEPCONFIG_OPENDLY STEPDELAY_OPEN(0x098)
86#define STEPDELAY_SAMPLE_MASK (0xFF << 24)
87#define STEPDELAY_SAMPLE(val) ((val) << 24)
88#define STEPCONFIG_SAMPLEDLY STEPDELAY_SAMPLE(0)
89
90/* Charge Config */
91#define STEPCHARGE_RFP_MASK (7 << 12)
92#define STEPCHARGE_RFP(val) ((val) << 12)
93#define STEPCHARGE_RFP_XPUL STEPCHARGE_RFP(1)
94#define STEPCHARGE_INM_MASK (0xF << 15)
95#define STEPCHARGE_INM(val) ((val) << 15)
96#define STEPCHARGE_INM_AN1 STEPCHARGE_INM(1)
97#define STEPCHARGE_INP_MASK (0xF << 19)
98#define STEPCHARGE_INP(val) ((val) << 19)
99#define STEPCHARGE_INP_AN1 STEPCHARGE_INP(1)
100#define STEPCHARGE_RFM_MASK (3 << 23)
101#define STEPCHARGE_RFM(val) ((val) << 23)
102#define STEPCHARGE_RFM_XNUR STEPCHARGE_RFM(1)
103
104/* Charge delay */
105#define CHARGEDLY_OPEN_MASK (0x3FFFF << 0)
106#define CHARGEDLY_OPEN(val) ((val) << 0)
107#define CHARGEDLY_OPENDLY CHARGEDLY_OPEN(1)
108
109/* Control register */
110#define CNTRLREG_TSCSSENB BIT(0)
111#define CNTRLREG_STEPID BIT(1)
112#define CNTRLREG_STEPCONFIGWRT BIT(2)
113#define CNTRLREG_POWERDOWN BIT(4)
114#define CNTRLREG_AFE_CTRL_MASK (3 << 5)
115#define CNTRLREG_AFE_CTRL(val) ((val) << 5)
116#define CNTRLREG_4WIRE CNTRLREG_AFE_CTRL(1)
117#define CNTRLREG_5WIRE CNTRLREG_AFE_CTRL(2)
118#define CNTRLREG_8WIRE CNTRLREG_AFE_CTRL(3)
119#define CNTRLREG_TSCENB BIT(7)
120
121#define ADC_CLK 3000000
122#define MAX_CLK_DIV 7
123#define TOTAL_STEPS 16
124#define TOTAL_CHANNELS 8
125
126#define TSCADC_CELLS 2
127
128enum tscadc_cells {
129 TSC_CELL,
130 ADC_CELL,
131};
132
133struct mfd_tscadc_board {
134 struct tsc_data *tsc_init;
135 struct adc_data *adc_init;
136};
137
138struct ti_tscadc_dev {
139 struct device *dev;
140 struct regmap *regmap_tscadc;
141 void __iomem *tscadc_base;
142 int irq;
143 struct mfd_cell cells[TSCADC_CELLS];
144
145 /* tsc device */
146 struct titsc *tsc;
147
148 /* adc device */
149 struct adc_device *adc;
150};
151
152#endif
diff --git a/include/linux/mfd/tps65090.h b/include/linux/mfd/tps65090.h
index 804e280c1e1d..6694cf43e8b8 100644
--- a/include/linux/mfd/tps65090.h
+++ b/include/linux/mfd/tps65090.h
@@ -23,6 +23,26 @@
23#define __LINUX_MFD_TPS65090_H 23#define __LINUX_MFD_TPS65090_H
24 24
25#include <linux/irq.h> 25#include <linux/irq.h>
26#include <linux/regmap.h>
27
28/* TPS65090 IRQs */
29enum {
30 TPS65090_IRQ_VAC_STATUS_CHANGE,
31 TPS65090_IRQ_VSYS_STATUS_CHANGE,
32 TPS65090_IRQ_BAT_STATUS_CHANGE,
33 TPS65090_IRQ_CHARGING_STATUS_CHANGE,
34 TPS65090_IRQ_CHARGING_COMPLETE,
35 TPS65090_IRQ_OVERLOAD_DCDC1,
36 TPS65090_IRQ_OVERLOAD_DCDC2,
37 TPS65090_IRQ_OVERLOAD_DCDC3,
38 TPS65090_IRQ_OVERLOAD_FET1,
39 TPS65090_IRQ_OVERLOAD_FET2,
40 TPS65090_IRQ_OVERLOAD_FET3,
41 TPS65090_IRQ_OVERLOAD_FET4,
42 TPS65090_IRQ_OVERLOAD_FET5,
43 TPS65090_IRQ_OVERLOAD_FET6,
44 TPS65090_IRQ_OVERLOAD_FET7,
45};
26 46
27/* TPS65090 Regulator ID */ 47/* TPS65090 Regulator ID */
28enum { 48enum {
@@ -44,20 +64,9 @@ enum {
44}; 64};
45 65
46struct tps65090 { 66struct tps65090 {
47 struct mutex lock;
48 struct device *dev; 67 struct device *dev;
49 struct i2c_client *client;
50 struct regmap *rmap; 68 struct regmap *rmap;
51 struct irq_chip irq_chip; 69 struct regmap_irq_chip_data *irq_data;
52 struct mutex irq_lock;
53 int irq_base;
54 unsigned int id;
55};
56
57struct tps65090_subdev_info {
58 int id;
59 const char *name;
60 void *platform_data;
61}; 70};
62 71
63/* 72/*
@@ -77,8 +86,6 @@ struct tps65090_regulator_plat_data {
77 86
78struct tps65090_platform_data { 87struct tps65090_platform_data {
79 int irq_base; 88 int irq_base;
80 int num_subdevs;
81 struct tps65090_subdev_info *subdevs;
82 struct tps65090_regulator_plat_data *reg_pdata[TPS65090_REGULATOR_MAX]; 89 struct tps65090_regulator_plat_data *reg_pdata[TPS65090_REGULATOR_MAX];
83}; 90};
84 91
@@ -86,9 +93,39 @@ struct tps65090_platform_data {
86 * NOTE: the functions below are not intended for use outside 93 * NOTE: the functions below are not intended for use outside
87 * of the TPS65090 sub-device drivers 94 * of the TPS65090 sub-device drivers
88 */ 95 */
89extern int tps65090_write(struct device *dev, int reg, uint8_t val); 96static inline int tps65090_write(struct device *dev, int reg, uint8_t val)
90extern int tps65090_read(struct device *dev, int reg, uint8_t *val); 97{
91extern int tps65090_set_bits(struct device *dev, int reg, uint8_t bit_num); 98 struct tps65090 *tps = dev_get_drvdata(dev);
92extern int tps65090_clr_bits(struct device *dev, int reg, uint8_t bit_num); 99
100 return regmap_write(tps->rmap, reg, val);
101}
102
103static inline int tps65090_read(struct device *dev, int reg, uint8_t *val)
104{
105 struct tps65090 *tps = dev_get_drvdata(dev);
106 unsigned int temp_val;
107 int ret;
108
109 ret = regmap_read(tps->rmap, reg, &temp_val);
110 if (!ret)
111 *val = temp_val;
112 return ret;
113}
114
115static inline int tps65090_set_bits(struct device *dev, int reg,
116 uint8_t bit_num)
117{
118 struct tps65090 *tps = dev_get_drvdata(dev);
119
120 return regmap_update_bits(tps->rmap, reg, BIT(bit_num), ~0u);
121}
122
123static inline int tps65090_clr_bits(struct device *dev, int reg,
124 uint8_t bit_num)
125{
126 struct tps65090 *tps = dev_get_drvdata(dev);
127
128 return regmap_update_bits(tps->rmap, reg, BIT(bit_num), 0u);
129}
93 130
94#endif /*__LINUX_MFD_TPS65090_H */ 131#endif /*__LINUX_MFD_TPS65090_H */
diff --git a/include/linux/mfd/tps6586x.h b/include/linux/mfd/tps6586x.h
index f8da0e152567..87994542573b 100644
--- a/include/linux/mfd/tps6586x.h
+++ b/include/linux/mfd/tps6586x.h
@@ -96,5 +96,6 @@ extern int tps6586x_set_bits(struct device *dev, int reg, uint8_t bit_mask);
96extern int tps6586x_clr_bits(struct device *dev, int reg, uint8_t bit_mask); 96extern int tps6586x_clr_bits(struct device *dev, int reg, uint8_t bit_mask);
97extern int tps6586x_update(struct device *dev, int reg, uint8_t val, 97extern int tps6586x_update(struct device *dev, int reg, uint8_t val,
98 uint8_t mask); 98 uint8_t mask);
99extern int tps6586x_irq_get_virq(struct device *dev, int irq);
99 100
100#endif /*__LINUX_MFD_TPS6586X_H */ 101#endif /*__LINUX_MFD_TPS6586X_H */
diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h
index 02e894f3ff45..20e433e551e3 100644
--- a/include/linux/mfd/tps65910.h
+++ b/include/linux/mfd/tps65910.h
@@ -572,6 +572,49 @@
572#define SPARE_SPARE_MASK 0xFF 572#define SPARE_SPARE_MASK 0xFF
573#define SPARE_SPARE_SHIFT 0 573#define SPARE_SPARE_SHIFT 0
574 574
575#define TPS65910_INT_STS_RTC_PERIOD_IT_MASK 0x80
576#define TPS65910_INT_STS_RTC_PERIOD_IT_SHIFT 7
577#define TPS65910_INT_STS_RTC_ALARM_IT_MASK 0x40
578#define TPS65910_INT_STS_RTC_ALARM_IT_SHIFT 6
579#define TPS65910_INT_STS_HOTDIE_IT_MASK 0x20
580#define TPS65910_INT_STS_HOTDIE_IT_SHIFT 5
581#define TPS65910_INT_STS_PWRHOLD_F_IT_MASK 0x10
582#define TPS65910_INT_STS_PWRHOLD_F_IT_SHIFT 4
583#define TPS65910_INT_STS_PWRON_LP_IT_MASK 0x08
584#define TPS65910_INT_STS_PWRON_LP_IT_SHIFT 3
585#define TPS65910_INT_STS_PWRON_IT_MASK 0x04
586#define TPS65910_INT_STS_PWRON_IT_SHIFT 2
587#define TPS65910_INT_STS_VMBHI_IT_MASK 0x02
588#define TPS65910_INT_STS_VMBHI_IT_SHIFT 1
589#define TPS65910_INT_STS_VMBDCH_IT_MASK 0x01
590#define TPS65910_INT_STS_VMBDCH_IT_SHIFT 0
591
592#define TPS65910_INT_MSK_RTC_PERIOD_IT_MSK_MASK 0x80
593#define TPS65910_INT_MSK_RTC_PERIOD_IT_MSK_SHIFT 7
594#define TPS65910_INT_MSK_RTC_ALARM_IT_MSK_MASK 0x40
595#define TPS65910_INT_MSK_RTC_ALARM_IT_MSK_SHIFT 6
596#define TPS65910_INT_MSK_HOTDIE_IT_MSK_MASK 0x20
597#define TPS65910_INT_MSK_HOTDIE_IT_MSK_SHIFT 5
598#define TPS65910_INT_MSK_PWRHOLD_IT_MSK_MASK 0x10
599#define TPS65910_INT_MSK_PWRHOLD_IT_MSK_SHIFT 4
600#define TPS65910_INT_MSK_PWRON_LP_IT_MSK_MASK 0x08
601#define TPS65910_INT_MSK_PWRON_LP_IT_MSK_SHIFT 3
602#define TPS65910_INT_MSK_PWRON_IT_MSK_MASK 0x04
603#define TPS65910_INT_MSK_PWRON_IT_MSK_SHIFT 2
604#define TPS65910_INT_MSK_VMBHI_IT_MSK_MASK 0x02
605#define TPS65910_INT_MSK_VMBHI_IT_MSK_SHIFT 1
606#define TPS65910_INT_MSK_VMBDCH_IT_MSK_MASK 0x01
607#define TPS65910_INT_MSK_VMBDCH_IT_MSK_SHIFT 0
608
609#define TPS65910_INT_STS2_GPIO0_F_IT_SHIFT 2
610#define TPS65910_INT_STS2_GPIO0_F_IT_MASK 0x02
611#define TPS65910_INT_STS2_GPIO0_R_IT_SHIFT 1
612#define TPS65910_INT_STS2_GPIO0_R_IT_MASK 0x01
613
614#define TPS65910_INT_MSK2_GPIO0_F_IT_MSK_SHIFT 2
615#define TPS65910_INT_MSK2_GPIO0_F_IT_MSK_MASK 0x02
616#define TPS65910_INT_MSK2_GPIO0_R_IT_MSK_SHIFT 1
617#define TPS65910_INT_MSK2_GPIO0_R_IT_MSK_MASK 0x01
575 618
576/*Register INT_STS (0x80) register.RegisterDescription */ 619/*Register INT_STS (0x80) register.RegisterDescription */
577#define INT_STS_RTC_PERIOD_IT_MASK 0x80 620#define INT_STS_RTC_PERIOD_IT_MASK 0x80
@@ -580,16 +623,16 @@
580#define INT_STS_RTC_ALARM_IT_SHIFT 6 623#define INT_STS_RTC_ALARM_IT_SHIFT 6
581#define INT_STS_HOTDIE_IT_MASK 0x20 624#define INT_STS_HOTDIE_IT_MASK 0x20
582#define INT_STS_HOTDIE_IT_SHIFT 5 625#define INT_STS_HOTDIE_IT_SHIFT 5
583#define INT_STS_PWRHOLD_IT_MASK 0x10 626#define INT_STS_PWRHOLD_R_IT_MASK 0x10
584#define INT_STS_PWRHOLD_IT_SHIFT 4 627#define INT_STS_PWRHOLD_R_IT_SHIFT 4
585#define INT_STS_PWRON_LP_IT_MASK 0x08 628#define INT_STS_PWRON_LP_IT_MASK 0x08
586#define INT_STS_PWRON_LP_IT_SHIFT 3 629#define INT_STS_PWRON_LP_IT_SHIFT 3
587#define INT_STS_PWRON_IT_MASK 0x04 630#define INT_STS_PWRON_IT_MASK 0x04
588#define INT_STS_PWRON_IT_SHIFT 2 631#define INT_STS_PWRON_IT_SHIFT 2
589#define INT_STS_VMBHI_IT_MASK 0x02 632#define INT_STS_VMBHI_IT_MASK 0x02
590#define INT_STS_VMBHI_IT_SHIFT 1 633#define INT_STS_VMBHI_IT_SHIFT 1
591#define INT_STS_VMBDCH_IT_MASK 0x01 634#define INT_STS_PWRHOLD_F_IT_MASK 0x01
592#define INT_STS_VMBDCH_IT_SHIFT 0 635#define INT_STS_PWRHOLD_F_IT_SHIFT 0
593 636
594 637
595/*Register INT_MSK (0x80) register.RegisterDescription */ 638/*Register INT_MSK (0x80) register.RegisterDescription */
@@ -599,16 +642,16 @@
599#define INT_MSK_RTC_ALARM_IT_MSK_SHIFT 6 642#define INT_MSK_RTC_ALARM_IT_MSK_SHIFT 6
600#define INT_MSK_HOTDIE_IT_MSK_MASK 0x20 643#define INT_MSK_HOTDIE_IT_MSK_MASK 0x20
601#define INT_MSK_HOTDIE_IT_MSK_SHIFT 5 644#define INT_MSK_HOTDIE_IT_MSK_SHIFT 5
602#define INT_MSK_PWRHOLD_IT_MSK_MASK 0x10 645#define INT_MSK_PWRHOLD_R_IT_MSK_MASK 0x10
603#define INT_MSK_PWRHOLD_IT_MSK_SHIFT 4 646#define INT_MSK_PWRHOLD_R_IT_MSK_SHIFT 4
604#define INT_MSK_PWRON_LP_IT_MSK_MASK 0x08 647#define INT_MSK_PWRON_LP_IT_MSK_MASK 0x08
605#define INT_MSK_PWRON_LP_IT_MSK_SHIFT 3 648#define INT_MSK_PWRON_LP_IT_MSK_SHIFT 3
606#define INT_MSK_PWRON_IT_MSK_MASK 0x04 649#define INT_MSK_PWRON_IT_MSK_MASK 0x04
607#define INT_MSK_PWRON_IT_MSK_SHIFT 2 650#define INT_MSK_PWRON_IT_MSK_SHIFT 2
608#define INT_MSK_VMBHI_IT_MSK_MASK 0x02 651#define INT_MSK_VMBHI_IT_MSK_MASK 0x02
609#define INT_MSK_VMBHI_IT_MSK_SHIFT 1 652#define INT_MSK_VMBHI_IT_MSK_SHIFT 1
610#define INT_MSK_VMBDCH_IT_MSK_MASK 0x01 653#define INT_MSK_PWRHOLD_F_IT_MSK_MASK 0x01
611#define INT_MSK_VMBDCH_IT_MSK_SHIFT 0 654#define INT_MSK_PWRHOLD_F_IT_MSK_SHIFT 0
612 655
613 656
614/*Register INT_STS2 (0x80) register.RegisterDescription */ 657/*Register INT_STS2 (0x80) register.RegisterDescription */
@@ -650,6 +693,14 @@
650 693
651 694
652/*Register INT_STS3 (0x80) register.RegisterDescription */ 695/*Register INT_STS3 (0x80) register.RegisterDescription */
696#define INT_STS3_PWRDN_IT_MASK 0x80
697#define INT_STS3_PWRDN_IT_SHIFT 7
698#define INT_STS3_VMBCH2_L_IT_MASK 0x40
699#define INT_STS3_VMBCH2_L_IT_SHIFT 6
700#define INT_STS3_VMBCH2_H_IT_MASK 0x20
701#define INT_STS3_VMBCH2_H_IT_SHIFT 5
702#define INT_STS3_WTCHDG_IT_MASK 0x10
703#define INT_STS3_WTCHDG_IT_SHIFT 4
653#define INT_STS3_GPIO5_F_IT_MASK 0x08 704#define INT_STS3_GPIO5_F_IT_MASK 0x08
654#define INT_STS3_GPIO5_F_IT_SHIFT 3 705#define INT_STS3_GPIO5_F_IT_SHIFT 3
655#define INT_STS3_GPIO5_R_IT_MASK 0x04 706#define INT_STS3_GPIO5_R_IT_MASK 0x04
@@ -661,6 +712,14 @@
661 712
662 713
663/*Register INT_MSK3 (0x80) register.RegisterDescription */ 714/*Register INT_MSK3 (0x80) register.RegisterDescription */
715#define INT_MSK3_PWRDN_IT_MSK_MASK 0x80
716#define INT_MSK3_PWRDN_IT_MSK_SHIFT 7
717#define INT_MSK3_VMBCH2_L_IT_MSK_MASK 0x40
718#define INT_MSK3_VMBCH2_L_IT_MSK_SHIFT 6
719#define INT_MSK3_VMBCH2_H_IT_MSK_MASK 0x20
720#define INT_MSK3_VMBCH2_H_IT_MSK_SHIFT 5
721#define INT_MSK3_WTCHDG_IT_MSK_MASK 0x10
722#define INT_MSK3_WTCHDG_IT_MSK_SHIFT 4
664#define INT_MSK3_GPIO5_F_IT_MSK_MASK 0x08 723#define INT_MSK3_GPIO5_F_IT_MSK_MASK 0x08
665#define INT_MSK3_GPIO5_F_IT_MSK_SHIFT 3 724#define INT_MSK3_GPIO5_F_IT_MSK_SHIFT 3
666#define INT_MSK3_GPIO5_R_IT_MSK_MASK 0x04 725#define INT_MSK3_GPIO5_R_IT_MSK_MASK 0x04
@@ -721,34 +780,32 @@
721#define TPS65910_IRQ_GPIO_F 9 780#define TPS65910_IRQ_GPIO_F 9
722#define TPS65910_NUM_IRQ 10 781#define TPS65910_NUM_IRQ 10
723 782
724#define TPS65911_IRQ_VBAT_VMBDCH 0 783#define TPS65911_IRQ_PWRHOLD_F 0
725#define TPS65911_IRQ_VBAT_VMBDCH2L 1 784#define TPS65911_IRQ_VBAT_VMHI 1
726#define TPS65911_IRQ_VBAT_VMBDCH2H 2 785#define TPS65911_IRQ_PWRON 2
727#define TPS65911_IRQ_VBAT_VMHI 3 786#define TPS65911_IRQ_PWRON_LP 3
728#define TPS65911_IRQ_PWRON 4 787#define TPS65911_IRQ_PWRHOLD_R 4
729#define TPS65911_IRQ_PWRON_LP 5 788#define TPS65911_IRQ_HOTDIE 5
730#define TPS65911_IRQ_PWRHOLD_F 6 789#define TPS65911_IRQ_RTC_ALARM 6
731#define TPS65911_IRQ_PWRHOLD_R 7 790#define TPS65911_IRQ_RTC_PERIOD 7
732#define TPS65911_IRQ_HOTDIE 8 791#define TPS65911_IRQ_GPIO0_R 8
733#define TPS65911_IRQ_RTC_ALARM 9 792#define TPS65911_IRQ_GPIO0_F 9
734#define TPS65911_IRQ_RTC_PERIOD 10 793#define TPS65911_IRQ_GPIO1_R 10
735#define TPS65911_IRQ_GPIO0_R 11 794#define TPS65911_IRQ_GPIO1_F 11
736#define TPS65911_IRQ_GPIO0_F 12 795#define TPS65911_IRQ_GPIO2_R 12
737#define TPS65911_IRQ_GPIO1_R 13 796#define TPS65911_IRQ_GPIO2_F 13
738#define TPS65911_IRQ_GPIO1_F 14 797#define TPS65911_IRQ_GPIO3_R 14
739#define TPS65911_IRQ_GPIO2_R 15 798#define TPS65911_IRQ_GPIO3_F 15
740#define TPS65911_IRQ_GPIO2_F 16 799#define TPS65911_IRQ_GPIO4_R 16
741#define TPS65911_IRQ_GPIO3_R 17 800#define TPS65911_IRQ_GPIO4_F 17
742#define TPS65911_IRQ_GPIO3_F 18 801#define TPS65911_IRQ_GPIO5_R 18
743#define TPS65911_IRQ_GPIO4_R 19 802#define TPS65911_IRQ_GPIO5_F 19
744#define TPS65911_IRQ_GPIO4_F 20 803#define TPS65911_IRQ_WTCHDG 20
745#define TPS65911_IRQ_GPIO5_R 21 804#define TPS65911_IRQ_VMBCH2_H 21
746#define TPS65911_IRQ_GPIO5_F 22 805#define TPS65911_IRQ_VMBCH2_L 22
747#define TPS65911_IRQ_WTCHDG 23 806#define TPS65911_IRQ_PWRDN 23
748#define TPS65911_IRQ_PWRDN 24 807
749 808#define TPS65911_NUM_IRQ 24
750#define TPS65911_NUM_IRQ 25
751
752 809
753/* GPIO Register Definitions */ 810/* GPIO Register Definitions */
754#define TPS65910_GPIO_DEB BIT(2) 811#define TPS65910_GPIO_DEB BIT(2)
@@ -836,7 +893,6 @@ struct tps65910 {
836 struct device *dev; 893 struct device *dev;
837 struct i2c_client *i2c_client; 894 struct i2c_client *i2c_client;
838 struct regmap *regmap; 895 struct regmap *regmap;
839 struct mutex io_mutex;
840 unsigned int id; 896 unsigned int id;
841 897
842 /* Client devices */ 898 /* Client devices */
@@ -848,12 +904,8 @@ struct tps65910 {
848 struct tps65910_board *of_plat_data; 904 struct tps65910_board *of_plat_data;
849 905
850 /* IRQ Handling */ 906 /* IRQ Handling */
851 struct mutex irq_lock;
852 int chip_irq; 907 int chip_irq;
853 int irq_base; 908 struct regmap_irq_chip_data *irq_data;
854 int irq_num;
855 u32 irq_mask;
856 struct irq_domain *domain;
857}; 909};
858 910
859struct tps65910_platform_data { 911struct tps65910_platform_data {
@@ -861,10 +913,6 @@ struct tps65910_platform_data {
861 int irq_base; 913 int irq_base;
862}; 914};
863 915
864int tps65910_irq_init(struct tps65910 *tps65910, int irq,
865 struct tps65910_platform_data *pdata);
866int tps65910_irq_exit(struct tps65910 *tps65910);
867
868static inline int tps65910_chip_id(struct tps65910 *tps65910) 916static inline int tps65910_chip_id(struct tps65910 *tps65910)
869{ 917{
870 return tps65910->id; 918 return tps65910->id;
@@ -900,4 +948,9 @@ static inline int tps65910_reg_update_bits(struct tps65910 *tps65910, u8 reg,
900 return regmap_update_bits(tps65910->regmap, reg, mask, val); 948 return regmap_update_bits(tps65910->regmap, reg, mask, val);
901} 949}
902 950
951static inline int tps65910_irq_get_virq(struct tps65910 *tps65910, int irq)
952{
953 return regmap_irq_get_virq(tps65910->irq_data, irq);
954}
955
903#endif /* __LINUX_MFD_TPS65910_H */ 956#endif /* __LINUX_MFD_TPS65910_H */
diff --git a/include/linux/mfd/tps80031.h b/include/linux/mfd/tps80031.h
new file mode 100644
index 000000000000..2c75c9c9318f
--- /dev/null
+++ b/include/linux/mfd/tps80031.h
@@ -0,0 +1,637 @@
1/*
2 * tps80031.h -- TI TPS80031 and TI TPS80032 PMIC driver.
3 *
4 * Copyright (c) 2012, NVIDIA Corporation.
5 *
6 * Author: Laxman Dewangan <ldewangan@nvidia.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation version 2.
11 *
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
13 * whether express or implied; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
20 * 02111-1307, USA
21 */
22
23#ifndef __LINUX_MFD_TPS80031_H
24#define __LINUX_MFD_TPS80031_H
25
26#include <linux/device.h>
27#include <linux/regmap.h>
28
29/* Pull-ups/Pull-downs */
30#define TPS80031_CFG_INPUT_PUPD1 0xF0
31#define TPS80031_CFG_INPUT_PUPD2 0xF1
32#define TPS80031_CFG_INPUT_PUPD3 0xF2
33#define TPS80031_CFG_INPUT_PUPD4 0xF3
34#define TPS80031_CFG_LDO_PD1 0xF4
35#define TPS80031_CFG_LDO_PD2 0xF5
36#define TPS80031_CFG_SMPS_PD 0xF6
37
38/* Real Time Clock */
39#define TPS80031_SECONDS_REG 0x00
40#define TPS80031_MINUTES_REG 0x01
41#define TPS80031_HOURS_REG 0x02
42#define TPS80031_DAYS_REG 0x03
43#define TPS80031_MONTHS_REG 0x04
44#define TPS80031_YEARS_REG 0x05
45#define TPS80031_WEEKS_REG 0x06
46#define TPS80031_ALARM_SECONDS_REG 0x08
47#define TPS80031_ALARM_MINUTES_REG 0x09
48#define TPS80031_ALARM_HOURS_REG 0x0A
49#define TPS80031_ALARM_DAYS_REG 0x0B
50#define TPS80031_ALARM_MONTHS_REG 0x0C
51#define TPS80031_ALARM_YEARS_REG 0x0D
52#define TPS80031_RTC_CTRL_REG 0x10
53#define TPS80031_RTC_STATUS_REG 0x11
54#define TPS80031_RTC_INTERRUPTS_REG 0x12
55#define TPS80031_RTC_COMP_LSB_REG 0x13
56#define TPS80031_RTC_COMP_MSB_REG 0x14
57#define TPS80031_RTC_RESET_STATUS_REG 0x16
58
59/*PMC Master Module */
60#define TPS80031_PHOENIX_START_CONDITION 0x1F
61#define TPS80031_PHOENIX_MSK_TRANSITION 0x20
62#define TPS80031_STS_HW_CONDITIONS 0x21
63#define TPS80031_PHOENIX_LAST_TURNOFF_STS 0x22
64#define TPS80031_VSYSMIN_LO_THRESHOLD 0x23
65#define TPS80031_VSYSMIN_HI_THRESHOLD 0x24
66#define TPS80031_PHOENIX_DEV_ON 0x25
67#define TPS80031_STS_PWR_GRP_STATE 0x27
68#define TPS80031_PH_CFG_VSYSLOW 0x28
69#define TPS80031_PH_STS_BOOT 0x29
70#define TPS80031_PHOENIX_SENS_TRANSITION 0x2A
71#define TPS80031_PHOENIX_SEQ_CFG 0x2B
72#define TPS80031_PRIMARY_WATCHDOG_CFG 0X2C
73#define TPS80031_KEY_PRESS_DUR_CFG 0X2D
74#define TPS80031_SMPS_LDO_SHORT_STS 0x2E
75
76/* PMC Slave Module - Broadcast */
77#define TPS80031_BROADCAST_ADDR_ALL 0x31
78#define TPS80031_BROADCAST_ADDR_REF 0x32
79#define TPS80031_BROADCAST_ADDR_PROV 0x33
80#define TPS80031_BROADCAST_ADDR_CLK_RST 0x34
81
82/* PMC Slave Module SMPS Regulators */
83#define TPS80031_SMPS4_CFG_TRANS 0x41
84#define TPS80031_SMPS4_CFG_STATE 0x42
85#define TPS80031_SMPS4_CFG_VOLTAGE 0x44
86#define TPS80031_VIO_CFG_TRANS 0x47
87#define TPS80031_VIO_CFG_STATE 0x48
88#define TPS80031_VIO_CFG_FORCE 0x49
89#define TPS80031_VIO_CFG_VOLTAGE 0x4A
90#define TPS80031_VIO_CFG_STEP 0x48
91#define TPS80031_SMPS1_CFG_TRANS 0x53
92#define TPS80031_SMPS1_CFG_STATE 0x54
93#define TPS80031_SMPS1_CFG_FORCE 0x55
94#define TPS80031_SMPS1_CFG_VOLTAGE 0x56
95#define TPS80031_SMPS1_CFG_STEP 0x57
96#define TPS80031_SMPS2_CFG_TRANS 0x59
97#define TPS80031_SMPS2_CFG_STATE 0x5A
98#define TPS80031_SMPS2_CFG_FORCE 0x5B
99#define TPS80031_SMPS2_CFG_VOLTAGE 0x5C
100#define TPS80031_SMPS2_CFG_STEP 0x5D
101#define TPS80031_SMPS3_CFG_TRANS 0x65
102#define TPS80031_SMPS3_CFG_STATE 0x66
103#define TPS80031_SMPS3_CFG_VOLTAGE 0x68
104
105/* PMC Slave Module LDO Regulators */
106#define TPS80031_VANA_CFG_TRANS 0x81
107#define TPS80031_VANA_CFG_STATE 0x82
108#define TPS80031_VANA_CFG_VOLTAGE 0x83
109#define TPS80031_LDO2_CFG_TRANS 0x85
110#define TPS80031_LDO2_CFG_STATE 0x86
111#define TPS80031_LDO2_CFG_VOLTAGE 0x87
112#define TPS80031_LDO4_CFG_TRANS 0x89
113#define TPS80031_LDO4_CFG_STATE 0x8A
114#define TPS80031_LDO4_CFG_VOLTAGE 0x8B
115#define TPS80031_LDO3_CFG_TRANS 0x8D
116#define TPS80031_LDO3_CFG_STATE 0x8E
117#define TPS80031_LDO3_CFG_VOLTAGE 0x8F
118#define TPS80031_LDO6_CFG_TRANS 0x91
119#define TPS80031_LDO6_CFG_STATE 0x92
120#define TPS80031_LDO6_CFG_VOLTAGE 0x93
121#define TPS80031_LDOLN_CFG_TRANS 0x95
122#define TPS80031_LDOLN_CFG_STATE 0x96
123#define TPS80031_LDOLN_CFG_VOLTAGE 0x97
124#define TPS80031_LDO5_CFG_TRANS 0x99
125#define TPS80031_LDO5_CFG_STATE 0x9A
126#define TPS80031_LDO5_CFG_VOLTAGE 0x9B
127#define TPS80031_LDO1_CFG_TRANS 0x9D
128#define TPS80031_LDO1_CFG_STATE 0x9E
129#define TPS80031_LDO1_CFG_VOLTAGE 0x9F
130#define TPS80031_LDOUSB_CFG_TRANS 0xA1
131#define TPS80031_LDOUSB_CFG_STATE 0xA2
132#define TPS80031_LDOUSB_CFG_VOLTAGE 0xA3
133#define TPS80031_LDO7_CFG_TRANS 0xA5
134#define TPS80031_LDO7_CFG_STATE 0xA6
135#define TPS80031_LDO7_CFG_VOLTAGE 0xA7
136
137/* PMC Slave Module External Control */
138#define TPS80031_REGEN1_CFG_TRANS 0xAE
139#define TPS80031_REGEN1_CFG_STATE 0xAF
140#define TPS80031_REGEN2_CFG_TRANS 0xB1
141#define TPS80031_REGEN2_CFG_STATE 0xB2
142#define TPS80031_SYSEN_CFG_TRANS 0xB4
143#define TPS80031_SYSEN_CFG_STATE 0xB5
144
145/* PMC Slave Module Internal Control */
146#define TPS80031_NRESPWRON_CFG_TRANS 0xB7
147#define TPS80031_NRESPWRON_CFG_STATE 0xB8
148#define TPS80031_CLK32KAO_CFG_TRANS 0xBA
149#define TPS80031_CLK32KAO_CFG_STATE 0xBB
150#define TPS80031_CLK32KG_CFG_TRANS 0xBD
151#define TPS80031_CLK32KG_CFG_STATE 0xBE
152#define TPS80031_CLK32KAUDIO_CFG_TRANS 0xC0
153#define TPS80031_CLK32KAUDIO_CFG_STATE 0xC1
154#define TPS80031_VRTC_CFG_TRANS 0xC3
155#define TPS80031_VRTC_CFG_STATE 0xC4
156#define TPS80031_BIAS_CFG_TRANS 0xC6
157#define TPS80031_BIAS_CFG_STATE 0xC7
158#define TPS80031_VSYSMIN_HI_CFG_TRANS 0xC9
159#define TPS80031_VSYSMIN_HI_CFG_STATE 0xCA
160#define TPS80031_RC6MHZ_CFG_TRANS 0xCC
161#define TPS80031_RC6MHZ_CFG_STATE 0xCD
162#define TPS80031_TMP_CFG_TRANS 0xCF
163#define TPS80031_TMP_CFG_STATE 0xD0
164
165/* PMC Slave Module resources assignment */
166#define TPS80031_PREQ1_RES_ASS_A 0xD7
167#define TPS80031_PREQ1_RES_ASS_B 0xD8
168#define TPS80031_PREQ1_RES_ASS_C 0xD9
169#define TPS80031_PREQ2_RES_ASS_A 0xDA
170#define TPS80031_PREQ2_RES_ASS_B 0xDB
171#define TPS80031_PREQ2_RES_ASS_C 0xDC
172#define TPS80031_PREQ3_RES_ASS_A 0xDD
173#define TPS80031_PREQ3_RES_ASS_B 0xDE
174#define TPS80031_PREQ3_RES_ASS_C 0xDF
175
176/* PMC Slave Module Miscellaneous */
177#define TPS80031_SMPS_OFFSET 0xE0
178#define TPS80031_SMPS_MULT 0xE3
179#define TPS80031_MISC1 0xE4
180#define TPS80031_MISC2 0xE5
181#define TPS80031_BBSPOR_CFG 0xE6
182#define TPS80031_TMP_CFG 0xE7
183
184/* Battery Charging Controller and Indicator LED */
185#define TPS80031_CONTROLLER_CTRL2 0xDA
186#define TPS80031_CONTROLLER_VSEL_COMP 0xDB
187#define TPS80031_CHARGERUSB_VSYSREG 0xDC
188#define TPS80031_CHARGERUSB_VICHRG_PC 0xDD
189#define TPS80031_LINEAR_CHRG_STS 0xDE
190#define TPS80031_CONTROLLER_INT_MASK 0xE0
191#define TPS80031_CONTROLLER_CTRL1 0xE1
192#define TPS80031_CONTROLLER_WDG 0xE2
193#define TPS80031_CONTROLLER_STAT1 0xE3
194#define TPS80031_CHARGERUSB_INT_STATUS 0xE4
195#define TPS80031_CHARGERUSB_INT_MASK 0xE5
196#define TPS80031_CHARGERUSB_STATUS_INT1 0xE6
197#define TPS80031_CHARGERUSB_STATUS_INT2 0xE7
198#define TPS80031_CHARGERUSB_CTRL1 0xE8
199#define TPS80031_CHARGERUSB_CTRL2 0xE9
200#define TPS80031_CHARGERUSB_CTRL3 0xEA
201#define TPS80031_CHARGERUSB_STAT1 0xEB
202#define TPS80031_CHARGERUSB_VOREG 0xEC
203#define TPS80031_CHARGERUSB_VICHRG 0xED
204#define TPS80031_CHARGERUSB_CINLIMIT 0xEE
205#define TPS80031_CHARGERUSB_CTRLLIMIT1 0xEF
206#define TPS80031_CHARGERUSB_CTRLLIMIT2 0xF0
207#define TPS80031_LED_PWM_CTRL1 0xF4
208#define TPS80031_LED_PWM_CTRL2 0xF5
209
210/* USB On-The-Go */
211#define TPS80031_BACKUP_REG 0xFA
212#define TPS80031_USB_VENDOR_ID_LSB 0x00
213#define TPS80031_USB_VENDOR_ID_MSB 0x01
214#define TPS80031_USB_PRODUCT_ID_LSB 0x02
215#define TPS80031_USB_PRODUCT_ID_MSB 0x03
216#define TPS80031_USB_VBUS_CTRL_SET 0x04
217#define TPS80031_USB_VBUS_CTRL_CLR 0x05
218#define TPS80031_USB_ID_CTRL_SET 0x06
219#define TPS80031_USB_ID_CTRL_CLR 0x07
220#define TPS80031_USB_VBUS_INT_SRC 0x08
221#define TPS80031_USB_VBUS_INT_LATCH_SET 0x09
222#define TPS80031_USB_VBUS_INT_LATCH_CLR 0x0A
223#define TPS80031_USB_VBUS_INT_EN_LO_SET 0x0B
224#define TPS80031_USB_VBUS_INT_EN_LO_CLR 0x0C
225#define TPS80031_USB_VBUS_INT_EN_HI_SET 0x0D
226#define TPS80031_USB_VBUS_INT_EN_HI_CLR 0x0E
227#define TPS80031_USB_ID_INT_SRC 0x0F
228#define TPS80031_USB_ID_INT_LATCH_SET 0x10
229#define TPS80031_USB_ID_INT_LATCH_CLR 0x11
230#define TPS80031_USB_ID_INT_EN_LO_SET 0x12
231#define TPS80031_USB_ID_INT_EN_LO_CLR 0x13
232#define TPS80031_USB_ID_INT_EN_HI_SET 0x14
233#define TPS80031_USB_ID_INT_EN_HI_CLR 0x15
234#define TPS80031_USB_OTG_ADP_CTRL 0x16
235#define TPS80031_USB_OTG_ADP_HIGH 0x17
236#define TPS80031_USB_OTG_ADP_LOW 0x18
237#define TPS80031_USB_OTG_ADP_RISE 0x19
238#define TPS80031_USB_OTG_REVISION 0x1A
239
240/* Gas Gauge */
241#define TPS80031_FG_REG_00 0xC0
242#define TPS80031_FG_REG_01 0xC1
243#define TPS80031_FG_REG_02 0xC2
244#define TPS80031_FG_REG_03 0xC3
245#define TPS80031_FG_REG_04 0xC4
246#define TPS80031_FG_REG_05 0xC5
247#define TPS80031_FG_REG_06 0xC6
248#define TPS80031_FG_REG_07 0xC7
249#define TPS80031_FG_REG_08 0xC8
250#define TPS80031_FG_REG_09 0xC9
251#define TPS80031_FG_REG_10 0xCA
252#define TPS80031_FG_REG_11 0xCB
253
254/* General Purpose ADC */
255#define TPS80031_GPADC_CTRL 0x2E
256#define TPS80031_GPADC_CTRL2 0x2F
257#define TPS80031_RTSELECT_LSB 0x32
258#define TPS80031_RTSELECT_ISB 0x33
259#define TPS80031_RTSELECT_MSB 0x34
260#define TPS80031_GPSELECT_ISB 0x35
261#define TPS80031_CTRL_P1 0x36
262#define TPS80031_RTCH0_LSB 0x37
263#define TPS80031_RTCH0_MSB 0x38
264#define TPS80031_RTCH1_LSB 0x39
265#define TPS80031_RTCH1_MSB 0x3A
266#define TPS80031_GPCH0_LSB 0x3B
267#define TPS80031_GPCH0_MSB 0x3C
268
269/* SIM, MMC and Battery Detection */
270#define TPS80031_SIMDEBOUNCING 0xEB
271#define TPS80031_SIMCTRL 0xEC
272#define TPS80031_MMCDEBOUNCING 0xED
273#define TPS80031_MMCCTRL 0xEE
274#define TPS80031_BATDEBOUNCING 0xEF
275
276/* Vibrator Driver and PWMs */
277#define TPS80031_VIBCTRL 0x9B
278#define TPS80031_VIBMODE 0x9C
279#define TPS80031_PWM1ON 0xBA
280#define TPS80031_PWM1OFF 0xBB
281#define TPS80031_PWM2ON 0xBD
282#define TPS80031_PWM2OFF 0xBE
283
284/* Control Interface */
285#define TPS80031_INT_STS_A 0xD0
286#define TPS80031_INT_STS_B 0xD1
287#define TPS80031_INT_STS_C 0xD2
288#define TPS80031_INT_MSK_LINE_A 0xD3
289#define TPS80031_INT_MSK_LINE_B 0xD4
290#define TPS80031_INT_MSK_LINE_C 0xD5
291#define TPS80031_INT_MSK_STS_A 0xD6
292#define TPS80031_INT_MSK_STS_B 0xD7
293#define TPS80031_INT_MSK_STS_C 0xD8
294#define TPS80031_TOGGLE1 0x90
295#define TPS80031_TOGGLE2 0x91
296#define TPS80031_TOGGLE3 0x92
297#define TPS80031_PWDNSTATUS1 0x93
298#define TPS80031_PWDNSTATUS2 0x94
299#define TPS80031_VALIDITY0 0x17
300#define TPS80031_VALIDITY1 0x18
301#define TPS80031_VALIDITY2 0x19
302#define TPS80031_VALIDITY3 0x1A
303#define TPS80031_VALIDITY4 0x1B
304#define TPS80031_VALIDITY5 0x1C
305#define TPS80031_VALIDITY6 0x1D
306#define TPS80031_VALIDITY7 0x1E
307
308/* Version number related register */
309#define TPS80031_JTAGVERNUM 0x87
310#define TPS80031_EPROM_REV 0xDF
311
312/* GPADC Trimming Bits. */
313#define TPS80031_GPADC_TRIM0 0xCC
314#define TPS80031_GPADC_TRIM1 0xCD
315#define TPS80031_GPADC_TRIM2 0xCE
316#define TPS80031_GPADC_TRIM3 0xCF
317#define TPS80031_GPADC_TRIM4 0xD0
318#define TPS80031_GPADC_TRIM5 0xD1
319#define TPS80031_GPADC_TRIM6 0xD2
320#define TPS80031_GPADC_TRIM7 0xD3
321#define TPS80031_GPADC_TRIM8 0xD4
322#define TPS80031_GPADC_TRIM9 0xD5
323#define TPS80031_GPADC_TRIM10 0xD6
324#define TPS80031_GPADC_TRIM11 0xD7
325#define TPS80031_GPADC_TRIM12 0xD8
326#define TPS80031_GPADC_TRIM13 0xD9
327#define TPS80031_GPADC_TRIM14 0xDA
328#define TPS80031_GPADC_TRIM15 0xDB
329#define TPS80031_GPADC_TRIM16 0xDC
330#define TPS80031_GPADC_TRIM17 0xDD
331#define TPS80031_GPADC_TRIM18 0xDE
332
333/* TPS80031_CONTROLLER_STAT1 bit fields */
334#define TPS80031_CONTROLLER_STAT1_BAT_TEMP 0
335#define TPS80031_CONTROLLER_STAT1_BAT_REMOVED 1
336#define TPS80031_CONTROLLER_STAT1_VBUS_DET 2
337#define TPS80031_CONTROLLER_STAT1_VAC_DET 3
338#define TPS80031_CONTROLLER_STAT1_FAULT_WDG 4
339#define TPS80031_CONTROLLER_STAT1_LINCH_GATED 6
340/* TPS80031_CONTROLLER_INT_MASK bit filed */
341#define TPS80031_CONTROLLER_INT_MASK_MVAC_DET 0
342#define TPS80031_CONTROLLER_INT_MASK_MVBUS_DET 1
343#define TPS80031_CONTROLLER_INT_MASK_MBAT_TEMP 2
344#define TPS80031_CONTROLLER_INT_MASK_MFAULT_WDG 3
345#define TPS80031_CONTROLLER_INT_MASK_MBAT_REMOVED 4
346#define TPS80031_CONTROLLER_INT_MASK_MLINCH_GATED 5
347
348#define TPS80031_CHARGE_CONTROL_SUB_INT_MASK 0x3F
349
350/* TPS80031_PHOENIX_DEV_ON bit field */
351#define TPS80031_DEVOFF 0x1
352
353#define TPS80031_EXT_CONTROL_CFG_TRANS 0
354#define TPS80031_EXT_CONTROL_CFG_STATE 1
355
356/* State register field */
357#define TPS80031_STATE_OFF 0x00
358#define TPS80031_STATE_ON 0x01
359#define TPS80031_STATE_MASK 0x03
360
361/* Trans register field */
362#define TPS80031_TRANS_ACTIVE_OFF 0x00
363#define TPS80031_TRANS_ACTIVE_ON 0x01
364#define TPS80031_TRANS_ACTIVE_MASK 0x03
365#define TPS80031_TRANS_SLEEP_OFF 0x00
366#define TPS80031_TRANS_SLEEP_ON 0x04
367#define TPS80031_TRANS_SLEEP_MASK 0x0C
368#define TPS80031_TRANS_OFF_OFF 0x00
369#define TPS80031_TRANS_OFF_ACTIVE 0x10
370#define TPS80031_TRANS_OFF_MASK 0x30
371
372#define TPS80031_EXT_PWR_REQ (TPS80031_PWR_REQ_INPUT_PREQ1 | \
373 TPS80031_PWR_REQ_INPUT_PREQ2 | \
374 TPS80031_PWR_REQ_INPUT_PREQ3)
375
376/* TPS80031_BBSPOR_CFG bit field */
377#define TPS80031_BBSPOR_CHG_EN 0x8
378#define TPS80031_MAX_REGISTER 0xFF
379
380struct i2c_client;
381
382/* Supported chips */
383enum chips {
384 TPS80031 = 0x00000001,
385 TPS80032 = 0x00000002,
386};
387
388enum {
389 TPS80031_INT_PWRON,
390 TPS80031_INT_RPWRON,
391 TPS80031_INT_SYS_VLOW,
392 TPS80031_INT_RTC_ALARM,
393 TPS80031_INT_RTC_PERIOD,
394 TPS80031_INT_HOT_DIE,
395 TPS80031_INT_VXX_SHORT,
396 TPS80031_INT_SPDURATION,
397 TPS80031_INT_WATCHDOG,
398 TPS80031_INT_BAT,
399 TPS80031_INT_SIM,
400 TPS80031_INT_MMC,
401 TPS80031_INT_RES,
402 TPS80031_INT_GPADC_RT,
403 TPS80031_INT_GPADC_SW2_EOC,
404 TPS80031_INT_CC_AUTOCAL,
405 TPS80031_INT_ID_WKUP,
406 TPS80031_INT_VBUSS_WKUP,
407 TPS80031_INT_ID,
408 TPS80031_INT_VBUS,
409 TPS80031_INT_CHRG_CTRL,
410 TPS80031_INT_EXT_CHRG,
411 TPS80031_INT_INT_CHRG,
412 TPS80031_INT_RES2,
413 TPS80031_INT_BAT_TEMP_OVRANGE,
414 TPS80031_INT_BAT_REMOVED,
415 TPS80031_INT_VBUS_DET,
416 TPS80031_INT_VAC_DET,
417 TPS80031_INT_FAULT_WDG,
418 TPS80031_INT_LINCH_GATED,
419
420 /* Last interrupt id to get the end number */
421 TPS80031_INT_NR,
422};
423
424/* TPS80031 Slave IDs */
425#define TPS80031_NUM_SLAVES 4
426#define TPS80031_SLAVE_ID0 0
427#define TPS80031_SLAVE_ID1 1
428#define TPS80031_SLAVE_ID2 2
429#define TPS80031_SLAVE_ID3 3
430
431/* TPS80031 I2C addresses */
432#define TPS80031_I2C_ID0_ADDR 0x12
433#define TPS80031_I2C_ID1_ADDR 0x48
434#define TPS80031_I2C_ID2_ADDR 0x49
435#define TPS80031_I2C_ID3_ADDR 0x4A
436
437enum {
438 TPS80031_REGULATOR_VIO,
439 TPS80031_REGULATOR_SMPS1,
440 TPS80031_REGULATOR_SMPS2,
441 TPS80031_REGULATOR_SMPS3,
442 TPS80031_REGULATOR_SMPS4,
443 TPS80031_REGULATOR_VANA,
444 TPS80031_REGULATOR_LDO1,
445 TPS80031_REGULATOR_LDO2,
446 TPS80031_REGULATOR_LDO3,
447 TPS80031_REGULATOR_LDO4,
448 TPS80031_REGULATOR_LDO5,
449 TPS80031_REGULATOR_LDO6,
450 TPS80031_REGULATOR_LDO7,
451 TPS80031_REGULATOR_LDOLN,
452 TPS80031_REGULATOR_LDOUSB,
453 TPS80031_REGULATOR_VBUS,
454 TPS80031_REGULATOR_REGEN1,
455 TPS80031_REGULATOR_REGEN2,
456 TPS80031_REGULATOR_SYSEN,
457 TPS80031_REGULATOR_MAX,
458};
459
460/* Different configurations for the rails */
461enum {
462 /* USBLDO input selection */
463 TPS80031_USBLDO_INPUT_VSYS = 0x00000001,
464 TPS80031_USBLDO_INPUT_PMID = 0x00000002,
465
466 /* LDO3 output mode */
467 TPS80031_LDO3_OUTPUT_VIB = 0x00000004,
468
469 /* VBUS configuration */
470 TPS80031_VBUS_DISCHRG_EN_PDN = 0x00000004,
471 TPS80031_VBUS_SW_ONLY = 0x00000008,
472 TPS80031_VBUS_SW_N_ID = 0x00000010,
473};
474
475/* External controls requests */
476enum tps80031_ext_control {
477 TPS80031_PWR_REQ_INPUT_NONE = 0x00000000,
478 TPS80031_PWR_REQ_INPUT_PREQ1 = 0x00000001,
479 TPS80031_PWR_REQ_INPUT_PREQ2 = 0x00000002,
480 TPS80031_PWR_REQ_INPUT_PREQ3 = 0x00000004,
481 TPS80031_PWR_OFF_ON_SLEEP = 0x00000008,
482 TPS80031_PWR_ON_ON_SLEEP = 0x00000010,
483};
484
485enum tps80031_pupd_pins {
486 TPS80031_PREQ1 = 0,
487 TPS80031_PREQ2A,
488 TPS80031_PREQ2B,
489 TPS80031_PREQ2C,
490 TPS80031_PREQ3,
491 TPS80031_NRES_WARM,
492 TPS80031_PWM_FORCE,
493 TPS80031_CHRG_EXT_CHRG_STATZ,
494 TPS80031_SIM,
495 TPS80031_MMC,
496 TPS80031_GPADC_START,
497 TPS80031_DVSI2C_SCL,
498 TPS80031_DVSI2C_SDA,
499 TPS80031_CTLI2C_SCL,
500 TPS80031_CTLI2C_SDA,
501};
502
503enum tps80031_pupd_settings {
504 TPS80031_PUPD_NORMAL,
505 TPS80031_PUPD_PULLDOWN,
506 TPS80031_PUPD_PULLUP,
507};
508
509struct tps80031 {
510 struct device *dev;
511 unsigned long chip_info;
512 int es_version;
513 struct i2c_client *clients[TPS80031_NUM_SLAVES];
514 struct regmap *regmap[TPS80031_NUM_SLAVES];
515 struct regmap_irq_chip_data *irq_data;
516};
517
518struct tps80031_pupd_init_data {
519 int input_pin;
520 int setting;
521};
522
523/*
524 * struct tps80031_regulator_platform_data - tps80031 regulator platform data.
525 *
526 * @reg_init_data: The regulator init data.
527 * @ext_ctrl_flag: External control flag for sleep/power request control.
528 * @config_flags: Configuration flag to configure the rails.
529 * It should be ORed of config enums.
530 */
531
532struct tps80031_regulator_platform_data {
533 struct regulator_init_data *reg_init_data;
534 unsigned int ext_ctrl_flag;
535 unsigned int config_flags;
536};
537
538struct tps80031_platform_data {
539 int irq_base;
540 bool use_power_off;
541 struct tps80031_pupd_init_data *pupd_init_data;
542 int pupd_init_data_size;
543 struct tps80031_regulator_platform_data
544 *regulator_pdata[TPS80031_REGULATOR_MAX];
545};
546
547static inline int tps80031_write(struct device *dev, int sid,
548 int reg, uint8_t val)
549{
550 struct tps80031 *tps80031 = dev_get_drvdata(dev);
551
552 return regmap_write(tps80031->regmap[sid], reg, val);
553}
554
555static inline int tps80031_writes(struct device *dev, int sid, int reg,
556 int len, uint8_t *val)
557{
558 struct tps80031 *tps80031 = dev_get_drvdata(dev);
559
560 return regmap_bulk_write(tps80031->regmap[sid], reg, val, len);
561}
562
563static inline int tps80031_read(struct device *dev, int sid,
564 int reg, uint8_t *val)
565{
566 struct tps80031 *tps80031 = dev_get_drvdata(dev);
567 unsigned int ival;
568 int ret;
569
570 ret = regmap_read(tps80031->regmap[sid], reg, &ival);
571 if (ret < 0) {
572 dev_err(dev, "failed reading from reg 0x%02x\n", reg);
573 return ret;
574 }
575
576 *val = ival;
577 return ret;
578}
579
580static inline int tps80031_reads(struct device *dev, int sid,
581 int reg, int len, uint8_t *val)
582{
583 struct tps80031 *tps80031 = dev_get_drvdata(dev);
584
585 return regmap_bulk_read(tps80031->regmap[sid], reg, val, len);
586}
587
588static inline int tps80031_set_bits(struct device *dev, int sid,
589 int reg, uint8_t bit_mask)
590{
591 struct tps80031 *tps80031 = dev_get_drvdata(dev);
592
593 return regmap_update_bits(tps80031->regmap[sid], reg,
594 bit_mask, bit_mask);
595}
596
597static inline int tps80031_clr_bits(struct device *dev, int sid,
598 int reg, uint8_t bit_mask)
599{
600 struct tps80031 *tps80031 = dev_get_drvdata(dev);
601
602 return regmap_update_bits(tps80031->regmap[sid], reg, bit_mask, 0);
603}
604
605static inline int tps80031_update(struct device *dev, int sid,
606 int reg, uint8_t val, uint8_t mask)
607{
608 struct tps80031 *tps80031 = dev_get_drvdata(dev);
609
610 return regmap_update_bits(tps80031->regmap[sid], reg, mask, val);
611}
612
613static inline unsigned long tps80031_get_chip_info(struct device *dev)
614{
615 struct tps80031 *tps80031 = dev_get_drvdata(dev);
616
617 return tps80031->chip_info;
618}
619
620static inline int tps80031_get_pmu_version(struct device *dev)
621{
622 struct tps80031 *tps80031 = dev_get_drvdata(dev);
623
624 return tps80031->es_version;
625}
626
627static inline int tps80031_irq_get_virq(struct device *dev, int irq)
628{
629 struct tps80031 *tps80031 = dev_get_drvdata(dev);
630
631 return regmap_irq_get_virq(tps80031->irq_data, irq);
632}
633
634extern int tps80031_ext_power_req_config(struct device *dev,
635 unsigned long ext_ctrl_flag, int preq_bit,
636 int state_reg_add, int trans_reg_add);
637#endif /*__LINUX_MFD_TPS80031_H */
diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h
index a8eff4ad9be5..94ac944d12f0 100644
--- a/include/linux/mfd/twl6040.h
+++ b/include/linux/mfd/twl6040.h
@@ -207,10 +207,12 @@ struct twl6040_platform_data {
207}; 207};
208 208
209struct regmap; 209struct regmap;
210struct regmap_irq_chips_data;
210 211
211struct twl6040 { 212struct twl6040 {
212 struct device *dev; 213 struct device *dev;
213 struct regmap *regmap; 214 struct regmap *regmap;
215 struct regmap_irq_chip_data *irq_data;
214 struct regulator_bulk_data supplies[2]; /* supplies for vio, v2v1 */ 216 struct regulator_bulk_data supplies[2]; /* supplies for vio, v2v1 */
215 struct mutex mutex; 217 struct mutex mutex;
216 struct mutex irq_mutex; 218 struct mutex irq_mutex;
@@ -228,9 +230,8 @@ struct twl6040 {
228 unsigned int mclk; 230 unsigned int mclk;
229 231
230 unsigned int irq; 232 unsigned int irq;
231 unsigned int irq_base; 233 unsigned int irq_ready;
232 u8 irq_masks_cur; 234 unsigned int irq_th;
233 u8 irq_masks_cache;
234}; 235};
235 236
236int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg); 237int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg);
@@ -245,8 +246,7 @@ int twl6040_set_pll(struct twl6040 *twl6040, int pll_id,
245 unsigned int freq_in, unsigned int freq_out); 246 unsigned int freq_in, unsigned int freq_out);
246int twl6040_get_pll(struct twl6040 *twl6040); 247int twl6040_get_pll(struct twl6040 *twl6040);
247unsigned int twl6040_get_sysclk(struct twl6040 *twl6040); 248unsigned int twl6040_get_sysclk(struct twl6040 *twl6040);
248int twl6040_irq_init(struct twl6040 *twl6040); 249
249void twl6040_irq_exit(struct twl6040 *twl6040);
250/* Get the combined status of the vibra control register */ 250/* Get the combined status of the vibra control register */
251int twl6040_get_vibralr_status(struct twl6040 *twl6040); 251int twl6040_get_vibralr_status(struct twl6040 *twl6040);
252 252
diff --git a/include/linux/mfd/viperboard.h b/include/linux/mfd/viperboard.h
new file mode 100644
index 000000000000..193452848c04
--- /dev/null
+++ b/include/linux/mfd/viperboard.h
@@ -0,0 +1,110 @@
1/*
2 * include/linux/mfd/viperboard.h
3 *
4 * Nano River Technologies viperboard definitions
5 *
6 * (C) 2012 by Lemonage GmbH
7 * Author: Lars Poeschel <poeschel@lemonage.de>
8 * All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16
17#ifndef __MFD_VIPERBOARD_H__
18#define __MFD_VIPERBOARD_H__
19
20#include <linux/types.h>
21#include <linux/usb.h>
22
23#define VPRBRD_EP_OUT 0x02
24#define VPRBRD_EP_IN 0x86
25
26#define VPRBRD_I2C_MSG_LEN 512 /* max length of a msg on USB level */
27
28#define VPRBRD_I2C_FREQ_6MHZ 1 /* 6 MBit/s */
29#define VPRBRD_I2C_FREQ_3MHZ 2 /* 3 MBit/s */
30#define VPRBRD_I2C_FREQ_1MHZ 3 /* 1 MBit/s */
31#define VPRBRD_I2C_FREQ_FAST 4 /* 400 kbit/s */
32#define VPRBRD_I2C_FREQ_400KHZ VPRBRD_I2C_FREQ_FAST
33#define VPRBRD_I2C_FREQ_200KHZ 5 /* 200 kbit/s */
34#define VPRBRD_I2C_FREQ_STD 6 /* 100 kbit/s */
35#define VPRBRD_I2C_FREQ_100KHZ VPRBRD_I2C_FREQ_STD
36#define VPRBRD_I2C_FREQ_10KHZ 7 /* 10 kbit/s */
37
38#define VPRBRD_I2C_CMD_WRITE 0x00
39#define VPRBRD_I2C_CMD_READ 0x01
40#define VPRBRD_I2C_CMD_ADDR 0x02
41
42#define VPRBRD_USB_TYPE_OUT 0x40
43#define VPRBRD_USB_TYPE_IN 0xc0
44#define VPRBRD_USB_TIMEOUT_MS 100
45#define VPRBRD_USB_REQUEST_I2C_FREQ 0xe6
46#define VPRBRD_USB_REQUEST_I2C 0xe9
47#define VPRBRD_USB_REQUEST_MAJOR 0xea
48#define VPRBRD_USB_REQUEST_MINOR 0xeb
49#define VPRBRD_USB_REQUEST_ADC 0xec
50#define VPRBRD_USB_REQUEST_GPIOA 0xed
51#define VPRBRD_USB_REQUEST_GPIOB 0xdd
52
53struct vprbrd_i2c_write_hdr {
54 u8 cmd;
55 u16 addr;
56 u8 len1;
57 u8 len2;
58 u8 last;
59 u8 chan;
60 u16 spi;
61} __packed;
62
63struct vprbrd_i2c_read_hdr {
64 u8 cmd;
65 u16 addr;
66 u8 len0;
67 u8 len1;
68 u8 len2;
69 u8 len3;
70 u8 len4;
71 u8 len5;
72 u16 tf1; /* transfer 1 length */
73 u16 tf2; /* transfer 2 length */
74} __packed;
75
76struct vprbrd_i2c_status {
77 u8 unknown[11];
78 u8 status;
79} __packed;
80
81struct vprbrd_i2c_write_msg {
82 struct vprbrd_i2c_write_hdr header;
83 u8 data[VPRBRD_I2C_MSG_LEN
84 - sizeof(struct vprbrd_i2c_write_hdr)];
85} __packed;
86
87struct vprbrd_i2c_read_msg {
88 struct vprbrd_i2c_read_hdr header;
89 u8 data[VPRBRD_I2C_MSG_LEN
90 - sizeof(struct vprbrd_i2c_read_hdr)];
91} __packed;
92
93struct vprbrd_i2c_addr_msg {
94 u8 cmd;
95 u8 addr;
96 u8 unknown1;
97 u16 len;
98 u8 unknown2;
99 u8 unknown3;
100} __packed;
101
102/* Structure to hold all device specific stuff */
103struct vprbrd {
104 struct usb_device *usb_dev; /* the usb device for this device */
105 struct mutex lock;
106 u8 buf[sizeof(struct vprbrd_i2c_write_msg)];
107 struct platform_device pdev;
108};
109
110#endif /* __MFD_VIPERBOARD_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 15:55:36 -0500