mfd: rtsx: Modify rts5249_optimize_phy

In some platforms, specially Thinkpad series, rts5249 won't be
initialized properly. So we need adjust some phy parameters to
improve the compatibility issue.

It is a little different between simulation and real chip. We have
no idea about which configuration is better before tape-out. We set
default settings according to simulation, but need to tune these
parameters after getting the real chip.

I can't explain every change in detail here. The below information is
just a rough description:

PHY_REG_REV: Disable internal clkreq_tx, enable rx_pwst
PHY_BPCR: No change, just turn the magic number to macro definitions
PHY_PCR: Change OOBS sensitivity, from 60mV to 90mV
PHY_RCR2: Control charge-pump current automatically
PHY_FLD4: Use TX cmu reference clock
PHY_RDR: Change RXDSEL from 30nF to 1.9nF
PHY_RCR1: Change the duration between adp_st and asserting cp_en from
0.32 us to 0.64us
PHY_FLD3: Adjust internal timers
PHY_TUNE: Fine tune the regulator12 output voltage

Signed-off-by: Wei WANG <wei_wang@realsil.com.cn>
Signed-off-by: Lee Jones <lee.jones@linaro.org>

1 files changed, 53 insertions, 0 deletions

diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h
index d1382dfbeff0..0ce772105508 100644
--- a/include/linux/mfd/rtsx_pci.h
+++ b/include/linux/mfd/rtsx_pci.h
@@ -756,6 +756,59 @@
 #define PCR_SETTING_REG2                0x814
 #define PCR_SETTING_REG3                0x747
 
+/* Phy bits */
+#define PHY_PCR_FORCE_CODE                      0xB000
+#define PHY_PCR_OOBS_CALI_50                    0x0800
+#define PHY_PCR_OOBS_VCM_08                     0x0200
+#define PHY_PCR_OOBS_SEN_90                     0x0040
+#define PHY_PCR_RSSI_EN                         0x0002
+
+#define PHY_RCR1_ADP_TIME                       0x0100
+#define PHY_RCR1_VCO_COARSE                     0x001F
+
+#define PHY_RCR2_EMPHASE_EN                     0x8000
+#define PHY_RCR2_NADJR                          0x4000
+#define PHY_RCR2_CDR_CP_10                      0x0400
+#define PHY_RCR2_CDR_SR_2                       0x0100
+#define PHY_RCR2_FREQSEL_12                     0x0040
+#define PHY_RCR2_CPADJEN                        0x0020
+#define PHY_RCR2_CDR_SC_8                       0x0008
+#define PHY_RCR2_CALIB_LATE                     0x0002
+
+#define PHY_RDR_RXDSEL_1_9                      0x4000
+
+#define PHY_TUNE_TUNEREF_1_0                    0x4000
+#define PHY_TUNE_VBGSEL_1252                    0x0C00
+#define PHY_TUNE_SDBUS_33                       0x0200
+#define PHY_TUNE_TUNED18                        0x01C0
+#define PHY_TUNE_TUNED12                        0X0020
+
+#define PHY_BPCR_IBRXSEL                        0x0400
+#define PHY_BPCR_IBTXSEL                        0x0100
+#define PHY_BPCR_IB_FILTER                      0x0080
+#define PHY_BPCR_CMIRROR_EN                     0x0040
+
+#define PHY_REG_REV_RESV                        0xE000
+#define PHY_REG_REV_RXIDLE_LATCHED              0x1000
+#define PHY_REG_REV_P1_EN                       0x0800
+#define PHY_REG_REV_RXIDLE_EN                   0x0400
+#define PHY_REG_REV_CLKREQ_DLY_TIMER_1_0        0x0040
+#define PHY_REG_REV_STOP_CLKRD                  0x0020
+#define PHY_REG_REV_RX_PWST                     0x0008
+#define PHY_REG_REV_STOP_CLKWR                  0x0004
+
+#define PHY_FLD3_TIMER_4                        0x7800
+#define PHY_FLD3_TIMER_6                        0x00E0
+#define PHY_FLD3_RXDELINK                       0x0004
+
+#define PHY_FLD4_FLDEN_SEL                      0x4000
+#define PHY_FLD4_REQ_REF                        0x2000
+#define PHY_FLD4_RXAMP_OFF                      0x1000
+#define PHY_FLD4_REQ_ADDA                       0x0800
+#define PHY_FLD4_BER_COUNT                      0x00E0
+#define PHY_FLD4_BER_TIMER                      0x000A
+#define PHY_FLD4_BER_CHK_EN                     0x0001
+
 #define rtsx_pci_init_cmd(pcr)          ((pcr)->ci = 0)
 
 struct rtsx_pcr;