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authorSangbeom Kim <sbkim73@samsung.com>2011-12-23 03:28:08 -0500
committerSamuel Ortiz <sameo@linux.intel.com>2012-01-08 18:37:46 -0500
commit0f5f70783eddde2bd277ae521fa04226cb1e249d (patch)
tree28c14534b369f0748bc0e1a9f164eff713774071 /include/linux/mfd
parent5d26dc821ad214906d63bbeda5cdb95ac9798ab0 (diff)
mfd: Add S5M core driver
S5M series are pmic including mutiple functional devices. It can support PMIC, RTC, Battery charger, codec. This patch implement core driver for s5m series. Signed-off-by: Sangbeom Kim <sbkim73@samsung.com> Reviewed-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Diffstat (limited to 'include/linux/mfd')
-rw-r--r--include/linux/mfd/s5m87xx/s5m-core.h373
-rw-r--r--include/linux/mfd/s5m87xx/s5m-pmic.h100
-rw-r--r--include/linux/mfd/s5m87xx/s5m-rtc.h84
3 files changed, 557 insertions, 0 deletions
diff --git a/include/linux/mfd/s5m87xx/s5m-core.h b/include/linux/mfd/s5m87xx/s5m-core.h
new file mode 100644
index 000000000000..a7480b57f92d
--- /dev/null
+++ b/include/linux/mfd/s5m87xx/s5m-core.h
@@ -0,0 +1,373 @@
1/*
2 * s5m-core.h
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14#ifndef __LINUX_MFD_S5M_CORE_H
15#define __LINUX_MFD_S5M_CORE_H
16
17#define NUM_IRQ_REGS 4
18
19enum s5m_device_type {
20 S5M8751X,
21 S5M8763X,
22 S5M8767X,
23};
24
25/* S5M8767 registers */
26enum s5m8767_reg {
27 S5M8767_REG_ID,
28 S5M8767_REG_INT1,
29 S5M8767_REG_INT2,
30 S5M8767_REG_INT3,
31 S5M8767_REG_INT1M,
32 S5M8767_REG_INT2M,
33 S5M8767_REG_INT3M,
34 S5M8767_REG_STATUS1,
35 S5M8767_REG_STATUS2,
36 S5M8767_REG_STATUS3,
37 S5M8767_REG_CTRL1,
38 S5M8767_REG_CTRL2,
39 S5M8767_REG_LOWBAT1,
40 S5M8767_REG_LOWBAT2,
41 S5M8767_REG_BUCHG,
42 S5M8767_REG_DVSRAMP,
43 S5M8767_REG_DVSTIMER2 = 0x10,
44 S5M8767_REG_DVSTIMER3,
45 S5M8767_REG_DVSTIMER4,
46 S5M8767_REG_LDO1,
47 S5M8767_REG_LDO2,
48 S5M8767_REG_LDO3,
49 S5M8767_REG_LDO4,
50 S5M8767_REG_LDO5,
51 S5M8767_REG_LDO6,
52 S5M8767_REG_LDO7,
53 S5M8767_REG_LDO8,
54 S5M8767_REG_LDO9,
55 S5M8767_REG_LDO10,
56 S5M8767_REG_LDO11,
57 S5M8767_REG_LDO12,
58 S5M8767_REG_LDO13,
59 S5M8767_REG_LDO14 = 0x20,
60 S5M8767_REG_LDO15,
61 S5M8767_REG_LDO16,
62 S5M8767_REG_LDO17,
63 S5M8767_REG_LDO18,
64 S5M8767_REG_LDO19,
65 S5M8767_REG_LDO20,
66 S5M8767_REG_LDO21,
67 S5M8767_REG_LDO22,
68 S5M8767_REG_LDO23,
69 S5M8767_REG_LDO24,
70 S5M8767_REG_LDO25,
71 S5M8767_REG_LDO26,
72 S5M8767_REG_LDO27,
73 S5M8767_REG_LDO28,
74 S5M8767_REG_UVLO = 0x31,
75 S5M8767_REG_BUCK1CTRL1,
76 S5M8767_REG_BUCK1CTRL2,
77 S5M8767_REG_BUCK2CTRL,
78 S5M8767_REG_BUCK2DVS1,
79 S5M8767_REG_BUCK2DVS2,
80 S5M8767_REG_BUCK2DVS3,
81 S5M8767_REG_BUCK2DVS4,
82 S5M8767_REG_BUCK2DVS5,
83 S5M8767_REG_BUCK2DVS6,
84 S5M8767_REG_BUCK2DVS7,
85 S5M8767_REG_BUCK2DVS8,
86 S5M8767_REG_BUCK3CTRL,
87 S5M8767_REG_BUCK3DVS1,
88 S5M8767_REG_BUCK3DVS2,
89 S5M8767_REG_BUCK3DVS3,
90 S5M8767_REG_BUCK3DVS4,
91 S5M8767_REG_BUCK3DVS5,
92 S5M8767_REG_BUCK3DVS6,
93 S5M8767_REG_BUCK3DVS7,
94 S5M8767_REG_BUCK3DVS8,
95 S5M8767_REG_BUCK4CTRL,
96 S5M8767_REG_BUCK4DVS1,
97 S5M8767_REG_BUCK4DVS2,
98 S5M8767_REG_BUCK4DVS3,
99 S5M8767_REG_BUCK4DVS4,
100 S5M8767_REG_BUCK4DVS5,
101 S5M8767_REG_BUCK4DVS6,
102 S5M8767_REG_BUCK4DVS7,
103 S5M8767_REG_BUCK4DVS8,
104 S5M8767_REG_BUCK5CTRL1,
105 S5M8767_REG_BUCK5CTRL2,
106 S5M8767_REG_BUCK5CTRL3,
107 S5M8767_REG_BUCK5CTRL4,
108 S5M8767_REG_BUCK5CTRL5,
109 S5M8767_REG_BUCK6CTRL1,
110 S5M8767_REG_BUCK6CTRL2,
111 S5M8767_REG_BUCK7CTRL1,
112 S5M8767_REG_BUCK7CTRL2,
113 S5M8767_REG_BUCK8CTRL1,
114 S5M8767_REG_BUCK8CTRL2,
115 S5M8767_REG_BUCK9CTRL1,
116 S5M8767_REG_BUCK9CTRL2,
117 S5M8767_REG_LDO1CTRL,
118 S5M8767_REG_LDO2_1CTRL,
119 S5M8767_REG_LDO2_2CTRL,
120 S5M8767_REG_LDO2_3CTRL,
121 S5M8767_REG_LDO2_4CTRL,
122 S5M8767_REG_LDO3CTRL,
123 S5M8767_REG_LDO4CTRL,
124 S5M8767_REG_LDO5CTRL,
125 S5M8767_REG_LDO6CTRL,
126 S5M8767_REG_LDO7CTRL,
127 S5M8767_REG_LDO8CTRL,
128 S5M8767_REG_LDO9CTRL,
129 S5M8767_REG_LDO10CTRL,
130 S5M8767_REG_LDO11CTRL,
131 S5M8767_REG_LDO12CTRL,
132 S5M8767_REG_LDO13CTRL,
133 S5M8767_REG_LDO14CTRL,
134 S5M8767_REG_LDO15CTRL,
135 S5M8767_REG_LDO16CTRL,
136 S5M8767_REG_LDO17CTRL,
137 S5M8767_REG_LDO18CTRL,
138 S5M8767_REG_LDO19CTRL,
139 S5M8767_REG_LDO20CTRL,
140 S5M8767_REG_LDO21CTRL,
141 S5M8767_REG_LDO22CTRL,
142 S5M8767_REG_LDO23CTRL,
143 S5M8767_REG_LDO24CTRL,
144 S5M8767_REG_LDO25CTRL,
145 S5M8767_REG_LDO26CTRL,
146 S5M8767_REG_LDO27CTRL,
147 S5M8767_REG_LDO28CTRL,
148};
149
150/* S5M8763 registers */
151enum s5m8763_reg {
152 S5M8763_REG_IRQ1,
153 S5M8763_REG_IRQ2,
154 S5M8763_REG_IRQ3,
155 S5M8763_REG_IRQ4,
156 S5M8763_REG_IRQM1,
157 S5M8763_REG_IRQM2,
158 S5M8763_REG_IRQM3,
159 S5M8763_REG_IRQM4,
160 S5M8763_REG_STATUS1,
161 S5M8763_REG_STATUS2,
162 S5M8763_REG_STATUSM1,
163 S5M8763_REG_STATUSM2,
164 S5M8763_REG_CHGR1,
165 S5M8763_REG_CHGR2,
166 S5M8763_REG_LDO_ACTIVE_DISCHARGE1,
167 S5M8763_REG_LDO_ACTIVE_DISCHARGE2,
168 S5M8763_REG_BUCK_ACTIVE_DISCHARGE3,
169 S5M8763_REG_ONOFF1,
170 S5M8763_REG_ONOFF2,
171 S5M8763_REG_ONOFF3,
172 S5M8763_REG_ONOFF4,
173 S5M8763_REG_BUCK1_VOLTAGE1,
174 S5M8763_REG_BUCK1_VOLTAGE2,
175 S5M8763_REG_BUCK1_VOLTAGE3,
176 S5M8763_REG_BUCK1_VOLTAGE4,
177 S5M8763_REG_BUCK2_VOLTAGE1,
178 S5M8763_REG_BUCK2_VOLTAGE2,
179 S5M8763_REG_BUCK3,
180 S5M8763_REG_BUCK4,
181 S5M8763_REG_LDO1_LDO2,
182 S5M8763_REG_LDO3,
183 S5M8763_REG_LDO4,
184 S5M8763_REG_LDO5,
185 S5M8763_REG_LDO6,
186 S5M8763_REG_LDO7,
187 S5M8763_REG_LDO7_LDO8,
188 S5M8763_REG_LDO9_LDO10,
189 S5M8763_REG_LDO11,
190 S5M8763_REG_LDO12,
191 S5M8763_REG_LDO13,
192 S5M8763_REG_LDO14,
193 S5M8763_REG_LDO15,
194 S5M8763_REG_LDO16,
195 S5M8763_REG_BKCHR,
196 S5M8763_REG_LBCNFG1,
197 S5M8763_REG_LBCNFG2,
198};
199
200enum s5m8767_irq {
201 S5M8767_IRQ_PWRR,
202 S5M8767_IRQ_PWRF,
203 S5M8767_IRQ_PWR1S,
204 S5M8767_IRQ_JIGR,
205 S5M8767_IRQ_JIGF,
206 S5M8767_IRQ_LOWBAT2,
207 S5M8767_IRQ_LOWBAT1,
208
209 S5M8767_IRQ_MRB,
210 S5M8767_IRQ_DVSOK2,
211 S5M8767_IRQ_DVSOK3,
212 S5M8767_IRQ_DVSOK4,
213
214 S5M8767_IRQ_RTC60S,
215 S5M8767_IRQ_RTCA1,
216 S5M8767_IRQ_RTCA2,
217 S5M8767_IRQ_SMPL,
218 S5M8767_IRQ_RTC1S,
219 S5M8767_IRQ_WTSR,
220
221 S5M8767_IRQ_NR,
222};
223
224#define S5M8767_IRQ_PWRR_MASK (1 << 0)
225#define S5M8767_IRQ_PWRF_MASK (1 << 1)
226#define S5M8767_IRQ_PWR1S_MASK (1 << 3)
227#define S5M8767_IRQ_JIGR_MASK (1 << 4)
228#define S5M8767_IRQ_JIGF_MASK (1 << 5)
229#define S5M8767_IRQ_LOWBAT2_MASK (1 << 6)
230#define S5M8767_IRQ_LOWBAT1_MASK (1 << 7)
231
232#define S5M8767_IRQ_MRB_MASK (1 << 2)
233#define S5M8767_IRQ_DVSOK2_MASK (1 << 3)
234#define S5M8767_IRQ_DVSOK3_MASK (1 << 4)
235#define S5M8767_IRQ_DVSOK4_MASK (1 << 5)
236
237#define S5M8767_IRQ_RTC60S_MASK (1 << 0)
238#define S5M8767_IRQ_RTCA1_MASK (1 << 1)
239#define S5M8767_IRQ_RTCA2_MASK (1 << 2)
240#define S5M8767_IRQ_SMPL_MASK (1 << 3)
241#define S5M8767_IRQ_RTC1S_MASK (1 << 4)
242#define S5M8767_IRQ_WTSR_MASK (1 << 5)
243
244enum s5m8763_irq {
245 S5M8763_IRQ_DCINF,
246 S5M8763_IRQ_DCINR,
247 S5M8763_IRQ_JIGF,
248 S5M8763_IRQ_JIGR,
249 S5M8763_IRQ_PWRONF,
250 S5M8763_IRQ_PWRONR,
251
252 S5M8763_IRQ_WTSREVNT,
253 S5M8763_IRQ_SMPLEVNT,
254 S5M8763_IRQ_ALARM1,
255 S5M8763_IRQ_ALARM0,
256
257 S5M8763_IRQ_ONKEY1S,
258 S5M8763_IRQ_TOPOFFR,
259 S5M8763_IRQ_DCINOVPR,
260 S5M8763_IRQ_CHGRSTF,
261 S5M8763_IRQ_DONER,
262 S5M8763_IRQ_CHGFAULT,
263
264 S5M8763_IRQ_LOBAT1,
265 S5M8763_IRQ_LOBAT2,
266
267 S5M8763_IRQ_NR,
268};
269
270#define S5M8763_IRQ_DCINF_MASK (1 << 2)
271#define S5M8763_IRQ_DCINR_MASK (1 << 3)
272#define S5M8763_IRQ_JIGF_MASK (1 << 4)
273#define S5M8763_IRQ_JIGR_MASK (1 << 5)
274#define S5M8763_IRQ_PWRONF_MASK (1 << 6)
275#define S5M8763_IRQ_PWRONR_MASK (1 << 7)
276
277#define S5M8763_IRQ_WTSREVNT_MASK (1 << 0)
278#define S5M8763_IRQ_SMPLEVNT_MASK (1 << 1)
279#define S5M8763_IRQ_ALARM1_MASK (1 << 2)
280#define S5M8763_IRQ_ALARM0_MASK (1 << 3)
281
282#define S5M8763_IRQ_ONKEY1S_MASK (1 << 0)
283#define S5M8763_IRQ_TOPOFFR_MASK (1 << 2)
284#define S5M8763_IRQ_DCINOVPR_MASK (1 << 3)
285#define S5M8763_IRQ_CHGRSTF_MASK (1 << 4)
286#define S5M8763_IRQ_DONER_MASK (1 << 5)
287#define S5M8763_IRQ_CHGFAULT_MASK (1 << 7)
288
289#define S5M8763_IRQ_LOBAT1_MASK (1 << 0)
290#define S5M8763_IRQ_LOBAT2_MASK (1 << 1)
291
292#define S5M8763_ENRAMP (1 << 4)
293
294/**
295 * struct s5m87xx_dev - s5m87xx master device for sub-drivers
296 * @dev: master device of the chip (can be used to access platform data)
297 * @i2c: i2c client private data for regulator
298 * @rtc: i2c client private data for rtc
299 * @iolock: mutex for serializing io access
300 * @irqlock: mutex for buslock
301 * @irq_base: base IRQ number for s5m87xx, required for IRQs
302 * @irq: generic IRQ number for s5m87xx
303 * @ono: power onoff IRQ number for s5m87xx
304 * @irq_masks_cur: currently active value
305 * @irq_masks_cache: cached hardware value
306 * @type: indicate which s5m87xx "variant" is used
307 */
308struct s5m87xx_dev {
309 struct device *dev;
310 struct regmap *regmap;
311 struct i2c_client *i2c;
312 struct i2c_client *rtc;
313 struct mutex iolock;
314 struct mutex irqlock;
315
316 int device_type;
317 int irq_base;
318 int irq;
319 int ono;
320 u8 irq_masks_cur[NUM_IRQ_REGS];
321 u8 irq_masks_cache[NUM_IRQ_REGS];
322 int type;
323 bool wakeup;
324};
325
326int s5m_irq_init(struct s5m87xx_dev *s5m87xx);
327void s5m_irq_exit(struct s5m87xx_dev *s5m87xx);
328int s5m_irq_resume(struct s5m87xx_dev *s5m87xx);
329
330extern int s5m_reg_read(struct s5m87xx_dev *s5m87xx, u8 reg, void *dest);
331extern int s5m_bulk_read(struct s5m87xx_dev *s5m87xx, u8 reg, int count, u8 *buf);
332extern int s5m_reg_write(struct s5m87xx_dev *s5m87xx, u8 reg, u8 value);
333extern int s5m_bulk_write(struct s5m87xx_dev *s5m87xx, u8 reg, int count, u8 *buf);
334extern int s5m_reg_update(struct s5m87xx_dev *s5m87xx, u8 reg, u8 val, u8 mask);
335
336struct s5m_platform_data {
337 struct s5m_regulator_data *regulators;
338 int device_type;
339 int num_regulators;
340
341 int irq_base;
342 int (*cfg_pmic_irq)(void);
343
344 int ono;
345 bool wakeup;
346 bool buck_voltage_lock;
347
348 int buck_gpios[3];
349 int buck2_voltage[8];
350 bool buck2_gpiodvs;
351 int buck3_voltage[8];
352 bool buck3_gpiodvs;
353 int buck4_voltage[8];
354 bool buck4_gpiodvs;
355
356 int buck_set1;
357 int buck_set2;
358 int buck_set3;
359 int buck2_enable;
360 int buck3_enable;
361 int buck4_enable;
362 int buck_default_idx;
363 int buck2_default_idx;
364 int buck3_default_idx;
365 int buck4_default_idx;
366
367 int buck_ramp_delay;
368 bool buck2_ramp_enable;
369 bool buck3_ramp_enable;
370 bool buck4_ramp_enable;
371};
372
373#endif /* __LINUX_MFD_S5M_CORE_H */
diff --git a/include/linux/mfd/s5m87xx/s5m-pmic.h b/include/linux/mfd/s5m87xx/s5m-pmic.h
new file mode 100644
index 000000000000..a72a5d27e62e
--- /dev/null
+++ b/include/linux/mfd/s5m87xx/s5m-pmic.h
@@ -0,0 +1,100 @@
1/* s5m87xx.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#ifndef __LINUX_MFD_S5M_PMIC_H
12#define __LINUX_MFD_S5M_PMIC_H
13
14#include <linux/regulator/machine.h>
15
16/* S5M8767 regulator ids */
17enum s5m8767_regulators {
18 S5M8767_LDO1,
19 S5M8767_LDO2,
20 S5M8767_LDO3,
21 S5M8767_LDO4,
22 S5M8767_LDO5,
23 S5M8767_LDO6,
24 S5M8767_LDO7,
25 S5M8767_LDO8,
26 S5M8767_LDO9,
27 S5M8767_LDO10,
28 S5M8767_LDO11,
29 S5M8767_LDO12,
30 S5M8767_LDO13,
31 S5M8767_LDO14,
32 S5M8767_LDO15,
33 S5M8767_LDO16,
34 S5M8767_LDO17,
35 S5M8767_LDO18,
36 S5M8767_LDO19,
37 S5M8767_LDO20,
38 S5M8767_LDO21,
39 S5M8767_LDO22,
40 S5M8767_LDO23,
41 S5M8767_LDO24,
42 S5M8767_LDO25,
43 S5M8767_LDO26,
44 S5M8767_LDO27,
45 S5M8767_LDO28,
46 S5M8767_BUCK1,
47 S5M8767_BUCK2,
48 S5M8767_BUCK3,
49 S5M8767_BUCK4,
50 S5M8767_BUCK5,
51 S5M8767_BUCK6,
52 S5M8767_BUCK7,
53 S5M8767_BUCK8,
54 S5M8767_BUCK9,
55 S5M8767_AP_EN32KHZ,
56 S5M8767_CP_EN32KHZ,
57
58 S5M8767_REG_MAX,
59};
60
61/* S5M8763 regulator ids */
62enum s5m8763_regulators {
63 S5M8763_LDO1,
64 S5M8763_LDO2,
65 S5M8763_LDO3,
66 S5M8763_LDO4,
67 S5M8763_LDO5,
68 S5M8763_LDO6,
69 S5M8763_LDO7,
70 S5M8763_LDO8,
71 S5M8763_LDO9,
72 S5M8763_LDO10,
73 S5M8763_LDO11,
74 S5M8763_LDO12,
75 S5M8763_LDO13,
76 S5M8763_LDO14,
77 S5M8763_LDO15,
78 S5M8763_LDO16,
79 S5M8763_BUCK1,
80 S5M8763_BUCK2,
81 S5M8763_BUCK3,
82 S5M8763_BUCK4,
83 S5M8763_AP_EN32KHZ,
84 S5M8763_CP_EN32KHZ,
85 S5M8763_ENCHGVI,
86 S5M8763_ESAFEUSB1,
87 S5M8763_ESAFEUSB2,
88};
89
90/**
91 * s5m87xx_regulator_data - regulator data
92 * @id: regulator id
93 * @initdata: regulator init data (contraints, supplies, ...)
94 */
95struct s5m_regulator_data {
96 int id;
97 struct regulator_init_data *initdata;
98};
99
100#endif /* __LINUX_MFD_S5M_PMIC_H */
diff --git a/include/linux/mfd/s5m87xx/s5m-rtc.h b/include/linux/mfd/s5m87xx/s5m-rtc.h
new file mode 100644
index 000000000000..6ce8da264cec
--- /dev/null
+++ b/include/linux/mfd/s5m87xx/s5m-rtc.h
@@ -0,0 +1,84 @@
1/*
2 * s5m-rtc.h
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14#ifndef __LINUX_MFD_S5M_RTC_H
15#define __LINUX_MFD_S5M_RTC_H
16
17enum s5m87xx_rtc_reg {
18 S5M87XX_RTC_SEC,
19 S5M87XX_RTC_MIN,
20 S5M87XX_RTC_HOUR,
21 S5M87XX_RTC_WEEKDAY,
22 S5M87XX_RTC_DATE,
23 S5M87XX_RTC_MONTH,
24 S5M87XX_RTC_YEAR1,
25 S5M87XX_RTC_YEAR2,
26 S5M87XX_ALARM0_SEC,
27 S5M87XX_ALARM0_MIN,
28 S5M87XX_ALARM0_HOUR,
29 S5M87XX_ALARM0_WEEKDAY,
30 S5M87XX_ALARM0_DATE,
31 S5M87XX_ALARM0_MONTH,
32 S5M87XX_ALARM0_YEAR1,
33 S5M87XX_ALARM0_YEAR2,
34 S5M87XX_ALARM1_SEC,
35 S5M87XX_ALARM1_MIN,
36 S5M87XX_ALARM1_HOUR,
37 S5M87XX_ALARM1_WEEKDAY,
38 S5M87XX_ALARM1_DATE,
39 S5M87XX_ALARM1_MONTH,
40 S5M87XX_ALARM1_YEAR1,
41 S5M87XX_ALARM1_YEAR2,
42 S5M87XX_ALARM0_CONF,
43 S5M87XX_ALARM1_CONF,
44 S5M87XX_RTC_STATUS,
45 S5M87XX_WTSR_SMPL_CNTL,
46 S5M87XX_RTC_UDR_CON,
47};
48
49#define RTC_I2C_ADDR (0x0C >> 1)
50
51#define HOUR_12 (1 << 7)
52#define HOUR_AMPM (1 << 6)
53#define HOUR_PM (1 << 5)
54#define ALARM0_STATUS (1 << 1)
55#define ALARM1_STATUS (1 << 2)
56#define UPDATE_AD (1 << 0)
57
58/* RTC Control Register */
59#define BCD_EN_SHIFT 0
60#define BCD_EN_MASK (1 << BCD_EN_SHIFT)
61#define MODEL24_SHIFT 1
62#define MODEL24_MASK (1 << MODEL24_SHIFT)
63/* RTC Update Register1 */
64#define RTC_UDR_SHIFT 0
65#define RTC_UDR_MASK (1 << RTC_UDR_SHIFT)
66/* RTC Hour register */
67#define HOUR_PM_SHIFT 6
68#define HOUR_PM_MASK (1 << HOUR_PM_SHIFT)
69/* RTC Alarm Enable */
70#define ALARM_ENABLE_SHIFT 7
71#define ALARM_ENABLE_MASK (1 << ALARM_ENABLE_SHIFT)
72
73enum {
74 RTC_SEC = 0,
75 RTC_MIN,
76 RTC_HOUR,
77 RTC_WEEKDAY,
78 RTC_DATE,
79 RTC_MONTH,
80 RTC_YEAR1,
81 RTC_YEAR2,
82};
83
84#endif /* __LINUX_MFD_S5M_RTC_H */
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-06 15:59:21 -0400