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authorGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
committerGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
commitc71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch)
treeecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /include/linux/mfd/tmio.h
parentea53c912f8a86a8567697115b6a0d8152beee5c8 (diff)
parent6a00f206debf8a5c8899055726ad127dbeeed098 (diff)
Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp
Conflicts: litmus/sched_cedf.c
Diffstat (limited to 'include/linux/mfd/tmio.h')
-rw-r--r--include/linux/mfd/tmio.h28
1 files changed, 28 insertions, 0 deletions
diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h
index f07425bc3dcd..5a90266c3a5a 100644
--- a/include/linux/mfd/tmio.h
+++ b/include/linux/mfd/tmio.h
@@ -4,6 +4,7 @@
4#include <linux/fb.h> 4#include <linux/fb.h>
5#include <linux/io.h> 5#include <linux/io.h>
6#include <linux/platform_device.h> 6#include <linux/platform_device.h>
7#include <linux/pm_runtime.h>
7 8
8#define tmio_ioread8(addr) readb(addr) 9#define tmio_ioread8(addr) readb(addr)
9#define tmio_ioread16(addr) readw(addr) 10#define tmio_ioread16(addr) readw(addr)
@@ -52,6 +53,21 @@
52 53
53/* tmio MMC platform flags */ 54/* tmio MMC platform flags */
54#define TMIO_MMC_WRPROTECT_DISABLE (1 << 0) 55#define TMIO_MMC_WRPROTECT_DISABLE (1 << 0)
56/*
57 * Some controllers can support a 2-byte block size when the bus width
58 * is configured in 4-bit mode.
59 */
60#define TMIO_MMC_BLKSZ_2BYTES (1 << 1)
61/*
62 * Some controllers can support SDIO IRQ signalling.
63 */
64#define TMIO_MMC_SDIO_IRQ (1 << 2)
65/*
66 * Some platforms can detect card insertion events with controller powered
67 * down, in which case they have to call tmio_mmc_cd_wakeup() to power up the
68 * controller and report the event to the driver.
69 */
70#define TMIO_MMC_HAS_COLD_CD (1 << 3)
55 71
56int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base); 72int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
57int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base); 73int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
@@ -61,6 +77,7 @@ void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state);
61struct tmio_mmc_dma { 77struct tmio_mmc_dma {
62 void *chan_priv_tx; 78 void *chan_priv_tx;
63 void *chan_priv_rx; 79 void *chan_priv_rx;
80 int alignment_shift;
64}; 81};
65 82
66/* 83/*
@@ -72,10 +89,21 @@ struct tmio_mmc_data {
72 unsigned long flags; 89 unsigned long flags;
73 u32 ocr_mask; /* available voltages */ 90 u32 ocr_mask; /* available voltages */
74 struct tmio_mmc_dma *dma; 91 struct tmio_mmc_dma *dma;
92 struct device *dev;
93 bool power;
75 void (*set_pwr)(struct platform_device *host, int state); 94 void (*set_pwr)(struct platform_device *host, int state);
76 void (*set_clk_div)(struct platform_device *host, int state); 95 void (*set_clk_div)(struct platform_device *host, int state);
96 int (*get_cd)(struct platform_device *host);
77}; 97};
78 98
99static inline void tmio_mmc_cd_wakeup(struct tmio_mmc_data *pdata)
100{
101 if (pdata && !pdata->power) {
102 pdata->power = true;
103 pm_runtime_get(pdata->dev);
104 }
105}
106
79/* 107/*
80 * data for the NAND controller 108 * data for the NAND controller
81 */ 109 */