Merge tag 'v3.11-rc7' into devel

Merged in this to avoid conflicts with the big locking fixes
from upstream.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Conflicts:
	drivers/pinctrl/pinctrl-sunxi.c

1 files changed, 92 insertions, 45 deletions

diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
index dab34a1deb2c..b6bdcd66c07d 100644
--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -103,15 +103,15 @@
 #define IMX6Q_GPR1_EXC_MON_MASK                 BIT(22)
 #define IMX6Q_GPR1_EXC_MON_OKAY                 0x0
 #define IMX6Q_GPR1_EXC_MON_SLVE                 BIT(22)
-#define IMX6Q_GPR1_MIPI_IPU2_SEL_MASK           BIT(21)
-#define IMX6Q_GPR1_MIPI_IPU2_SEL_GASKET         0x0
-#define IMX6Q_GPR1_MIPI_IPU2_SEL_IOMUX          BIT(21)
-#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK           BIT(20)
-#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET         0x0
-#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX          BIT(20)
-#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK           BIT(19)
+#define IMX6Q_GPR1_ENET_CLK_SEL_MASK            BIT(21)
+#define IMX6Q_GPR1_ENET_CLK_SEL_PAD             0
+#define IMX6Q_GPR1_ENET_CLK_SEL_ANATOP          BIT(21)
+#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK           BIT(20)
 #define IMX6Q_GPR1_MIPI_IPU2_MUX_GASKET         0x0
-#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX          BIT(19)
+#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX          BIT(20)
+#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK           BIT(19)
+#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET         0x0
+#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX          BIT(19)
 #define IMX6Q_GPR1_PCIE_TEST_PD                 BIT(18)
 #define IMX6Q_GPR1_IPU_VPU_MUX_MASK             BIT(17)
 #define IMX6Q_GPR1_IPU_VPU_MUX_IPU1             0x0
@@ -279,41 +279,88 @@
 #define IMX6Q_GPR13_CAN2_STOP_REQ               BIT(29)
 #define IMX6Q_GPR13_CAN1_STOP_REQ               BIT(28)
 #define IMX6Q_GPR13_ENET_STOP_REQ               BIT(27)
-#define IMX6Q_GPR13_SATA_PHY_8_MASK             (0x7 << 24)
-#define IMX6Q_GPR13_SATA_PHY_8_0_5_DB           (0x0 << 24)
-#define IMX6Q_GPR13_SATA_PHY_8_1_0_DB           (0x1 << 24)
-#define IMX6Q_GPR13_SATA_PHY_8_1_5_DB           (0x2 << 24)
-#define IMX6Q_GPR13_SATA_PHY_8_2_0_DB           (0x3 << 24)
-#define IMX6Q_GPR13_SATA_PHY_8_2_5_DB           (0x4 << 24)
-#define IMX6Q_GPR13_SATA_PHY_8_3_0_DB           (0x5 << 24)
-#define IMX6Q_GPR13_SATA_PHY_8_3_5_DB           (0x6 << 24)
-#define IMX6Q_GPR13_SATA_PHY_8_4_0_DB           (0x7 << 24)
-#define IMX6Q_GPR13_SATA_PHY_7_MASK             (0x1f << 19)
-#define IMX6Q_GPR13_SATA_PHY_7_SATA1I           (0x10 << 19)
-#define IMX6Q_GPR13_SATA_PHY_7_SATA1M           (0x10 << 19)
-#define IMX6Q_GPR13_SATA_PHY_7_SATA1X           (0x1a << 19)
-#define IMX6Q_GPR13_SATA_PHY_7_SATA2I           (0x12 << 19)
-#define IMX6Q_GPR13_SATA_PHY_7_SATA2M           (0x12 << 19)
-#define IMX6Q_GPR13_SATA_PHY_7_SATA2X           (0x1a << 19)
-#define IMX6Q_GPR13_SATA_PHY_6_MASK             (0x7 << 16)
-#define IMX6Q_GPR13_SATA_SPEED_MASK             BIT(15)
-#define IMX6Q_GPR13_SATA_SPEED_1P5G             0x0
-#define IMX6Q_GPR13_SATA_SPEED_3P0G             BIT(15)
-#define IMX6Q_GPR13_SATA_PHY_5                  BIT(14)
-#define IMX6Q_GPR13_SATA_PHY_4_MASK             (0x7 << 11)
-#define IMX6Q_GPR13_SATA_PHY_4_16_16            (0x0 << 11)
-#define IMX6Q_GPR13_SATA_PHY_4_14_16            (0x1 << 11)
-#define IMX6Q_GPR13_SATA_PHY_4_12_16            (0x2 << 11)
-#define IMX6Q_GPR13_SATA_PHY_4_10_16            (0x3 << 11)
-#define IMX6Q_GPR13_SATA_PHY_4_9_16             (0x4 << 11)
-#define IMX6Q_GPR13_SATA_PHY_4_8_16             (0x5 << 11)
-#define IMX6Q_GPR13_SATA_PHY_3_MASK             (0xf << 7)
-#define IMX6Q_GPR13_SATA_PHY_3_OFF              0x7
-#define IMX6Q_GPR13_SATA_PHY_2_MASK             (0x1f << 2)
-#define IMX6Q_GPR13_SATA_PHY_2_OFF              0x2
-#define IMX6Q_GPR13_SATA_PHY_1_MASK             (0x3 << 0)
-#define IMX6Q_GPR13_SATA_PHY_1_FAST             (0x0 << 0)
-#define IMX6Q_GPR13_SATA_PHY_1_MED              (0x1 << 0)
-#define IMX6Q_GPR13_SATA_PHY_1_SLOW             (0x2 << 0)
-
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK         (0x7 << 24)
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB       (0x0 << 24)
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB       (0x1 << 24)
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB       (0x2 << 24)
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB       (0x3 << 24)
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB       (0x4 << 24)
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB       (0x5 << 24)
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB       (0x6 << 24)
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB       (0x7 << 24)
+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK        (0x1f << 19)
+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1I      (0x10 << 19)
+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1M      (0x10 << 19)
+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1X      (0x1a << 19)
+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2I      (0x12 << 19)
+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M      (0x12 << 19)
+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2X      (0x1a << 19)
+#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK      (0x7 << 16)
+#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_1F     (0x0 << 16)
+#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_2F     (0x1 << 16)
+#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_4F     (0x2 << 16)
+#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F     (0x3 << 16)
+#define IMX6Q_GPR13_SATA_SPD_MODE_MASK          BIT(15)
+#define IMX6Q_GPR13_SATA_SPD_MODE_1P5G          0x0
+#define IMX6Q_GPR13_SATA_SPD_MODE_3P0G          BIT(15)
+#define IMX6Q_GPR13_SATA_MPLL_SS_EN             BIT(14)
+#define IMX6Q_GPR13_SATA_TX_ATTEN_MASK          (0x7 << 11)
+#define IMX6Q_GPR13_SATA_TX_ATTEN_16_16         (0x0 << 11)
+#define IMX6Q_GPR13_SATA_TX_ATTEN_14_16         (0x1 << 11)
+#define IMX6Q_GPR13_SATA_TX_ATTEN_12_16         (0x2 << 11)
+#define IMX6Q_GPR13_SATA_TX_ATTEN_10_16         (0x3 << 11)
+#define IMX6Q_GPR13_SATA_TX_ATTEN_9_16          (0x4 << 11)
+#define IMX6Q_GPR13_SATA_TX_ATTEN_8_16          (0x5 << 11)
+#define IMX6Q_GPR13_SATA_TX_BOOST_MASK          (0xf << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_0_00_DB       (0x0 << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_0_37_DB       (0x1 << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB       (0x2 << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB       (0x3 << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_1_48_DB       (0x4 << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_1_85_DB       (0x5 << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_2_22_DB       (0x6 << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_2_59_DB       (0x7 << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_2_96_DB       (0x8 << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB       (0x9 << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_3_70_DB       (0xa << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_4_07_DB       (0xb << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_4_44_DB       (0xc << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_4_81_DB       (0xd << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_5_28_DB       (0xe << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_5_75_DB       (0xf << 7)
+#define IMX6Q_GPR13_SATA_TX_LVL_MASK            (0x1f << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_0_937_V         (0x00 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_0_947_V         (0x01 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_0_957_V         (0x02 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_0_966_V         (0x03 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_0_976_V         (0x04 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_0_986_V         (0x05 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_0_996_V         (0x06 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_005_V         (0x07 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_015_V         (0x08 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_025_V         (0x09 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_035_V         (0x0a << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_045_V         (0x0b << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_054_V         (0x0c << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_064_V         (0x0d << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_074_V         (0x0e << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_084_V         (0x0f << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_094_V         (0x10 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_104_V         (0x11 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_113_V         (0x12 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_123_V         (0x13 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_133_V         (0x14 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_143_V         (0x15 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_152_V         (0x16 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_162_V         (0x17 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_172_V         (0x18 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_182_V         (0x19 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_191_V         (0x1a << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_201_V         (0x1b << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_211_V         (0x1c << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_221_V         (0x1d << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_230_V         (0x1e << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_240_V         (0x1f << 2)
+#define IMX6Q_GPR13_SATA_MPLL_CLK_EN            BIT(1)
+#define IMX6Q_GPR13_SATA_TX_EDGE_RATE           BIT(0)
 #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */