mfd: Unify abx500 headers in mfd/abx500

This moves all the header files related to the abx500 family into
a common include directory below mfd. From now on we place any
subchip header in that directory. Headers previously in e.g.
<linux/mfd/ab8500/gpio.h> get prefixed and are now e.g.
<linux/mfd/abx500/ab8500-gpio.h>. The top-level abstract interface
remains in <linux/mfd/abx500.h>.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>

5 files changed, 651 insertions, 0 deletions

diff --git a/include/linux/mfd/abx500/ab5500.h b/include/linux/mfd/abx500/ab5500.h
new file mode 100644
index 000000000000..a720051ae933
--- /dev/null
+++ b/include/linux/mfd/abx500/ab5500.h
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) ST-Ericsson 2011
+ *
+ * License Terms: GNU General Public License v2
+ */
+#ifndef MFD_AB5500_H
+#define MFD_AB5500_H
+
+#include <linux/device.h>
+
+enum ab5500_devid {
+        AB5500_DEVID_ADC,
+        AB5500_DEVID_LEDS,
+        AB5500_DEVID_POWER,
+        AB5500_DEVID_REGULATORS,
+        AB5500_DEVID_SIM,
+        AB5500_DEVID_RTC,
+        AB5500_DEVID_CHARGER,
+        AB5500_DEVID_FUELGAUGE,
+        AB5500_DEVID_VIBRATOR,
+        AB5500_DEVID_CODEC,
+        AB5500_DEVID_USB,
+        AB5500_DEVID_OTP,
+        AB5500_DEVID_VIDEO,
+        AB5500_DEVID_DBIECI,
+        AB5500_DEVID_ONSWA,
+        AB5500_NUM_DEVICES,
+};
+
+enum ab5500_banks {
+        AB5500_BANK_VIT_IO_I2C_CLK_TST_OTP = 0,
+        AB5500_BANK_VDDDIG_IO_I2C_CLK_TST = 1,
+        AB5500_BANK_VDENC = 2,
+        AB5500_BANK_SIM_USBSIM  = 3,
+        AB5500_BANK_LED = 4,
+        AB5500_BANK_ADC  = 5,
+        AB5500_BANK_RTC  = 6,
+        AB5500_BANK_STARTUP  = 7,
+        AB5500_BANK_DBI_ECI  = 8,
+        AB5500_BANK_CHG  = 9,
+        AB5500_BANK_FG_BATTCOM_ACC = 10,
+        AB5500_BANK_USB = 11,
+        AB5500_BANK_IT = 12,
+        AB5500_BANK_VIBRA = 13,
+        AB5500_BANK_AUDIO_HEADSETUSB = 14,
+        AB5500_NUM_BANKS = 15,
+};
+
+enum ab5500_banks_addr {
+        AB5500_ADDR_VIT_IO_I2C_CLK_TST_OTP = 0x4A,
+        AB5500_ADDR_VDDDIG_IO_I2C_CLK_TST = 0x4B,
+        AB5500_ADDR_VDENC = 0x06,
+        AB5500_ADDR_SIM_USBSIM  = 0x04,
+        AB5500_ADDR_LED = 0x10,
+        AB5500_ADDR_ADC  = 0x0A,
+        AB5500_ADDR_RTC  = 0x0F,
+        AB5500_ADDR_STARTUP  = 0x03,
+        AB5500_ADDR_DBI_ECI  = 0x07,
+        AB5500_ADDR_CHG  = 0x0B,
+        AB5500_ADDR_FG_BATTCOM_ACC = 0x0C,
+        AB5500_ADDR_USB = 0x05,
+        AB5500_ADDR_IT = 0x0E,
+        AB5500_ADDR_VIBRA = 0x02,
+        AB5500_ADDR_AUDIO_HEADSETUSB = 0x0D,
+};
+
+/*
+ * Interrupt register offsets
+ * Bank : 0x0E
+ */
+#define AB5500_IT_SOURCE0_REG           0x20
+#define AB5500_IT_SOURCE1_REG           0x21
+#define AB5500_IT_SOURCE2_REG           0x22
+#define AB5500_IT_SOURCE3_REG           0x23
+#define AB5500_IT_SOURCE4_REG           0x24
+#define AB5500_IT_SOURCE5_REG           0x25
+#define AB5500_IT_SOURCE6_REG           0x26
+#define AB5500_IT_SOURCE7_REG           0x27
+#define AB5500_IT_SOURCE8_REG           0x28
+#define AB5500_IT_SOURCE9_REG           0x29
+#define AB5500_IT_SOURCE10_REG          0x2A
+#define AB5500_IT_SOURCE11_REG          0x2B
+#define AB5500_IT_SOURCE12_REG          0x2C
+#define AB5500_IT_SOURCE13_REG          0x2D
+#define AB5500_IT_SOURCE14_REG          0x2E
+#define AB5500_IT_SOURCE15_REG          0x2F
+#define AB5500_IT_SOURCE16_REG          0x30
+#define AB5500_IT_SOURCE17_REG          0x31
+#define AB5500_IT_SOURCE18_REG          0x32
+#define AB5500_IT_SOURCE19_REG          0x33
+#define AB5500_IT_SOURCE20_REG          0x34
+#define AB5500_IT_SOURCE21_REG          0x35
+#define AB5500_IT_SOURCE22_REG          0x36
+#define AB5500_IT_SOURCE23_REG          0x37
+
+#define AB5500_NUM_IRQ_REGS             23
+
+/**
+ * struct ab5500
+ * @access_mutex: lock out concurrent accesses to the AB registers
+ * @dev: a pointer to the device struct for this chip driver
+ * @ab5500_irq: the analog baseband irq
+ * @irq_base: the platform configuration irq base for subdevices
+ * @chip_name: name of this chip variant
+ * @chip_id: 8 bit chip ID for this chip variant
+ * @irq_lock: a lock to protect the mask
+ * @abb_events: a local bit mask of the prcmu wakeup events
+ * @event_mask: a local copy of the mask event registers
+ * @last_event_mask: a copy of the last event_mask written to hardware
+ * @startup_events: a copy of the first reading of the event registers
+ * @startup_events_read: whether the first events have been read
+ */
+struct ab5500 {
+        struct mutex access_mutex;
+        struct device *dev;
+        unsigned int ab5500_irq;
+        unsigned int irq_base;
+        char chip_name[32];
+        u8 chip_id;
+        struct mutex irq_lock;
+        u32 abb_events;
+        u8 mask[AB5500_NUM_IRQ_REGS];
+        u8 oldmask[AB5500_NUM_IRQ_REGS];
+        u8 startup_events[AB5500_NUM_IRQ_REGS];
+        bool startup_events_read;
+#ifdef CONFIG_DEBUG_FS
+        unsigned int debug_bank;
+        unsigned int debug_address;
+#endif
+};
+
+struct ab5500_platform_data {
+        struct {unsigned int base; unsigned int count; } irq;
+        void *dev_data[AB5500_NUM_DEVICES];
+        struct abx500_init_settings *init_settings;
+        unsigned int init_settings_sz;
+        bool pm_power_off;
+};
+
+#endif /* MFD_AB5500_H */
diff --git a/include/linux/mfd/abx500/ab8500-gpadc.h b/include/linux/mfd/abx500/ab8500-gpadc.h
new file mode 100644
index 000000000000..252966769d93
--- /dev/null
+++ b/include/linux/mfd/abx500/ab8500-gpadc.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2010 ST-Ericsson SA
+ * Licensed under GPLv2.
+ *
+ * Author: Arun R Murthy <arun.murthy@stericsson.com>
+ * Author: Daniel Willerud <daniel.willerud@stericsson.com>
+ */
+
+#ifndef _AB8500_GPADC_H
+#define _AB8500_GPADC_H
+
+/* GPADC source: From datasheet(ADCSwSel[4:0] in GPADCCtrl2) */
+#define BAT_CTRL        0x01
+#define BTEMP_BALL      0x02
+#define MAIN_CHARGER_V  0x03
+#define ACC_DETECT1     0x04
+#define ACC_DETECT2     0x05
+#define ADC_AUX1        0x06
+#define ADC_AUX2        0x07
+#define MAIN_BAT_V      0x08
+#define VBUS_V          0x09
+#define MAIN_CHARGER_C  0x0A
+#define USB_CHARGER_C   0x0B
+#define BK_BAT_V        0x0C
+#define DIE_TEMP        0x0D
+
+struct ab8500_gpadc;
+
+struct ab8500_gpadc *ab8500_gpadc_get(char *name);
+int ab8500_gpadc_convert(struct ab8500_gpadc *gpadc, u8 channel);
+int ab8500_gpadc_read_raw(struct ab8500_gpadc *gpadc, u8 channel);
+int ab8500_gpadc_ad_to_voltage(struct ab8500_gpadc *gpadc,
+    u8 channel, int ad_value);
+
+#endif /* _AB8500_GPADC_H */
diff --git a/include/linux/mfd/abx500/ab8500-gpio.h b/include/linux/mfd/abx500/ab8500-gpio.h
new file mode 100644
index 000000000000..488a8c920a29
--- /dev/null
+++ b/include/linux/mfd/abx500/ab8500-gpio.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright ST-Ericsson 2010.
+ *
+ * Author: Bibek Basu <bibek.basu@stericsson.com>
+ * Licensed under GPLv2.
+ */
+
+#ifndef _AB8500_GPIO_H
+#define _AB8500_GPIO_H
+
+/*
+ * Platform data to register a block: only the initial gpio/irq number.
+ */
+
+struct ab8500_gpio_platform_data {
+        int gpio_base;
+        u32 irq_base;
+        u8  config_reg[7];
+};
+
+#endif /* _AB8500_GPIO_H */
diff --git a/include/linux/mfd/abx500/ab8500-sysctrl.h b/include/linux/mfd/abx500/ab8500-sysctrl.h
new file mode 100644
index 000000000000..10da0291f8f8
--- /dev/null
+++ b/include/linux/mfd/abx500/ab8500-sysctrl.h
@@ -0,0 +1,254 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> for ST Ericsson.
+ * License terms: GNU General Public License (GPL) version 2
+ */
+#ifndef __AB8500_SYSCTRL_H
+#define __AB8500_SYSCTRL_H
+
+#include <linux/bitops.h>
+
+#ifdef CONFIG_AB8500_CORE
+
+int ab8500_sysctrl_read(u16 reg, u8 *value);
+int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value);
+
+#else
+
+static inline int ab8500_sysctrl_read(u16 reg, u8 *value)
+{
+        return 0;
+}
+
+static inline int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value)
+{
+        return 0;
+}
+
+#endif /* CONFIG_AB8500_CORE */
+
+static inline int ab8500_sysctrl_set(u16 reg, u8 bits)
+{
+        return ab8500_sysctrl_write(reg, bits, bits);
+}
+
+static inline int ab8500_sysctrl_clear(u16 reg, u8 bits)
+{
+        return ab8500_sysctrl_write(reg, bits, 0);
+}
+
+/* Registers */
+#define AB8500_TURNONSTATUS             0x100
+#define AB8500_RESETSTATUS              0x101
+#define AB8500_PONKEY1PRESSSTATUS       0x102
+#define AB8500_SYSCLKREQSTATUS          0x142
+#define AB8500_STW4500CTRL1             0x180
+#define AB8500_STW4500CTRL2             0x181
+#define AB8500_STW4500CTRL3             0x200
+#define AB8500_MAINWDOGCTRL             0x201
+#define AB8500_MAINWDOGTIMER            0x202
+#define AB8500_LOWBAT                   0x203
+#define AB8500_BATTOK                   0x204
+#define AB8500_SYSCLKTIMER              0x205
+#define AB8500_SMPSCLKCTRL              0x206
+#define AB8500_SMPSCLKSEL1              0x207
+#define AB8500_SMPSCLKSEL2              0x208
+#define AB8500_SMPSCLKSEL3              0x209
+#define AB8500_SYSULPCLKCONF            0x20A
+#define AB8500_SYSULPCLKCTRL1           0x20B
+#define AB8500_SYSCLKCTRL               0x20C
+#define AB8500_SYSCLKREQ1VALID          0x20D
+#define AB8500_SYSTEMCTRLSUP            0x20F
+#define AB8500_SYSCLKREQ1RFCLKBUF       0x210
+#define AB8500_SYSCLKREQ2RFCLKBUF       0x211
+#define AB8500_SYSCLKREQ3RFCLKBUF       0x212
+#define AB8500_SYSCLKREQ4RFCLKBUF       0x213
+#define AB8500_SYSCLKREQ5RFCLKBUF       0x214
+#define AB8500_SYSCLKREQ6RFCLKBUF       0x215
+#define AB8500_SYSCLKREQ7RFCLKBUF       0x216
+#define AB8500_SYSCLKREQ8RFCLKBUF       0x217
+#define AB8500_DITHERCLKCTRL            0x220
+#define AB8500_SWATCTRL                 0x230
+#define AB8500_HIQCLKCTRL               0x232
+#define AB8500_VSIMSYSCLKCTRL           0x233
+
+/* Bits */
+#define AB8500_TURNONSTATUS_PORNVBAT BIT(0)
+#define AB8500_TURNONSTATUS_PONKEY1DBF BIT(1)
+#define AB8500_TURNONSTATUS_PONKEY2DBF BIT(2)
+#define AB8500_TURNONSTATUS_RTCALARM BIT(3)
+#define AB8500_TURNONSTATUS_MAINCHDET BIT(4)
+#define AB8500_TURNONSTATUS_VBUSDET BIT(5)
+#define AB8500_TURNONSTATUS_USBIDDETECT BIT(6)
+
+#define AB8500_RESETSTATUS_RESETN4500NSTATUS BIT(0)
+#define AB8500_RESETSTATUS_SWRESETN4500NSTATUS BIT(2)
+
+#define AB8500_PONKEY1PRESSSTATUS_PONKEY1PRESSTIME_MASK 0x7F
+#define AB8500_PONKEY1PRESSSTATUS_PONKEY1PRESSTIME_SHIFT 0
+
+#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ1STATUS BIT(0)
+#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ2STATUS BIT(1)
+#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ3STATUS BIT(2)
+#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ4STATUS BIT(3)
+#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ5STATUS BIT(4)
+#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ6STATUS BIT(5)
+#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ7STATUS BIT(6)
+#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ8STATUS BIT(7)
+
+#define AB8500_STW4500CTRL1_SWOFF BIT(0)
+#define AB8500_STW4500CTRL1_SWRESET4500N BIT(1)
+#define AB8500_STW4500CTRL1_THDB8500SWOFF BIT(2)
+
+#define AB8500_STW4500CTRL2_RESETNVAUX1VALID BIT(0)
+#define AB8500_STW4500CTRL2_RESETNVAUX2VALID BIT(1)
+#define AB8500_STW4500CTRL2_RESETNVAUX3VALID BIT(2)
+#define AB8500_STW4500CTRL2_RESETNVMODVALID BIT(3)
+#define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY1VALID BIT(4)
+#define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY2VALID BIT(5)
+#define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY3VALID BIT(6)
+#define AB8500_STW4500CTRL2_RESETNVSMPS1VALID BIT(7)
+
+#define AB8500_STW4500CTRL3_CLK32KOUT2DIS BIT(0)
+#define AB8500_STW4500CTRL3_RESETAUDN BIT(1)
+#define AB8500_STW4500CTRL3_RESETDENCN BIT(2)
+#define AB8500_STW4500CTRL3_THSDENA BIT(3)
+
+#define AB8500_MAINWDOGCTRL_MAINWDOGENA BIT(0)
+#define AB8500_MAINWDOGCTRL_MAINWDOGKICK BIT(1)
+#define AB8500_MAINWDOGCTRL_WDEXPTURNONVALID BIT(4)
+
+#define AB8500_MAINWDOGTIMER_MAINWDOGTIMER_MASK 0x7F
+#define AB8500_MAINWDOGTIMER_MAINWDOGTIMER_SHIFT 0
+
+#define AB8500_LOWBAT_LOWBATENA BIT(0)
+#define AB8500_LOWBAT_LOWBAT_MASK 0x7E
+#define AB8500_LOWBAT_LOWBAT_SHIFT 1
+
+#define AB8500_BATTOK_BATTOKSEL0THF_MASK 0x0F
+#define AB8500_BATTOK_BATTOKSEL0THF_SHIFT 0
+#define AB8500_BATTOK_BATTOKSEL1THF_MASK 0xF0
+#define AB8500_BATTOK_BATTOKSEL1THF_SHIFT 4
+
+#define AB8500_SYSCLKTIMER_SYSCLKTIMER_MASK 0x0F
+#define AB8500_SYSCLKTIMER_SYSCLKTIMER_SHIFT 0
+#define AB8500_SYSCLKTIMER_SYSCLKTIMERADJ_MASK 0xF0
+#define AB8500_SYSCLKTIMER_SYSCLKTIMERADJ_SHIFT 4
+
+#define AB8500_SMPSCLKCTRL_SMPSCLKINTSEL_MASK 0x03
+#define AB8500_SMPSCLKCTRL_SMPSCLKINTSEL_SHIFT 0
+#define AB8500_SMPSCLKCTRL_3M2CLKINTENA BIT(2)
+
+#define AB8500_SMPSCLKSEL1_VARMCLKSEL_MASK 0x07
+#define AB8500_SMPSCLKSEL1_VARMCLKSEL_SHIFT 0
+#define AB8500_SMPSCLKSEL1_VAPECLKSEL_MASK 0x38
+#define AB8500_SMPSCLKSEL1_VAPECLKSEL_SHIFT 3
+
+#define AB8500_SMPSCLKSEL2_VMODCLKSEL_MASK 0x07
+#define AB8500_SMPSCLKSEL2_VMODCLKSEL_SHIFT 0
+#define AB8500_SMPSCLKSEL2_VSMPS1CLKSEL_MASK 0x38
+#define AB8500_SMPSCLKSEL2_VSMPS1CLKSEL_SHIFT 3
+
+#define AB8500_SMPSCLKSEL3_VSMPS2CLKSEL_MASK 0x07
+#define AB8500_SMPSCLKSEL3_VSMPS2CLKSEL_SHIFT 0
+#define AB8500_SMPSCLKSEL3_VSMPS3CLKSEL_MASK 0x38
+#define AB8500_SMPSCLKSEL3_VSMPS3CLKSEL_SHIFT 3
+
+#define AB8500_SYSULPCLKCONF_ULPCLKCONF_MASK 0x03
+#define AB8500_SYSULPCLKCONF_ULPCLKCONF_SHIFT 0
+#define AB8500_SYSULPCLKCONF_CLK27MHZSTRE BIT(2)
+#define AB8500_SYSULPCLKCONF_TVOUTCLKDELN BIT(3)
+#define AB8500_SYSULPCLKCONF_TVOUTCLKINV BIT(4)
+#define AB8500_SYSULPCLKCONF_ULPCLKSTRE BIT(5)
+#define AB8500_SYSULPCLKCONF_CLK27MHZBUFENA BIT(6)
+#define AB8500_SYSULPCLKCONF_CLK27MHZPDENA BIT(7)
+
+#define AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_MASK 0x03
+#define AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_SHIFT 0
+#define AB8500_SYSULPCLKCTRL1_ULPCLKREQ BIT(2)
+#define AB8500_SYSULPCLKCTRL1_4500SYSCLKREQ BIT(3)
+#define AB8500_SYSULPCLKCTRL1_AUDIOCLKENA BIT(4)
+#define AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ BIT(5)
+#define AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ BIT(6)
+#define AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ BIT(7)
+
+#define AB8500_SYSCLKCTRL_TVOUTPLLENA BIT(0)
+#define AB8500_SYSCLKCTRL_TVOUTCLKENA BIT(1)
+#define AB8500_SYSCLKCTRL_USBCLKENA BIT(2)
+
+#define AB8500_SYSCLKREQ1VALID_SYSCLKREQ1VALID BIT(0)
+#define AB8500_SYSCLKREQ1VALID_ULPCLKREQ1VALID BIT(1)
+#define AB8500_SYSCLKREQ1VALID_USBSYSCLKREQ1VALID BIT(2)
+
+#define AB8500_SYSTEMCTRLSUP_EXTSUP12LPNCLKSEL_MASK 0x03
+#define AB8500_SYSTEMCTRLSUP_EXTSUP12LPNCLKSEL_SHIFT 0
+#define AB8500_SYSTEMCTRLSUP_EXTSUP3LPNCLKSEL_MASK 0x0C
+#define AB8500_SYSTEMCTRLSUP_EXTSUP3LPNCLKSEL_SHIFT 2
+#define AB8500_SYSTEMCTRLSUP_INTDB8500NOD BIT(4)
+
+#define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF2 BIT(2)
+#define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF3 BIT(3)
+#define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF4 BIT(4)
+
+#define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF2 BIT(2)
+#define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF3 BIT(3)
+#define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF4 BIT(4)
+
+#define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF2 BIT(2)
+#define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF3 BIT(3)
+#define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF4 BIT(4)
+
+#define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF2 BIT(2)
+#define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF3 BIT(3)
+#define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF4 BIT(4)
+
+#define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF2 BIT(2)
+#define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF3 BIT(3)
+#define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF4 BIT(4)
+
+#define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF2 BIT(2)
+#define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF3 BIT(3)
+#define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF4 BIT(4)
+
+#define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF2 BIT(2)
+#define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF3 BIT(3)
+#define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF4 BIT(4)
+
+#define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF2 BIT(2)
+#define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF3 BIT(3)
+#define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF4 BIT(4)
+
+#define AB8500_DITHERCLKCTRL_VARMDITHERENA BIT(0)
+#define AB8500_DITHERCLKCTRL_VSMPS3DITHERENA BIT(1)
+#define AB8500_DITHERCLKCTRL_VSMPS1DITHERENA BIT(2)
+#define AB8500_DITHERCLKCTRL_VSMPS2DITHERENA BIT(3)
+#define AB8500_DITHERCLKCTRL_VMODDITHERENA BIT(4)
+#define AB8500_DITHERCLKCTRL_VAPEDITHERENA BIT(5)
+#define AB8500_DITHERCLKCTRL_DITHERDEL_MASK 0xC0
+#define AB8500_DITHERCLKCTRL_DITHERDEL_SHIFT 6
+
+#define AB8500_SWATCTRL_UPDATERF BIT(0)
+#define AB8500_SWATCTRL_SWATENABLE BIT(1)
+#define AB8500_SWATCTRL_RFOFFTIMER_MASK 0x1C
+#define AB8500_SWATCTRL_RFOFFTIMER_SHIFT 2
+#define AB8500_SWATCTRL_SWATBIT5 BIT(6)
+
+#define AB8500_HIQCLKCTRL_SYSCLKREQ1HIQENAVALID BIT(0)
+#define AB8500_HIQCLKCTRL_SYSCLKREQ2HIQENAVALID BIT(1)
+#define AB8500_HIQCLKCTRL_SYSCLKREQ3HIQENAVALID BIT(2)
+#define AB8500_HIQCLKCTRL_SYSCLKREQ4HIQENAVALID BIT(3)
+#define AB8500_HIQCLKCTRL_SYSCLKREQ5HIQENAVALID BIT(4)
+#define AB8500_HIQCLKCTRL_SYSCLKREQ6HIQENAVALID BIT(5)
+#define AB8500_HIQCLKCTRL_SYSCLKREQ7HIQENAVALID BIT(6)
+#define AB8500_HIQCLKCTRL_SYSCLKREQ8HIQENAVALID BIT(7)
+
+#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ1VALID BIT(0)
+#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ2VALID BIT(1)
+#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ3VALID BIT(2)
+#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ4VALID BIT(3)
+#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ5VALID BIT(4)
+#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ6VALID BIT(5)
+#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ7VALID BIT(6)
+#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ8VALID BIT(7)
+
+#endif /* __AB8500_SYSCTRL_H */
diff --git a/include/linux/mfd/abx500/ab8500.h b/include/linux/mfd/abx500/ab8500.h
new file mode 100644
index 000000000000..838c6b487cc5
--- /dev/null
+++ b/include/linux/mfd/abx500/ab8500.h
@@ -0,0 +1,201 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License v2
+ * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
+ */
+#ifndef MFD_AB8500_H
+#define MFD_AB8500_H
+
+#include <linux/device.h>
+
+/*
+ * AB8500 bank addresses
+ */
+#define AB8500_SYS_CTRL1_BLOCK  0x1
+#define AB8500_SYS_CTRL2_BLOCK  0x2
+#define AB8500_REGU_CTRL1       0x3
+#define AB8500_REGU_CTRL2       0x4
+#define AB8500_USB              0x5
+#define AB8500_TVOUT            0x6
+#define AB8500_DBI              0x7
+#define AB8500_ECI_AV_ACC       0x8
+#define AB8500_RESERVED         0x9
+#define AB8500_GPADC            0xA
+#define AB8500_CHARGER          0xB
+#define AB8500_GAS_GAUGE        0xC
+#define AB8500_AUDIO            0xD
+#define AB8500_INTERRUPT        0xE
+#define AB8500_RTC              0xF
+#define AB8500_MISC             0x10
+#define AB8500_DEVELOPMENT      0x11
+#define AB8500_DEBUG            0x12
+#define AB8500_PROD_TEST        0x13
+#define AB8500_OTP_EMUL         0x15
+
+/*
+ * Interrupts
+ */
+
+#define AB8500_INT_MAIN_EXT_CH_NOT_OK   0
+#define AB8500_INT_UN_PLUG_TV_DET       1
+#define AB8500_INT_PLUG_TV_DET          2
+#define AB8500_INT_TEMP_WARM            3
+#define AB8500_INT_PON_KEY2DB_F         4
+#define AB8500_INT_PON_KEY2DB_R         5
+#define AB8500_INT_PON_KEY1DB_F         6
+#define AB8500_INT_PON_KEY1DB_R         7
+#define AB8500_INT_BATT_OVV             8
+#define AB8500_INT_MAIN_CH_UNPLUG_DET   10
+#define AB8500_INT_MAIN_CH_PLUG_DET     11
+#define AB8500_INT_USB_ID_DET_F         12
+#define AB8500_INT_USB_ID_DET_R         13
+#define AB8500_INT_VBUS_DET_F           14
+#define AB8500_INT_VBUS_DET_R           15
+#define AB8500_INT_VBUS_CH_DROP_END     16
+#define AB8500_INT_RTC_60S              17
+#define AB8500_INT_RTC_ALARM            18
+#define AB8500_INT_BAT_CTRL_INDB        20
+#define AB8500_INT_CH_WD_EXP            21
+#define AB8500_INT_VBUS_OVV             22
+#define AB8500_INT_MAIN_CH_DROP_END     23
+#define AB8500_INT_CCN_CONV_ACC         24
+#define AB8500_INT_INT_AUD              25
+#define AB8500_INT_CCEOC                26
+#define AB8500_INT_CC_INT_CALIB         27
+#define AB8500_INT_LOW_BAT_F            28
+#define AB8500_INT_LOW_BAT_R            29
+#define AB8500_INT_BUP_CHG_NOT_OK       30
+#define AB8500_INT_BUP_CHG_OK           31
+#define AB8500_INT_GP_HW_ADC_CONV_END   32
+#define AB8500_INT_ACC_DETECT_1DB_F     33
+#define AB8500_INT_ACC_DETECT_1DB_R     34
+#define AB8500_INT_ACC_DETECT_22DB_F    35
+#define AB8500_INT_ACC_DETECT_22DB_R    36
+#define AB8500_INT_ACC_DETECT_21DB_F    37
+#define AB8500_INT_ACC_DETECT_21DB_R    38
+#define AB8500_INT_GP_SW_ADC_CONV_END   39
+#define AB8500_INT_GPIO6R               40
+#define AB8500_INT_GPIO7R               41
+#define AB8500_INT_GPIO8R               42
+#define AB8500_INT_GPIO9R               43
+#define AB8500_INT_GPIO10R              44
+#define AB8500_INT_GPIO11R              45
+#define AB8500_INT_GPIO12R              46
+#define AB8500_INT_GPIO13R              47
+#define AB8500_INT_GPIO24R              48
+#define AB8500_INT_GPIO25R              49
+#define AB8500_INT_GPIO36R              50
+#define AB8500_INT_GPIO37R              51
+#define AB8500_INT_GPIO38R              52
+#define AB8500_INT_GPIO39R              53
+#define AB8500_INT_GPIO40R              54
+#define AB8500_INT_GPIO41R              55
+#define AB8500_INT_GPIO6F               56
+#define AB8500_INT_GPIO7F               57
+#define AB8500_INT_GPIO8F               58
+#define AB8500_INT_GPIO9F               59
+#define AB8500_INT_GPIO10F              60
+#define AB8500_INT_GPIO11F              61
+#define AB8500_INT_GPIO12F              62
+#define AB8500_INT_GPIO13F              63
+#define AB8500_INT_GPIO24F              64
+#define AB8500_INT_GPIO25F              65
+#define AB8500_INT_GPIO36F              66
+#define AB8500_INT_GPIO37F              67
+#define AB8500_INT_GPIO38F              68
+#define AB8500_INT_GPIO39F              69
+#define AB8500_INT_GPIO40F              70
+#define AB8500_INT_GPIO41F              71
+#define AB8500_INT_ADP_SOURCE_ERROR     72
+#define AB8500_INT_ADP_SINK_ERROR       73
+#define AB8500_INT_ADP_PROBE_PLUG       74
+#define AB8500_INT_ADP_PROBE_UNPLUG     75
+#define AB8500_INT_ADP_SENSE_OFF        76
+#define AB8500_INT_USB_PHY_POWER_ERR    78
+#define AB8500_INT_USB_LINK_STATUS      79
+#define AB8500_INT_BTEMP_LOW            80
+#define AB8500_INT_BTEMP_LOW_MEDIUM     81
+#define AB8500_INT_BTEMP_MEDIUM_HIGH    82
+#define AB8500_INT_BTEMP_HIGH           83
+#define AB8500_INT_USB_CHARGER_NOT_OK   89
+#define AB8500_INT_ID_WAKEUP_R          90
+#define AB8500_INT_ID_DET_R1R           92
+#define AB8500_INT_ID_DET_R2R           93
+#define AB8500_INT_ID_DET_R3R           94
+#define AB8500_INT_ID_DET_R4R           95
+#define AB8500_INT_ID_WAKEUP_F          96
+#define AB8500_INT_ID_DET_R1F           98
+#define AB8500_INT_ID_DET_R2F           99
+#define AB8500_INT_ID_DET_R3F           100
+#define AB8500_INT_ID_DET_R4F           101
+#define AB8500_INT_USB_CHG_DET_DONE     102
+#define AB8500_INT_USB_CH_TH_PROT_F     104
+#define AB8500_INT_USB_CH_TH_PROT_R    105
+#define AB8500_INT_MAIN_CH_TH_PROT_F   106
+#define AB8500_INT_MAIN_CH_TH_PROT_R    107
+#define AB8500_INT_USB_CHARGER_NOT_OKF  111
+
+#define AB8500_NR_IRQS                  112
+#define AB8500_NUM_IRQ_REGS             14
+
+/**
+ * struct ab8500 - ab8500 internal structure
+ * @dev: parent device
+ * @lock: read/write operations lock
+ * @irq_lock: genirq bus lock
+ * @irq: irq line
+ * @chip_id: chip revision id
+ * @write: register write
+ * @read: register read
+ * @rx_buf: rx buf for SPI
+ * @tx_buf: tx buf for SPI
+ * @mask: cache of IRQ regs for bus lock
+ * @oldmask: cache of previous IRQ regs for bus lock
+ */
+struct ab8500 {
+        struct device   *dev;
+        struct mutex    lock;
+        struct mutex    irq_lock;
+
+        int             irq_base;
+        int             irq;
+        u8              chip_id;
+
+        int (*write) (struct ab8500 *a8500, u16 addr, u8 data);
+        int (*read) (struct ab8500 *a8500, u16 addr);
+
+        unsigned long   tx_buf[4];
+        unsigned long   rx_buf[4];
+
+        u8 mask[AB8500_NUM_IRQ_REGS];
+        u8 oldmask[AB8500_NUM_IRQ_REGS];
+};
+
+struct regulator_reg_init;
+struct regulator_init_data;
+struct ab8500_gpio_platform_data;
+
+/**
+ * struct ab8500_platform_data - AB8500 platform data
+ * @irq_base: start of AB8500 IRQs, AB8500_NR_IRQS will be used
+ * @init: board-specific initialization after detection of ab8500
+ * @num_regulator_reg_init: number of regulator init registers
+ * @regulator_reg_init: regulator init registers
+ * @num_regulator: number of regulators
+ * @regulator: machine-specific constraints for regulators
+ */
+struct ab8500_platform_data {
+        int irq_base;
+        void (*init) (struct ab8500 *);
+        int num_regulator_reg_init;
+        struct ab8500_regulator_reg_init *regulator_reg_init;
+        int num_regulator;
+        struct regulator_init_data *regulator;
+        struct ab8500_gpio_platform_data *gpio;
+};
+
+extern int __devinit ab8500_init(struct ab8500 *ab8500);
+extern int __devexit ab8500_exit(struct ab8500 *ab8500);
+
+#endif /* MFD_AB8500_H */