litmus-rt.git - The LITMUS^RT kernel.

The LITMUS^RT kernel.

Bjoern Brandenburg

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author	Hillf Danton <dhillf@gmail.com>	2011-08-04 10:38:31 -0400
committer	Ralf Baechle <ralf@linux-mips.org>	2011-09-16 20:37:03 -0400
commit	9fbcbd7e1fa9acde67f3516f7aceef2c0d968a7b (patch)
tree	6ce4f2899656a29cf8b7a7420cd44ddf9021c6a3 /include/linux/libps2.h
parent	ddf28352b80c86754a6424e3a61e8bdf9213b3c7 (diff)

MIPS: VPE: Select correct tc

If we could find tc on the tc list for @index, the found tc should be returned. Signed-off-by: Hillf Danton <dhillf@gmail.com> To: LKML <linux-kernel@vger.kernel.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2692/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Diffstat (limited to 'include/linux/libps2.h')

0 files changed, 0 insertions, 0 deletions

rface port */ #define W_PAR0 0xaa /* write physical address register 0 */ #define W_PAR1 0xab /* write physical address register 1 */ #define W_PAR2 0xac /* write physical address register 2 */ #define W_PAR3 0xad /* write physical address register 3 */ #define W_PAR4 0xae /* write physical address register 4 */ #define W_PAR5 0xaf /* write physical address register 5 */ /* IDC 2 Command */ #define R_STS 0xc0 /* read status register */ #define R_CPR 0xc1 /* read current page register */ #define R_BPR 0xc2 /* read boundary page register */ #define R_TDR 0xc3 /* read time domain reflectometry reg */ /* STATUS Register */ #define EEDI 0x80 /* EEPM DO pin */ #define TXSUC 0x40 /* tx success */ #define T16 0x20 /* tx fail 16 times */ #define TS1 0x40 /* 0=Tx success, 1=T16 */ #define TS0 0x20 /* 0=Tx success, 1=T16 */ #define RXGOOD 0x10 /* rx a good packet */ #define RXCRC 0x08 /* rx a CRC error packet */ #define RXSHORT 0x04 /* rx a short packet */ #define COLS 0x02 /* coaxial collision status */ #define LNKS 0x01 /* UTP link status */ /* Command Register */ #define CLEAR 0x10 /* reset part of hardware */ #define NOPER 0x08 /* No Operation */ #define RNOP 0x08 #define RRA 0x06 /* After RR then auto-advance NPR & BPR(=NPR-1) */ #define RRN 0x04 /* Normal Remote Read mode */ #define RW1 0x02 /* Remote Write tx buffer 1 ( page 6 - 11 ) */ #define RW0 0x00 /* Remote Write tx buffer 0 ( page 0 - 5 ) */ #define TXEN 0x01 /* 0->1 tx enable */ /* System Configuration Register */ #define TESTON 0x80 /* test host data transfer reliability */ #define SLEEP 0x40 /* sleep mode */ #if 0 #define FASTMODE 0x04 /* fast mode for intel 82360SL fast mode */ #define BYTEMODE 0x02 /* byte mode */ #else #define FASTMODE 0x20 /* fast mode for intel 82360SL fast mode */ #define BYTEMODE 0x10 /* byte mode */ #endif #define NIBBLEMODE 0x00 /* nibble mode */ #define IRQINV 0x08 /* turn off IRQ line inverter */ #define IRQNML 0x00 /* turn on IRQ line inverter */ #define INTON 0x04 #define AUTOFFSET 0x02 /* auto shift address to TPR+12 */ #define AUTOTX 0x01 /* auto tx when leave RW mode */ /* Transceiver Configuration Register */ #define JABBER 0x80 /* generate jabber condition */ #define TXSUCINT 0x40 /* enable tx success interrupt */ #define T16INT 0x20 /* enable T16 interrupt */ #define RXERRPKT 0x10 /* accept CRC error or short packet */ #define EXTERNALB2 0x0C /* external loopback 2 */ #define EXTERNALB1 0x08 /* external loopback 1 */ #define INTERNALB 0x04 /* internal loopback */ #define NMLOPERATE 0x00 /* normal operation */ #define RXPBM 0x03 /* rx physical, broadcast, multicast */ #define RXPB 0x02 /* rx physical, broadcast */ #define RXALL 0x01 /* rx all packet */ #define RXOFF 0x00 /* rx disable */


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