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authorHe, Qing <qing.he@intel.com>2007-07-26 04:05:18 -0400
committerAvi Kivity <avi@qumranet.com>2007-10-13 04:18:25 -0400
commit6ceb9d791eeeb0a5493958f5d6d4dc7d91e59cf7 (patch)
tree8cef21acf9346fdbea36075029dc007fe969b51e /include/linux/kvm.h
parent9cf98828d12285d1fb43e774c8c100a55f8f34e1 (diff)
KVM: Add get/set irqchip ioctls for in-kernel PIC live migration support
This patch adds two new ioctls to dump and write kernel irqchips for save/restore and live migration. PIC s/r and l/m is implemented in this patch. Signed-off-by: Yaozu (Eddie) Dong <eddie.dong@intel.com> Signed-off-by: Qing He <qing.he@intel.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
Diffstat (limited to 'include/linux/kvm.h')
-rw-r--r--include/linux/kvm.h36
1 files changed, 36 insertions, 0 deletions
diff --git a/include/linux/kvm.h b/include/linux/kvm.h
index b0a13d1b34cc..6560f11870fd 100644
--- a/include/linux/kvm.h
+++ b/include/linux/kvm.h
@@ -45,6 +45,40 @@ struct kvm_irq_level {
45 __u32 level; 45 __u32 level;
46}; 46};
47 47
48/* for KVM_GET_IRQCHIP / KVM_SET_IRQCHIP */
49struct kvm_pic_state {
50 __u8 last_irr; /* edge detection */
51 __u8 irr; /* interrupt request register */
52 __u8 imr; /* interrupt mask register */
53 __u8 isr; /* interrupt service register */
54 __u8 priority_add; /* highest irq priority */
55 __u8 irq_base;
56 __u8 read_reg_select;
57 __u8 poll;
58 __u8 special_mask;
59 __u8 init_state;
60 __u8 auto_eoi;
61 __u8 rotate_on_auto_eoi;
62 __u8 special_fully_nested_mode;
63 __u8 init4; /* true if 4 byte init */
64 __u8 elcr; /* PIIX edge/trigger selection */
65 __u8 elcr_mask;
66};
67
68enum kvm_irqchip_id {
69 KVM_IRQCHIP_PIC_MASTER = 0,
70 KVM_IRQCHIP_PIC_SLAVE = 1,
71};
72
73struct kvm_irqchip {
74 __u32 chip_id;
75 __u32 pad;
76 union {
77 char dummy[512]; /* reserving space */
78 struct kvm_pic_state pic;
79 } chip;
80};
81
48enum kvm_exit_reason { 82enum kvm_exit_reason {
49 KVM_EXIT_UNKNOWN = 0, 83 KVM_EXIT_UNKNOWN = 0,
50 KVM_EXIT_EXCEPTION = 1, 84 KVM_EXIT_EXCEPTION = 1,
@@ -299,6 +333,8 @@ struct kvm_signal_mask {
299/* Device model IOC */ 333/* Device model IOC */
300#define KVM_CREATE_IRQCHIP _IO(KVMIO, 0x60) 334#define KVM_CREATE_IRQCHIP _IO(KVMIO, 0x60)
301#define KVM_IRQ_LINE _IOW(KVMIO, 0x61, struct kvm_irq_level) 335#define KVM_IRQ_LINE _IOW(KVMIO, 0x61, struct kvm_irq_level)
336#define KVM_GET_IRQCHIP _IOWR(KVMIO, 0x62, struct kvm_irqchip)
337#define KVM_SET_IRQCHIP _IOR(KVMIO, 0x63, struct kvm_irqchip)
302 338
303/* 339/*
304 * ioctls for vcpu fds 340 * ioctls for vcpu fds