diff options
| author | James Hogan <james.hogan@imgtec.com> | 2015-01-27 16:45:51 -0500 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2015-03-31 06:04:12 -0400 |
| commit | ea3c023ebf7130d72f9f00a3992c22176ef6703b (patch) | |
| tree | b86ffe4183b99e17774d5cb5ff793779dbb8e840 /include/linux/irqchip | |
| parent | 7e3e6cb29aeb64df24a0325ffd18892eca33e9b4 (diff) | |
IRQCHIP: mips-gic: Add missing definitions for FDC IRQ
Add missing VPE_PEND, VPE_RMASK and VPE_SMASK definitions for the local
FDC interrupt.
These local interrupt definitions aren't directly used, but if they
exist they should be complete.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: linux-mips@linux-mips.org
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9127/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/linux/irqchip')
| -rw-r--r-- | include/linux/irqchip/mips-gic.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h index e6a6aac451db..2e79b4bb2d75 100644 --- a/include/linux/irqchip/mips-gic.h +++ b/include/linux/irqchip/mips-gic.h | |||
| @@ -165,6 +165,8 @@ | |||
| 165 | #define GIC_VPE_PEND_SWINT0_MSK (MSK(1) << GIC_VPE_PEND_SWINT0_SHF) | 165 | #define GIC_VPE_PEND_SWINT0_MSK (MSK(1) << GIC_VPE_PEND_SWINT0_SHF) |
| 166 | #define GIC_VPE_PEND_SWINT1_SHF 5 | 166 | #define GIC_VPE_PEND_SWINT1_SHF 5 |
| 167 | #define GIC_VPE_PEND_SWINT1_MSK (MSK(1) << GIC_VPE_PEND_SWINT1_SHF) | 167 | #define GIC_VPE_PEND_SWINT1_MSK (MSK(1) << GIC_VPE_PEND_SWINT1_SHF) |
| 168 | #define GIC_VPE_PEND_FDC_SHF 6 | ||
| 169 | #define GIC_VPE_PEND_FDC_MSK (MSK(1) << GIC_VPE_PEND_FDC_SHF) | ||
| 168 | 170 | ||
| 169 | /* GIC_VPE_RMASK Masks */ | 171 | /* GIC_VPE_RMASK Masks */ |
| 170 | #define GIC_VPE_RMASK_WD_SHF 0 | 172 | #define GIC_VPE_RMASK_WD_SHF 0 |
| @@ -179,6 +181,8 @@ | |||
| 179 | #define GIC_VPE_RMASK_SWINT0_MSK (MSK(1) << GIC_VPE_RMASK_SWINT0_SHF) | 181 | #define GIC_VPE_RMASK_SWINT0_MSK (MSK(1) << GIC_VPE_RMASK_SWINT0_SHF) |
| 180 | #define GIC_VPE_RMASK_SWINT1_SHF 5 | 182 | #define GIC_VPE_RMASK_SWINT1_SHF 5 |
| 181 | #define GIC_VPE_RMASK_SWINT1_MSK (MSK(1) << GIC_VPE_RMASK_SWINT1_SHF) | 183 | #define GIC_VPE_RMASK_SWINT1_MSK (MSK(1) << GIC_VPE_RMASK_SWINT1_SHF) |
| 184 | #define GIC_VPE_RMASK_FDC_SHF 6 | ||
| 185 | #define GIC_VPE_RMASK_FDC_MSK (MSK(1) << GIC_VPE_RMASK_FDC_SHF) | ||
| 182 | 186 | ||
| 183 | /* GIC_VPE_SMASK Masks */ | 187 | /* GIC_VPE_SMASK Masks */ |
| 184 | #define GIC_VPE_SMASK_WD_SHF 0 | 188 | #define GIC_VPE_SMASK_WD_SHF 0 |
| @@ -193,6 +197,8 @@ | |||
| 193 | #define GIC_VPE_SMASK_SWINT0_MSK (MSK(1) << GIC_VPE_SMASK_SWINT0_SHF) | 197 | #define GIC_VPE_SMASK_SWINT0_MSK (MSK(1) << GIC_VPE_SMASK_SWINT0_SHF) |
| 194 | #define GIC_VPE_SMASK_SWINT1_SHF 5 | 198 | #define GIC_VPE_SMASK_SWINT1_SHF 5 |
| 195 | #define GIC_VPE_SMASK_SWINT1_MSK (MSK(1) << GIC_VPE_SMASK_SWINT1_SHF) | 199 | #define GIC_VPE_SMASK_SWINT1_MSK (MSK(1) << GIC_VPE_SMASK_SWINT1_SHF) |
| 200 | #define GIC_VPE_SMASK_FDC_SHF 6 | ||
| 201 | #define GIC_VPE_SMASK_FDC_MSK (MSK(1) << GIC_VPE_SMASK_FDC_SHF) | ||
| 196 | 202 | ||
| 197 | /* GIC nomenclature for Core Interrupt Pins. */ | 203 | /* GIC nomenclature for Core Interrupt Pins. */ |
| 198 | #define GIC_CPU_INT0 0 /* Core Interrupt 2 */ | 204 | #define GIC_CPU_INT0 0 /* Core Interrupt 2 */ |