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authorViresh Kumar <viresh.kumar@linaro.org>2012-11-12 12:26:03 -0500
committerViresh Kumar <viresh.kumar@linaro.org>2012-11-26 06:25:33 -0500
commitdf1590d9ae5e37e07e7cf91107e4c2c946ce8bf4 (patch)
tree7e17333920f4ab9986f3f40e881b4bc890a91724 /include/linux/irqchip
parente2eb69183ec4156eb814e67672e492bf902bbcd2 (diff)
ARM: SPEAr3xx: Shirq: Move shirq controller out of plat/
This patch moves shirq interrupt controllers driver and header file out of plat-spear directory. It is moved to drivers/irqchip/ directory. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Diffstat (limited to 'include/linux/irqchip')
-rw-r--r--include/linux/irqchip/spear-shirq.h64
1 files changed, 64 insertions, 0 deletions
diff --git a/include/linux/irqchip/spear-shirq.h b/include/linux/irqchip/spear-shirq.h
new file mode 100644
index 000000000000..c8be16d213a3
--- /dev/null
+++ b/include/linux/irqchip/spear-shirq.h
@@ -0,0 +1,64 @@
1/*
2 * SPEAr platform shared irq layer header file
3 *
4 * Copyright (C) 2009-2012 ST Microelectronics
5 * Viresh Kumar <viresh.linux@gmail.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#ifndef __SPEAR_SHIRQ_H
13#define __SPEAR_SHIRQ_H
14
15#include <linux/irq.h>
16#include <linux/types.h>
17
18/*
19 * struct shirq_regs: shared irq register configuration
20 *
21 * enb_reg: enable register offset
22 * reset_to_enb: val 1 indicates, we need to clear bit for enabling interrupt
23 * status_reg: status register offset
24 * status_reg_mask: status register valid mask
25 * clear_reg: clear register offset
26 * reset_to_clear: val 1 indicates, we need to clear bit for clearing interrupt
27 */
28struct shirq_regs {
29 u32 enb_reg;
30 u32 reset_to_enb;
31 u32 status_reg;
32 u32 clear_reg;
33 u32 reset_to_clear;
34};
35
36/*
37 * struct spear_shirq: shared irq structure
38 *
39 * irq: hardware irq number
40 * irq_base: base irq in linux domain
41 * irq_nr: no. of shared interrupts in a particular block
42 * irq_bit_off: starting bit offset in the status register
43 * invalid_irq: irq group is currently disabled
44 * base: base address of shared irq register
45 * regs: register configuration for shared irq block
46 */
47struct spear_shirq {
48 u32 irq;
49 u32 irq_base;
50 u32 irq_nr;
51 u32 irq_bit_off;
52 int invalid_irq;
53 void __iomem *base;
54 struct shirq_regs regs;
55};
56
57int __init spear300_shirq_of_init(struct device_node *np,
58 struct device_node *parent);
59int __init spear310_shirq_of_init(struct device_node *np,
60 struct device_node *parent);
61int __init spear320_shirq_of_init(struct device_node *np,
62 struct device_node *parent);
63
64#endif /* __SPEAR_SHIRQ_H */