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The LITMUS^RT kernel.

Bjoern Brandenburg

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author	Linus Torvalds <torvalds@linux-foundation.org>	2008-09-09 15:23:41 -0400
committer	Linus Torvalds <torvalds@linux-foundation.org>	2008-09-09 15:23:41 -0400
commit	93811d94f7e9bcfeed7d6ba75ea5d9c80a70ab95 (patch)
tree	ce7e4e6056b575138777793520dded9cb3638056 /include/linux/io-mapping.h
parent	ea81e2722e55ba0269c92f266763e445dcffb973 (diff)
parent	d6be118a97ce51ca84035270f91c2bccecbfac5f (diff)

Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip

* 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86: fix memmap=exactmap boot argument x86: disable static NOPLs on 32 bits xen: fix 2.6.27-rc5 xen balloon driver warnings

Diffstat (limited to 'include/linux/io-mapping.h')

0 files changed, 0 insertions, 0 deletions

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/******************************************************************************
             Device driver for Interphase ATM PCI adapter cards 
                    Author: Peter Wang  <pwang@iphase.com>            
                   Interphase Corporation  <www.iphase.com>           
                               Version: 1.0   
               iphase.h:  This is the header file for iphase.c. 
*******************************************************************************
      
      This software may be used and distributed according to the terms
      of the GNU General Public License (GPL), incorporated herein by reference.
      Drivers based on this skeleton fall under the GPL and must retain
      the authorship (implicit copyright) notice.

      This program is distributed in the hope that it will be useful, but
      WITHOUT ANY WARRANTY; without even the implied warranty of
      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
      General Public License for more details.
      
      Modified from an incomplete driver for Interphase 5575 1KVC 1M card which 
      was originally written by Monalisa Agrawal at UNH. Now this driver 
      supports a variety of varients of Interphase ATM PCI (i)Chip adapter 
      card family (See www.iphase.com/products/ClassSheet.cfm?ClassID=ATM) 
      in terms of PHY type, the size of control memory and the size of 
      packet memory. The followings are the change log and history:
     
          Bugfix the Mona's UBR driver.
          Modify the basic memory allocation and dma logic.
          Port the driver to the latest kernel from 2.0.46.
          Complete the ABR logic of the driver, and added the ABR work-
              around for the hardware anormalies.
          Add the CBR support.
	  Add the flow control logic to the driver to allow rate-limit VC.
          Add 4K VC support to the board with 512K control memory.
          Add the support of all the variants of the Interphase ATM PCI 
          (i)Chip adapter cards including x575 (155M OC3 and UTP155), x525
          (25M UTP25) and x531 (DS3 and E3).
          Add SMP support.

      Support and updates available at: ftp://ftp.iphase.com/pub/atm

*******************************************************************************/
  
#ifndef IPHASE_H  
#define IPHASE_H  


/************************ IADBG DEFINE *********************************/
/* IADebugFlag Bit Map */ 
#define IF_IADBG_INIT_ADAPTER   0x00000001        // init adapter info
#define IF_IADBG_TX             0x00000002        // debug TX
#define IF_IADBG_RX             0x00000004        // debug RX
#define IF_IADBG_QUERY_INFO     0x00000008        // debug Request call
#define IF_IADBG_SHUTDOWN       0x00000010        // debug shutdown event
#define IF_IADBG_INTR           0x00000020        // debug interrupt DPC
#define IF_IADBG_TXPKT          0x00000040  	  // debug TX PKT
#define IF_IADBG_RXPKT          0x00000080  	  // debug RX PKT
#define IF_IADBG_ERR            0x00000100        // debug system error
#define IF_IADBG_EVENT          0x00000200        // debug event
#define IF_IADBG_DIS_INTR       0x00001000        // debug disable interrupt
#define IF_IADBG_EN_INTR        0x00002000        // debug enable interrupt
#define IF_IADBG_LOUD           0x00004000        // debugging info
#define IF_IADBG_VERY_LOUD      0x00008000        // excessive debugging info
#define IF_IADBG_CBR            0x00100000  	  //
#define IF_IADBG_UBR            0x00200000  	  //
#define IF_IADBG_ABR            0x00400000        //
#define IF_IADBG_DESC           0x01000000        //
#define IF_IADBG_SUNI_STAT      0x02000000        // suni statistics
#define IF_IADBG_RESET          0x04000000        

#define IF_IADBG(f) if (IADebugFlag & (f))

#ifdef  CONFIG_ATM_IA_DEBUG   /* Debug build */

#define IF_LOUD(A) IF_IADBG(IF_IADBG_LOUD) { A }
#define IF_ERR(A) IF_IADBG(IF_IADBG_ERR) { A }
#define IF_VERY_LOUD(A) IF_IADBG( IF_IADBG_VERY_LOUD ) { A }

#define IF_INIT_ADAPTER(A) IF_IADBG( IF_IADBG_INIT_ADAPTER ) { A }
#define IF_INIT(A) IF_IADBG( IF_IADBG_INIT_ADAPTER ) { A }
#define IF_SUNI_STAT(A) IF_IADBG( IF_IADBG_SUNI_STAT ) { A }
#define IF_QUERY_INFO(A) IF_IADBG( IF_IADBG_QUERY_INFO ) { A }
#define IF_COPY_OVER(A) IF_IADBG( IF_IADBG_COPY_OVER ) { A }

#define IF_INTR(A) IF_IADBG( IF_IADBG_INTR ) { A }
#define IF_DIS_INTR(A) IF_IADBG( IF_IADBG_DIS_INTR ) { A }
#define IF_EN_INTR(A) IF_IADBG( IF_IADBG_EN_INTR ) { A }

#define IF_TX(A) IF_IADBG( IF_IADBG_TX ) { A }
#define IF_RX(A) IF_IADBG( IF_IADBG_RX ) { A }
#define IF_TXPKT(A) IF_IADBG( IF_IADBG_TXPKT ) { A }
#define IF_RXPKT(A) IF_IADBG( IF_IADBG_RXPKT ) { A }

#define IF_SHUTDOWN(A) IF_IADBG(IF_IADBG_SHUTDOWN) { A }
#define IF_CBR(A) IF_IADBG( IF_IADBG_CBR ) { A }
#define IF_UBR(A) IF_IADBG( IF_IADBG_UBR ) { A }
#define IF_ABR(A) IF_IADBG( IF_IADBG_ABR ) { A }
#define IF_EVENT(A) IF_IADBG( IF_IADBG_EVENT) { A }

#else /* free build */
#define IF_LOUD(A)
#define IF_VERY_LOUD(A)
#define IF_INIT_ADAPTER(A)
#define IF_INIT(A)
#define IF_SUNI_STAT(A)
#define IF_PVC_CHKPKT(A)
#define IF_QUERY_INFO(A)
#define IF_COPY_OVER(A)
#define IF_HANG(A)
#define IF_INTR(A)
#define IF_DIS_INTR(A)
#define IF_EN_INTR(A)
#define IF_TX(A)
#define IF_RX(A)
#define IF_TXDEBUG(A)
#define IF_VC(A)
#define IF_ERR(A) 
#define IF_CBR(A)
#define IF_UBR(A)
#define IF_ABR(A)
#define IF_SHUTDOWN(A)
#define DbgPrint(A)
#define IF_EVENT(A)
#define IF_TXPKT(A) 
#define IF_RXPKT(A)
#endif /* CONFIG_ATM_IA_DEBUG */ 

#define isprint(a) ((a >=' ')&&(a <= '~'))  
#define ATM_DESC(skb) (skb->protocol)
#define IA_SKB_STATE(skb) (skb->protocol)
#define IA_DLED   1
#define IA_TX_DONE 2

/* iadbg defines */
#define IA_CMD   0x7749
typedef struct {
	int cmd;
        int sub_cmd;
        int len;
        u32 maddr;
        int status;
        void __user *buf;
} IA_CMDBUF, *PIA_CMDBUF;

/* cmds */
#define MEMDUMP     		0x01

/* sub_cmds */
#define MEMDUMP_SEGREG          0x2
#define MEMDUMP_DEV  		0x1
#define MEMDUMP_REASSREG        0x3
#define MEMDUMP_FFL             0x4
#define READ_REG                0x5
#define WAKE_DBG_WAIT           0x6

/************************ IADBG DEFINE END ***************************/

#define Boolean(x)    	((x) ? 1 : 0)
#define NR_VCI 1024		/* number of VCIs */  
#define NR_VCI_LD 10		/* log2(NR_VCI) */  
#define NR_VCI_4K 4096 		/* number of VCIs */  
#define NR_VCI_4K_LD 12		/* log2(NR_VCI) */  
#define MEM_VALID 0xfffffff0	/* mask base address with this */  
  
#ifndef PCI_VENDOR_ID_IPHASE  
#define PCI_VENDOR_ID_IPHASE 0x107e  
#endif  
#ifndef PCI_DEVICE_ID_IPHASE_5575  
#define PCI_DEVICE_ID_IPHASE_5575 0x0008  
#endif  
#define DEV_LABEL 	"ia"  
#define PCR	207692  
#define ICR	100000  
#define MCR	0  
#define TBE	1000  
#define FRTT	1  
#define RIF	2		  
#define RDF	4  
#define NRMCODE 5	/* 0 - 7 */  
#define TRMCODE	3	/* 0 - 7 */  
#define CDFCODE	6  
#define ATDFCODE 2	/* 0 - 15 */  
  
/*---------------------- Packet/Cell Memory ------------------------*/  
#define TX_PACKET_RAM 	0x00000 /* start of Trasnmit Packet memory - 0 */  
#define DFL_TX_BUF_SZ	10240	/* 10 K buffers */  
#define DFL_TX_BUFFERS     50 	/* number of packet buffers for Tx   
					- descriptor 0 unused */  
#define REASS_RAM_SIZE 0x10000  /* for 64K 1K VC board */  
#define RX_PACKET_RAM 	0x80000 /* start of Receive Packet memory - 512K */  
#define DFL_RX_BUF_SZ	10240	/* 10k buffers */  
#define DFL_RX_BUFFERS      50	/* number of packet buffers for Rx   
					- descriptor 0 unused */  
  
struct cpcs_trailer 
{  
	u_short control;  
	u_short length;  
	u_int	crc32;  
};  

struct cpcs_trailer_desc
{
	struct cpcs_trailer *cpcs;
	dma_addr_t dma_addr;
};

struct ia_vcc 
{ 
	int rxing;	 
	int txing;		 
        int NumCbrEntry;
        u32 pcr;
        u32 saved_tx_quota;
        int flow_inc;
        struct sk_buff_head txing_skb; 
        int  ltimeout;                  
        u8  vc_desc_cnt;                
                
};  
  
struct abr_vc_table 
{  
	u_char status;  
	u_char rdf;  
	u_short air;  
	u_int res[3];  
	u_int req_rm_cell_data1;  
	u_int req_rm_cell_data2;  
	u_int add_rm_cell_data1;  
	u_int add_rm_cell_data2;  
};  
    
/* 32 byte entries */  
struct main_vc 
{  
	u_short 	type;  
#define ABR	0x8000  
#define UBR 	0xc000  
#define CBR	0x0000  
	/* ABR fields */  
	u_short 	nrm;	 
 	u_short 	trm;	   
	u_short 	rm_timestamp_hi;  
	u_short 	rm_timestamp_lo:8,  
			crm:8;		  
	u_short 	remainder; 	/* ABR and UBR fields - last 10 bits*/  
	u_short 	next_vc_sched;  
	u_short 	present_desc;	/* all classes */  
	u_short 	last_cell_slot;	/* ABR and UBR */  
	u_short 	pcr;  
	u_short 	fraction;  
	u_short 	icr;  
	u_short 	atdf;  
	u_short 	mcr;  
	u_short 	acr;		 
	u_short 	unack:8,  
			status:8;	/* all classes */  
#define UIOLI 0x80  
#define CRC_APPEND 0x40			/* for status field - CRC-32 append */  
#define ABR_STATE 0x02  
  
};  
  
  
/* 8 byte entries */  
struct ext_vc 
{  
	u_short 	atm_hdr1;  
	u_short 	atm_hdr2;  
	u_short 	last_desc;  
      	u_short 	out_of_rate_link;   /* reserved for UBR and CBR */  
};  
  
  
#define DLE_ENTRIES 256  
#define DMA_INT_ENABLE 0x0002	/* use for both Tx and Rx */  
#define TX_DLE_PSI 0x0001  
#define DLE_TOTAL_SIZE (sizeof(struct dle)*DLE_ENTRIES)
  
/* Descriptor List Entries (DLE) */  
struct dle 
{  
	u32 	sys_pkt_addr;  
	u32 	local_pkt_addr;  
	u32 	bytes;  
	u16 	prq_wr_ptr_data;  
	u16 	mode;  
};  
  
struct dle_q 
{  
	struct dle 	*start;  
	struct dle 	*end;  
	struct dle 	*read;  
	struct dle 	*write;  
};  
  
struct free_desc_q 
{  
	int 	desc;	/* Descriptor number */  
	struct free_desc_q *next;  
};  
  
struct tx_buf_desc {  
	unsigned short desc_mode;  
	unsigned short vc_index;  
	unsigned short res1;		/* reserved field */  
	unsigned short bytes;  
	unsigned short buf_start_hi;  
	unsigned short buf_start_lo;  
	unsigned short res2[10];	/* reserved field */  
};  
	  
  
struct rx_buf_desc { 
	unsigned short desc_mode;
	unsigned short vc_index;
	unsigned short vpi; 
	unsigned short bytes; 
	unsigned short buf_start_hi;  
	unsigned short buf_start_lo;  
	unsigned short dma_start_hi;  
	unsigned short dma_start_lo;  
	unsigned short crc_upper;  
	unsigned short crc_lower;  
	unsigned short res:8, timeout:8;  
	unsigned short res2[5];	/* reserved field */  
};  
  
/*--------SAR stuff ---------------------*/  
  
#define EPROM_SIZE 0x40000	/* says 64K in the docs ??? */  
#define MAC1_LEN	4	   					  
#define MAC2_LEN	2  
   
/*------------ PCI Memory Space Map, 128K SAR memory ----------------*/  
#define IPHASE5575_PCI_CONFIG_REG_BASE	0x0000  
#define IPHASE5575_BUS_CONTROL_REG_BASE 0x1000	/* offsets 0x00 - 0x3c */  
#define IPHASE5575_FRAG_CONTROL_REG_BASE 0x2000  
#define IPHASE5575_REASS_CONTROL_REG_BASE 0x3000  
#define IPHASE5575_DMA_CONTROL_REG_BASE	0x4000  
#define IPHASE5575_FRONT_END_REG_BASE IPHASE5575_DMA_CONTROL_REG_BASE  
#define IPHASE5575_FRAG_CONTROL_RAM_BASE 0x10000  
#define IPHASE5575_REASS_CONTROL_RAM_BASE 0x20000  
  
/*------------ Bus interface control registers -----------------*/  
#define IPHASE5575_BUS_CONTROL_REG	0x00  
#define IPHASE5575_BUS_STATUS_REG	0x01	/* actual offset 0x04 */  
#define IPHASE5575_MAC1			0x02  
#define IPHASE5575_REV			0x03  
#define IPHASE5575_MAC2			0x03	/*actual offset 0x0e-reg 0x0c*/  
#define IPHASE5575_EXT_RESET		0x04  
#define IPHASE5575_INT_RESET		0x05	/* addr 1c ?? reg 0x06 */  
#define IPHASE5575_PCI_ADDR_PAGE	0x07	/* reg 0x08, 0x09 ?? */  
#define IPHASE5575_EEPROM_ACCESS	0x0a	/* actual offset 0x28 */  
#define IPHASE5575_CELL_FIFO_QUEUE_SZ	0x0b  
#define IPHASE5575_CELL_FIFO_MARK_STATE	0x0c  
#define IPHASE5575_CELL_FIFO_READ_PTR	0x0d  
#define IPHASE5575_CELL_FIFO_WRITE_PTR	0x0e  
#define IPHASE5575_CELL_FIFO_CELLS_AVL	0x0f	/* actual offset 0x3c */  
  
/* Bus Interface Control Register bits */  
#define CTRL_FE_RST	0x80000000  
#define CTRL_LED	0x40000000  
#define CTRL_25MBPHY	0x10000000  
#define CTRL_ENCMBMEM	0x08000000  
#define CTRL_ENOFFSEG	0x01000000  
#define CTRL_ERRMASK	0x00400000  
#define CTRL_DLETMASK	0x00100000  
#define CTRL_DLERMASK	0x00080000  
#define CTRL_FEMASK	0x00040000  
#define CTRL_SEGMASK	0x00020000  
#define CTRL_REASSMASK	0x00010000  
#define CTRL_CSPREEMPT	0x00002000  
#define CTRL_B128	0x00000200  
#define CTRL_B64	0x00000100  
#define CTRL_B48	0x00000080  
#define CTRL_B32	0x00000040  
#define CTRL_B16	0x00000020  
#define CTRL_B8		0x00000010  
  
/* Bus Interface Status Register bits */  
#define STAT_CMEMSIZ	0xc0000000  
#define STAT_ADPARCK	0x20000000  
#define STAT_RESVD	0x1fffff80  
#define STAT_ERRINT	0x00000040  
#define STAT_MARKINT	0x00000020  
#define STAT_DLETINT	0x00000010  
#define STAT_DLERINT	0x00000008  
#define STAT_FEINT	0x00000004  
#define STAT_SEGINT	0x00000002  
#define STAT_REASSINT	0x00000001  
  
  
/*--------------- Segmentation control registers -----------------*/  
/* The segmentation registers are 16 bits access and the addresses  
	are defined as such so the addresses are the actual "offsets" */  
#define IDLEHEADHI	0x00  
#define IDLEHEADLO	0x01  
#define MAXRATE		0x02  
/* Values for MAXRATE register for 155Mbps and 25.6 Mbps operation */  
#define RATE155		0x64b1 // 16 bits float format 
#define MAX_ATM_155     352768 // Cells/second p.118
#define RATE25		0x5f9d  
  
#define STPARMS		0x03  
#define STPARMS_1K	0x008c  
#define STPARMS_2K	0x0049  
#define STPARMS_4K	0x0026  
#define COMP_EN		0x4000  
#define CBR_EN		0x2000  
#define ABR_EN		0x0800  
#define UBR_EN		0x0400  
  
#define ABRUBR_ARB	0x04  
#define RM_TYPE		0x05  
/*Value for RM_TYPE register for ATM Forum Traffic Mangement4.0 support*/  
#define RM_TYPE_4_0	0x0100  
  
#define SEG_COMMAND_REG		0x17  
/* Values for the command register */  
#define RESET_SEG 0x0055  
#define RESET_SEG_STATE	0x00aa  
#define RESET_TX_CELL_CTR 0x00cc  
  
#define CBR_PTR_BASE	0x20  
#define ABR_SBPTR_BASE	0x22  
#define UBR_SBPTR_BASE  0x23  
#define ABRWQ_BASE	0x26  
#define UBRWQ_BASE	0x27  
#define VCT_BASE	0x28  
#define VCTE_BASE	0x29  
#define CBR_TAB_BEG	0x2c  
#define CBR_TAB_END	0x2d  
#define PRQ_ST_ADR	0x30  
#define PRQ_ED_ADR	0x31  
#define PRQ_RD_PTR	0x32  
#define PRQ_WR_PTR	0x33  
#define TCQ_ST_ADR	0x34  
#define TCQ_ED_ADR 	0x35  
#define TCQ_RD_PTR	0x36  
#define TCQ_WR_PTR	0x37  
#define SEG_QUEUE_BASE	0x40  
#define SEG_DESC_BASE	0x41  
#define MODE_REG_0	0x45  
#define T_ONLINE	0x0002		/* (i)chipSAR is online */  
  
#define MODE_REG_1	0x46  
#define MODE_REG_1_VAL	0x0400		/*for propoer device operation*/  
  
#define SEG_INTR_STATUS_REG 0x47  
#define SEG_MASK_REG	0x48  
#define TRANSMIT_DONE 0x0200
#define TCQ_NOT_EMPTY 0x1000	/* this can be used for both the interrupt   
				status registers as well as the mask register */  
  
#define CELL_CTR_HIGH_AUTO 0x49  
#define CELL_CTR_HIGH_NOAUTO 0xc9  
#define CELL_CTR_LO_AUTO 0x4a  
#define CELL_CTR_LO_NOAUTO 0xca  
  
/* Diagnostic registers */  
#define NEXTDESC 	0x59  
#define NEXTVC		0x5a  
#define PSLOTCNT	0x5d  
#define NEWDN		0x6a  
#define NEWVC		0x6b  
#define SBPTR		0x6c  
#define ABRWQ_WRPTR	0x6f  
#define ABRWQ_RDPTR	0x70  
#define UBRWQ_WRPTR	0x71  
#define UBRWQ_RDPTR	0x72  
#define CBR_VC		0x73  
#define ABR_SBVC	0x75  
#define UBR_SBVC	0x76  
#define ABRNEXTLINK	0x78  
#define UBRNEXTLINK	0x79  
  
  
/*----------------- Reassembly control registers ---------------------*/  
/* The reassembly registers are 16 bits access and the addresses  
	are defined as such so the addresses are the actual "offsets" */  
#define MODE_REG	0x00  
#define R_ONLINE	0x0002		/* (i)chip is online */  
#define IGN_RAW_FL     	0x0004
  
#define PROTOCOL_ID	0x01  
#define REASS_MASK_REG	0x02  
#define REASS_INTR_STATUS_REG	0x03  
/* Interrupt Status register bits */  
#define RX_PKT_CTR_OF	0x8000  
#define RX_ERR_CTR_OF	0x4000  
#define RX_CELL_CTR_OF	0x1000  
#define RX_FREEQ_EMPT	0x0200


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