diff options
author | Han, Weidong <weidong.han@intel.com> | 2009-04-03 05:15:47 -0400 |
---|---|---|
committer | David Woodhouse <David.Woodhouse@intel.com> | 2009-04-03 16:46:01 -0400 |
commit | 161fde083f3403e7aa178dc944bf43c339e18491 (patch) | |
tree | 79473edadf7aad496c9158400ea7bb4f8336516e /include/linux/intel-iommu.h | |
parent | b24696bc55f66fecc30715e003f10fc2555a9271 (diff) |
intel-iommu: set compatibility format interrupt
When extended interrupt mode (x2apic mode) is not supported in a
system, it must set compatibility format interrupt to bypass
interrupt remapping, otherwise compatibility format interrupts
will be blocked.
This will be used when interrupt remapping is enabled while x2apic
is not supported.
Signed-off-by: Weidong Han <weidong.han@intel.com>
Acked-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'include/linux/intel-iommu.h')
-rw-r--r-- | include/linux/intel-iommu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h index 3771cd1f876e..aa8c53171233 100644 --- a/include/linux/intel-iommu.h +++ b/include/linux/intel-iommu.h | |||
@@ -164,6 +164,7 @@ static inline void dmar_writeq(void __iomem *addr, u64 val) | |||
164 | #define DMA_GCMD_QIE (((u32)1) << 26) | 164 | #define DMA_GCMD_QIE (((u32)1) << 26) |
165 | #define DMA_GCMD_SIRTP (((u32)1) << 24) | 165 | #define DMA_GCMD_SIRTP (((u32)1) << 24) |
166 | #define DMA_GCMD_IRE (((u32) 1) << 25) | 166 | #define DMA_GCMD_IRE (((u32) 1) << 25) |
167 | #define DMA_GCMD_CFI (((u32) 1) << 23) | ||
167 | 168 | ||
168 | /* GSTS_REG */ | 169 | /* GSTS_REG */ |
169 | #define DMA_GSTS_TES (((u32)1) << 31) | 170 | #define DMA_GSTS_TES (((u32)1) << 31) |
@@ -174,6 +175,7 @@ static inline void dmar_writeq(void __iomem *addr, u64 val) | |||
174 | #define DMA_GSTS_QIES (((u32)1) << 26) | 175 | #define DMA_GSTS_QIES (((u32)1) << 26) |
175 | #define DMA_GSTS_IRTPS (((u32)1) << 24) | 176 | #define DMA_GSTS_IRTPS (((u32)1) << 24) |
176 | #define DMA_GSTS_IRES (((u32)1) << 25) | 177 | #define DMA_GSTS_IRES (((u32)1) << 25) |
178 | #define DMA_GSTS_CFIS (((u32)1) << 23) | ||
177 | 179 | ||
178 | /* CCMD_REG */ | 180 | /* CCMD_REG */ |
179 | #define DMA_CCMD_ICC (((u64)1) << 63) | 181 | #define DMA_CCMD_ICC (((u64)1) << 63) |