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authorChanwoo Choi <cw00.choi@samsung.com>2014-07-31 03:32:46 -0400
committerChanwoo Choi <cw00.choi@samsung.com>2014-09-21 22:43:08 -0400
commitca2a07e45d1d3d31a0a85d2f63d81a897c610040 (patch)
tree774e177e1e6b2b505c8b26146a13d167f99773a5 /include/linux/extcon
parent0746d5d31f61721bf3e4ab84d75fac08d03e2a9a (diff)
extcon: sm5502: Move sm5502.h header file to extcon directory
This patch move sm5502.h header file from 'include/linux/extcon' to 'driver/extcon' because sm5502.h is used for driver/extcon/extcon-sm5502.c. and remove duplicate license description. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Diffstat (limited to 'include/linux/extcon')
-rw-r--r--include/linux/extcon/sm5502.h287
1 files changed, 0 insertions, 287 deletions
diff --git a/include/linux/extcon/sm5502.h b/include/linux/extcon/sm5502.h
deleted file mode 100644
index 030526bf8d79..000000000000
--- a/include/linux/extcon/sm5502.h
+++ /dev/null
@@ -1,287 +0,0 @@
1/*
2 * sm5502.h
3 *
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef __LINUX_EXTCON_SM5502_H
18#define __LINUX_EXTCON_SM5502_H
19
20enum sm5502_types {
21 TYPE_SM5502,
22};
23
24/* SM5502 registers */
25enum sm5502_reg {
26 SM5502_REG_DEVICE_ID = 0x01,
27 SM5502_REG_CONTROL,
28 SM5502_REG_INT1,
29 SM5502_REG_INT2,
30 SM5502_REG_INTMASK1,
31 SM5502_REG_INTMASK2,
32 SM5502_REG_ADC,
33 SM5502_REG_TIMING_SET1,
34 SM5502_REG_TIMING_SET2,
35 SM5502_REG_DEV_TYPE1,
36 SM5502_REG_DEV_TYPE2,
37 SM5502_REG_BUTTON1,
38 SM5502_REG_BUTTON2,
39 SM5502_REG_CAR_KIT_STATUS,
40 SM5502_REG_RSVD1,
41 SM5502_REG_RSVD2,
42 SM5502_REG_RSVD3,
43 SM5502_REG_RSVD4,
44 SM5502_REG_MANUAL_SW1,
45 SM5502_REG_MANUAL_SW2,
46 SM5502_REG_DEV_TYPE3,
47 SM5502_REG_RSVD5,
48 SM5502_REG_RSVD6,
49 SM5502_REG_RSVD7,
50 SM5502_REG_RSVD8,
51 SM5502_REG_RSVD9,
52 SM5502_REG_RESET,
53 SM5502_REG_RSVD10,
54 SM5502_REG_RESERVED_ID1,
55 SM5502_REG_RSVD11,
56 SM5502_REG_RSVD12,
57 SM5502_REG_RESERVED_ID2,
58 SM5502_REG_RSVD13,
59 SM5502_REG_OCP,
60 SM5502_REG_RSVD14,
61 SM5502_REG_RSVD15,
62 SM5502_REG_RSVD16,
63 SM5502_REG_RSVD17,
64 SM5502_REG_RSVD18,
65 SM5502_REG_RSVD19,
66 SM5502_REG_RSVD20,
67 SM5502_REG_RSVD21,
68 SM5502_REG_RSVD22,
69 SM5502_REG_RSVD23,
70 SM5502_REG_RSVD24,
71 SM5502_REG_RSVD25,
72 SM5502_REG_RSVD26,
73 SM5502_REG_RSVD27,
74 SM5502_REG_RSVD28,
75 SM5502_REG_RSVD29,
76 SM5502_REG_RSVD30,
77 SM5502_REG_RSVD31,
78 SM5502_REG_RSVD32,
79 SM5502_REG_RSVD33,
80 SM5502_REG_RSVD34,
81 SM5502_REG_RSVD35,
82 SM5502_REG_RSVD36,
83 SM5502_REG_RESERVED_ID3,
84
85 SM5502_REG_END,
86};
87
88/* Define SM5502 MASK/SHIFT constant */
89#define SM5502_REG_DEVICE_ID_VENDOR_SHIFT 0
90#define SM5502_REG_DEVICE_ID_VERSION_SHIFT 3
91#define SM5502_REG_DEVICE_ID_VENDOR_MASK (0x3 << SM5502_REG_DEVICE_ID_VENDOR_SHIFT)
92#define SM5502_REG_DEVICE_ID_VERSION_MASK (0x1f << SM5502_REG_DEVICE_ID_VERSION_SHIFT)
93
94#define SM5502_REG_CONTROL_MASK_INT_SHIFT 0
95#define SM5502_REG_CONTROL_WAIT_SHIFT 1
96#define SM5502_REG_CONTROL_MANUAL_SW_SHIFT 2
97#define SM5502_REG_CONTROL_RAW_DATA_SHIFT 3
98#define SM5502_REG_CONTROL_SW_OPEN_SHIFT 4
99#define SM5502_REG_CONTROL_MASK_INT_MASK (0x1 << SM5502_REG_CONTROL_MASK_INT_SHIFT)
100#define SM5502_REG_CONTROL_WAIT_MASK (0x1 << SM5502_REG_CONTROL_WAIT_SHIFT)
101#define SM5502_REG_CONTROL_MANUAL_SW_MASK (0x1 << SM5502_REG_CONTROL_MANUAL_SW_SHIFT)
102#define SM5502_REG_CONTROL_RAW_DATA_MASK (0x1 << SM5502_REG_CONTROL_RAW_DATA_SHIFT)
103#define SM5502_REG_CONTROL_SW_OPEN_MASK (0x1 << SM5502_REG_CONTROL_SW_OPEN_SHIFT)
104
105#define SM5502_REG_INTM1_ATTACH_SHIFT 0
106#define SM5502_REG_INTM1_DETACH_SHIFT 1
107#define SM5502_REG_INTM1_KP_SHIFT 2
108#define SM5502_REG_INTM1_LKP_SHIFT 3
109#define SM5502_REG_INTM1_LKR_SHIFT 4
110#define SM5502_REG_INTM1_OVP_EVENT_SHIFT 5
111#define SM5502_REG_INTM1_OCP_EVENT_SHIFT 6
112#define SM5502_REG_INTM1_OVP_OCP_DIS_SHIFT 7
113#define SM5502_REG_INTM1_ATTACH_MASK (0x1 << SM5502_REG_INTM1_ATTACH_SHIFT)
114#define SM5502_REG_INTM1_DETACH_MASK (0x1 << SM5502_REG_INTM1_DETACH_SHIFT)
115#define SM5502_REG_INTM1_KP_MASK (0x1 << SM5502_REG_INTM1_KP_SHIFT)
116#define SM5502_REG_INTM1_LKP_MASK (0x1 << SM5502_REG_INTM1_LKP_SHIFT)
117#define SM5502_REG_INTM1_LKR_MASK (0x1 << SM5502_REG_INTM1_LKR_SHIFT)
118#define SM5502_REG_INTM1_OVP_EVENT_MASK (0x1 << SM5502_REG_INTM1_OVP_EVENT_SHIFT)
119#define SM5502_REG_INTM1_OCP_EVENT_MASK (0x1 << SM5502_REG_INTM1_OCP_EVENT_SHIFT)
120#define SM5502_REG_INTM1_OVP_OCP_DIS_MASK (0x1 << SM5502_REG_INTM1_OVP_OCP_DIS_SHIFT)
121
122#define SM5502_REG_INTM2_VBUS_DET_SHIFT 0
123#define SM5502_REG_INTM2_REV_ACCE_SHIFT 1
124#define SM5502_REG_INTM2_ADC_CHG_SHIFT 2
125#define SM5502_REG_INTM2_STUCK_KEY_SHIFT 3
126#define SM5502_REG_INTM2_STUCK_KEY_RCV_SHIFT 4
127#define SM5502_REG_INTM2_MHL_SHIFT 5
128#define SM5502_REG_INTM2_VBUS_DET_MASK (0x1 << SM5502_REG_INTM2_VBUS_DET_SHIFT)
129#define SM5502_REG_INTM2_REV_ACCE_MASK (0x1 << SM5502_REG_INTM2_REV_ACCE_SHIFT)
130#define SM5502_REG_INTM2_ADC_CHG_MASK (0x1 << SM5502_REG_INTM2_ADC_CHG_SHIFT)
131#define SM5502_REG_INTM2_STUCK_KEY_MASK (0x1 << SM5502_REG_INTM2_STUCK_KEY_SHIFT)
132#define SM5502_REG_INTM2_STUCK_KEY_RCV_MASK (0x1 << SM5502_REG_INTM2_STUCK_KEY_RCV_SHIFT)
133#define SM5502_REG_INTM2_MHL_MASK (0x1 << SM5502_REG_INTM2_MHL_SHIFT)
134
135#define SM5502_REG_ADC_SHIFT 0
136#define SM5502_REG_ADC_MASK (0x1f << SM5502_REG_ADC_SHIFT)
137
138#define SM5502_REG_TIMING_SET1_KEY_PRESS_SHIFT 4
139#define SM5502_REG_TIMING_SET1_KEY_PRESS_MASK (0xf << SM5502_REG_TIMING_SET1_KEY_PRESS_SHIFT)
140#define TIMING_KEY_PRESS_100MS 0x0
141#define TIMING_KEY_PRESS_200MS 0x1
142#define TIMING_KEY_PRESS_300MS 0x2
143#define TIMING_KEY_PRESS_400MS 0x3
144#define TIMING_KEY_PRESS_500MS 0x4
145#define TIMING_KEY_PRESS_600MS 0x5
146#define TIMING_KEY_PRESS_700MS 0x6
147#define TIMING_KEY_PRESS_800MS 0x7
148#define TIMING_KEY_PRESS_900MS 0x8
149#define TIMING_KEY_PRESS_1000MS 0x9
150#define SM5502_REG_TIMING_SET1_ADC_DET_SHIFT 0
151#define SM5502_REG_TIMING_SET1_ADC_DET_MASK (0xf << SM5502_REG_TIMING_SET1_ADC_DET_SHIFT)
152#define TIMING_ADC_DET_50MS 0x0
153#define TIMING_ADC_DET_100MS 0x1
154#define TIMING_ADC_DET_150MS 0x2
155#define TIMING_ADC_DET_200MS 0x3
156#define TIMING_ADC_DET_300MS 0x4
157#define TIMING_ADC_DET_400MS 0x5
158#define TIMING_ADC_DET_500MS 0x6
159#define TIMING_ADC_DET_600MS 0x7
160#define TIMING_ADC_DET_700MS 0x8
161#define TIMING_ADC_DET_800MS 0x9
162#define TIMING_ADC_DET_900MS 0xA
163#define TIMING_ADC_DET_1000MS 0xB
164
165#define SM5502_REG_TIMING_SET2_SW_WAIT_SHIFT 4
166#define SM5502_REG_TIMING_SET2_SW_WAIT_MASK (0xf << SM5502_REG_TIMING_SET2_SW_WAIT_SHIFT)
167#define TIMING_SW_WAIT_10MS 0x0
168#define TIMING_SW_WAIT_30MS 0x1
169#define TIMING_SW_WAIT_50MS 0x2
170#define TIMING_SW_WAIT_70MS 0x3
171#define TIMING_SW_WAIT_90MS 0x4
172#define TIMING_SW_WAIT_110MS 0x5
173#define TIMING_SW_WAIT_130MS 0x6
174#define TIMING_SW_WAIT_150MS 0x7
175#define TIMING_SW_WAIT_170MS 0x8
176#define TIMING_SW_WAIT_190MS 0x9
177#define TIMING_SW_WAIT_210MS 0xA
178#define SM5502_REG_TIMING_SET2_LONG_KEY_SHIFT 0
179#define SM5502_REG_TIMING_SET2_LONG_KEY_MASK (0xf << SM5502_REG_TIMING_SET2_LONG_KEY_SHIFT)
180#define TIMING_LONG_KEY_300MS 0x0
181#define TIMING_LONG_KEY_400MS 0x1
182#define TIMING_LONG_KEY_500MS 0x2
183#define TIMING_LONG_KEY_600MS 0x3
184#define TIMING_LONG_KEY_700MS 0x4
185#define TIMING_LONG_KEY_800MS 0x5
186#define TIMING_LONG_KEY_900MS 0x6
187#define TIMING_LONG_KEY_1000MS 0x7
188#define TIMING_LONG_KEY_1100MS 0x8
189#define TIMING_LONG_KEY_1200MS 0x9
190#define TIMING_LONG_KEY_1300MS 0xA
191#define TIMING_LONG_KEY_1400MS 0xB
192#define TIMING_LONG_KEY_1500MS 0xC
193
194#define SM5502_REG_DEV_TYPE1_AUDIO_TYPE1_SHIFT 0
195#define SM5502_REG_DEV_TYPE1_AUDIO_TYPE2_SHIFT 1
196#define SM5502_REG_DEV_TYPE1_USB_SDP_SHIFT 2
197#define SM5502_REG_DEV_TYPE1_UART_SHIFT 3
198#define SM5502_REG_DEV_TYPE1_CAR_KIT_CHARGER_SHIFT 4
199#define SM5502_REG_DEV_TYPE1_USB_CHG_SHIFT 5
200#define SM5502_REG_DEV_TYPE1_DEDICATED_CHG_SHIFT 6
201#define SM5502_REG_DEV_TYPE1_USB_OTG_SHIFT 7
202#define SM5502_REG_DEV_TYPE1_AUDIO_TYPE1_MASK (0x1 << SM5502_REG_DEV_TYPE1_AUDIO_TYPE1_SHIFT)
203#define SM5502_REG_DEV_TYPE1_AUDIO_TYPE1__MASK (0x1 << SM5502_REG_DEV_TYPE1_AUDIO_TYPE2_SHIFT)
204#define SM5502_REG_DEV_TYPE1_USB_SDP_MASK (0x1 << SM5502_REG_DEV_TYPE1_USB_SDP_SHIFT)
205#define SM5502_REG_DEV_TYPE1_UART_MASK (0x1 << SM5502_REG_DEV_TYPE1_UART_SHIFT)
206#define SM5502_REG_DEV_TYPE1_CAR_KIT_CHARGER_MASK (0x1 << SM5502_REG_DEV_TYPE1_CAR_KIT_CHARGER_SHIFT)
207#define SM5502_REG_DEV_TYPE1_USB_CHG_MASK (0x1 << SM5502_REG_DEV_TYPE1_USB_CHG_SHIFT)
208#define SM5502_REG_DEV_TYPE1_DEDICATED_CHG_MASK (0x1 << SM5502_REG_DEV_TYPE1_DEDICATED_CHG_SHIFT)
209#define SM5502_REG_DEV_TYPE1_USB_OTG_MASK (0x1 << SM5502_REG_DEV_TYPE1_USB_OTG_SHIFT)
210
211#define SM5502_REG_DEV_TYPE2_JIG_USB_ON_SHIFT 0
212#define SM5502_REG_DEV_TYPE2_JIG_USB_OFF_SHIFT 1
213#define SM5502_REG_DEV_TYPE2_JIG_UART_ON_SHIFT 2
214#define SM5502_REG_DEV_TYPE2_JIG_UART_OFF_SHIFT 3
215#define SM5502_REG_DEV_TYPE2_PPD_SHIFT 4
216#define SM5502_REG_DEV_TYPE2_TTY_SHIFT 5
217#define SM5502_REG_DEV_TYPE2_AV_CABLE_SHIFT 6
218#define SM5502_REG_DEV_TYPE2_JIG_USB_ON_MASK (0x1 << SM5502_REG_DEV_TYPE2_JIG_USB_ON_SHIFT)
219#define SM5502_REG_DEV_TYPE2_JIG_USB_OFF_MASK (0x1 << SM5502_REG_DEV_TYPE2_JIG_USB_OFF_SHIFT)
220#define SM5502_REG_DEV_TYPE2_JIG_UART_ON_MASK (0x1 << SM5502_REG_DEV_TYPE2_JIG_UART_ON_SHIFT)
221#define SM5502_REG_DEV_TYPE2_JIG_UART_OFF_MASK (0x1 << SM5502_REG_DEV_TYPE2_JIG_UART_OFF_SHIFT)
222#define SM5502_REG_DEV_TYPE2_PPD_MASK (0x1 << SM5502_REG_DEV_TYPE2_PPD_SHIFT)
223#define SM5502_REG_DEV_TYPE2_TTY_MASK (0x1 << SM5502_REG_DEV_TYPE2_TTY_SHIFT)
224#define SM5502_REG_DEV_TYPE2_AV_CABLE_MASK (0x1 << SM5502_REG_DEV_TYPE2_AV_CABLE_SHIFT)
225
226#define SM5502_REG_MANUAL_SW1_VBUSIN_SHIFT 0
227#define SM5502_REG_MANUAL_SW1_DP_SHIFT 2
228#define SM5502_REG_MANUAL_SW1_DM_SHIFT 5
229#define SM5502_REG_MANUAL_SW1_VBUSIN_MASK (0x3 << SM5502_REG_MANUAL_SW1_VBUSIN_SHIFT)
230#define SM5502_REG_MANUAL_SW1_DP_MASK (0x7 << SM5502_REG_MANUAL_SW1_DP_SHIFT)
231#define SM5502_REG_MANUAL_SW1_DM_MASK (0x7 << SM5502_REG_MANUAL_SW1_DM_SHIFT)
232#define VBUSIN_SWITCH_OPEN 0x0
233#define VBUSIN_SWITCH_VBUSOUT 0x1
234#define VBUSIN_SWITCH_MIC 0x2
235#define VBUSIN_SWITCH_VBUSOUT_WITH_USB 0x3
236#define DM_DP_CON_SWITCH_OPEN 0x0
237#define DM_DP_CON_SWITCH_USB 0x1
238#define DM_DP_CON_SWITCH_AUDIO 0x2
239#define DM_DP_CON_SWITCH_UART 0x3
240#define DM_DP_SWITCH_OPEN ((DM_DP_CON_SWITCH_OPEN <<SM5502_REG_MANUAL_SW1_DP_SHIFT) \
241 | (DM_DP_CON_SWITCH_OPEN <<SM5502_REG_MANUAL_SW1_DM_SHIFT))
242#define DM_DP_SWITCH_USB ((DM_DP_CON_SWITCH_USB <<SM5502_REG_MANUAL_SW1_DP_SHIFT) \
243 | (DM_DP_CON_SWITCH_USB <<SM5502_REG_MANUAL_SW1_DM_SHIFT))
244#define DM_DP_SWITCH_AUDIO ((DM_DP_CON_SWITCH_AUDIO <<SM5502_REG_MANUAL_SW1_DP_SHIFT) \
245 | (DM_DP_CON_SWITCH_AUDIO <<SM5502_REG_MANUAL_SW1_DM_SHIFT))
246#define DM_DP_SWITCH_UART ((DM_DP_CON_SWITCH_UART <<SM5502_REG_MANUAL_SW1_DP_SHIFT) \
247 | (DM_DP_CON_SWITCH_UART <<SM5502_REG_MANUAL_SW1_DM_SHIFT))
248
249/* SM5502 Interrupts */
250enum sm5502_irq {
251 /* INT1 */
252 SM5502_IRQ_INT1_ATTACH,
253 SM5502_IRQ_INT1_DETACH,
254 SM5502_IRQ_INT1_KP,
255 SM5502_IRQ_INT1_LKP,
256 SM5502_IRQ_INT1_LKR,
257 SM5502_IRQ_INT1_OVP_EVENT,
258 SM5502_IRQ_INT1_OCP_EVENT,
259 SM5502_IRQ_INT1_OVP_OCP_DIS,
260
261 /* INT2 */
262 SM5502_IRQ_INT2_VBUS_DET,
263 SM5502_IRQ_INT2_REV_ACCE,
264 SM5502_IRQ_INT2_ADC_CHG,
265 SM5502_IRQ_INT2_STUCK_KEY,
266 SM5502_IRQ_INT2_STUCK_KEY_RCV,
267 SM5502_IRQ_INT2_MHL,
268
269 SM5502_IRQ_NUM,
270};
271
272#define SM5502_IRQ_INT1_ATTACH_MASK BIT(0)
273#define SM5502_IRQ_INT1_DETACH_MASK BIT(1)
274#define SM5502_IRQ_INT1_KP_MASK BIT(2)
275#define SM5502_IRQ_INT1_LKP_MASK BIT(3)
276#define SM5502_IRQ_INT1_LKR_MASK BIT(4)
277#define SM5502_IRQ_INT1_OVP_EVENT_MASK BIT(5)
278#define SM5502_IRQ_INT1_OCP_EVENT_MASK BIT(6)
279#define SM5502_IRQ_INT1_OVP_OCP_DIS_MASK BIT(7)
280#define SM5502_IRQ_INT2_VBUS_DET_MASK BIT(0)
281#define SM5502_IRQ_INT2_REV_ACCE_MASK BIT(1)
282#define SM5502_IRQ_INT2_ADC_CHG_MASK BIT(2)
283#define SM5502_IRQ_INT2_STUCK_KEY_MASK BIT(3)
284#define SM5502_IRQ_INT2_STUCK_KEY_RCV_MASK BIT(4)
285#define SM5502_IRQ_INT2_MHL_MASK BIT(5)
286
287#endif /* __LINUX_EXTCON_SM5502_H */
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