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authorMike Turquette <mturquette@linaro.org>2014-06-10 19:53:25 -0400
committerMike Turquette <mturquette@linaro.org>2014-06-10 19:53:25 -0400
commit3f6eec9969d24f91a3909d51e86e007ca5efd4c4 (patch)
treebff0f51bab78b18d52cfd57ad7cd8b78ac6a882c /include/linux/clk
parent963649d735c8b6eb0f97e82c54f02426ff3f1f45 (diff)
parent7e148070001ae82df08966199580a29b934e3bf3 (diff)
Merge branch 'for-v3.16/ti-clk-drv' of github.com:t-kristo/linux-pm into clk-next
Diffstat (limited to 'include/linux/clk')
-rw-r--r--include/linux/clk/ti.h35
1 files changed, 34 insertions, 1 deletions
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 4a21a872dbbd..e8d8a35034a5 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -41,6 +41,8 @@
41 * @idlest_reg: register containing the DPLL idle status bitfield 41 * @idlest_reg: register containing the DPLL idle status bitfield
42 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg 42 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
43 * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg 43 * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
44 * @dcc_mask: mask of the DPLL DCC correction bitfield @mult_div1_reg
45 * @dcc_rate: rate atleast which DCC @dcc_mask must be set
44 * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg 46 * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
45 * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg 47 * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
46 * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg 48 * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
@@ -86,6 +88,8 @@ struct dpll_data {
86 u32 idlest_mask; 88 u32 idlest_mask;
87 u32 dco_mask; 89 u32 dco_mask;
88 u32 sddiv_mask; 90 u32 sddiv_mask;
91 u32 dcc_mask;
92 unsigned long dcc_rate;
89 u32 lpmode_mask; 93 u32 lpmode_mask;
90 u32 m4xen_mask; 94 u32 m4xen_mask;
91 u8 auto_recal_bit; 95 u8 auto_recal_bit;
@@ -94,7 +98,26 @@ struct dpll_data {
94 u8 flags; 98 u8 flags;
95}; 99};
96 100
97struct clk_hw_omap_ops; 101struct clk_hw_omap;
102
103/**
104 * struct clk_hw_omap_ops - OMAP clk ops
105 * @find_idlest: find idlest register information for a clock
106 * @find_companion: find companion clock register information for a clock,
107 * basically converts CM_ICLKEN* <-> CM_FCLKEN*
108 * @allow_idle: enables autoidle hardware functionality for a clock
109 * @deny_idle: prevent autoidle hardware functionality for a clock
110 */
111struct clk_hw_omap_ops {
112 void (*find_idlest)(struct clk_hw_omap *oclk,
113 void __iomem **idlest_reg,
114 u8 *idlest_bit, u8 *idlest_val);
115 void (*find_companion)(struct clk_hw_omap *oclk,
116 void __iomem **other_reg,
117 u8 *other_bit);
118 void (*allow_idle)(struct clk_hw_omap *oclk);
119 void (*deny_idle)(struct clk_hw_omap *oclk);
120};
98 121
99/** 122/**
100 * struct clk_hw_omap - OMAP struct clk 123 * struct clk_hw_omap - OMAP struct clk
@@ -259,6 +282,12 @@ int omap2_dflt_clk_enable(struct clk_hw *hw);
259void omap2_dflt_clk_disable(struct clk_hw *hw); 282void omap2_dflt_clk_disable(struct clk_hw *hw);
260int omap2_dflt_clk_is_enabled(struct clk_hw *hw); 283int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
261void omap3_clk_lock_dpll5(void); 284void omap3_clk_lock_dpll5(void);
285unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
286 unsigned long parent_rate);
287int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate,
288 unsigned long parent_rate);
289void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw);
290void omap2xxx_clkt_vps_init(void);
262 291
263void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index); 292void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index);
264void ti_dt_clocks_register(struct ti_dt_clk *oclks); 293void ti_dt_clocks_register(struct ti_dt_clk *oclks);
@@ -278,6 +307,8 @@ int omap5xxx_dt_clk_init(void);
278int dra7xx_dt_clk_init(void); 307int dra7xx_dt_clk_init(void);
279int am33xx_dt_clk_init(void); 308int am33xx_dt_clk_init(void);
280int am43xx_dt_clk_init(void); 309int am43xx_dt_clk_init(void);
310int omap2420_dt_clk_init(void);
311int omap2430_dt_clk_init(void);
281 312
282#ifdef CONFIG_OF 313#ifdef CONFIG_OF
283void of_ti_clk_allow_autoidle_all(void); 314void of_ti_clk_allow_autoidle_all(void);
@@ -287,6 +318,8 @@ static inline void of_ti_clk_allow_autoidle_all(void) { }
287static inline void of_ti_clk_deny_autoidle_all(void) { } 318static inline void of_ti_clk_deny_autoidle_all(void) { }
288#endif 319#endif
289 320
321extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
322extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
290extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; 323extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
291extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; 324extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
292extern const struct clk_hw_omap_ops clkhwops_wait; 325extern const struct clk_hw_omap_ops clkhwops_wait;