Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into fixes

The merge of the 'clk-for-linus' branch caused an automated
merge failure. Pull that in here so we can fix the problem.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

3 files changed, 226 insertions, 1 deletions

diff --git a/include/linux/bcma/bcma.h b/include/linux/bcma/bcma.h
index 8deaf6d050c3..1954a4e305a3 100644
--- a/include/linux/bcma/bcma.h
+++ b/include/linux/bcma/bcma.h
@@ -7,6 +7,7 @@
 #include <linux/bcma/bcma_driver_chipcommon.h>
 #include <linux/bcma/bcma_driver_pci.h>
 #include <linux/bcma/bcma_driver_mips.h>
+#include <linux/bcma/bcma_driver_gmac_cmn.h>
 #include <linux/ssb/ssb.h> /* SPROM sharing */
 
 #include "bcma_regs.h"
@@ -70,6 +71,13 @@ struct bcma_host_ops {
 
 /* Core-ID values. */
 #define BCMA_CORE_OOB_ROUTER            0x367   /* Out of band */
+#define BCMA_CORE_4706_CHIPCOMMON       0x500
+#define BCMA_CORE_4706_SOC_RAM          0x50E
+#define BCMA_CORE_4706_MAC_GBIT         0x52D
+#define BCMA_CORE_AMEMC                 0x52E   /* DDR1/2 memory controller core */
+#define BCMA_CORE_ALTA                  0x534   /* I2S core */
+#define BCMA_CORE_4706_MAC_GBIT_COMMON  0x5DC
+#define BCMA_CORE_DDR23_PHY             0x5DD
 #define BCMA_CORE_INVALID               0x700
 #define BCMA_CORE_CHIPCOMMON            0x800
 #define BCMA_CORE_ILINE20               0x801
@@ -130,6 +138,36 @@ struct bcma_host_ops {
 
 #define BCMA_MAX_NR_CORES               16
 
+/* Chip IDs of PCIe devices */
+#define BCMA_CHIP_ID_BCM4313    0x4313
+#define BCMA_CHIP_ID_BCM43224   43224
+#define  BCMA_PKG_ID_BCM43224_FAB_CSM   0x8
+#define  BCMA_PKG_ID_BCM43224_FAB_SMIC  0xa
+#define BCMA_CHIP_ID_BCM43225   43225
+#define BCMA_CHIP_ID_BCM43227   43227
+#define BCMA_CHIP_ID_BCM43228   43228
+#define BCMA_CHIP_ID_BCM43421   43421
+#define BCMA_CHIP_ID_BCM43428   43428
+#define BCMA_CHIP_ID_BCM43431   43431
+#define BCMA_CHIP_ID_BCM43460   43460
+#define BCMA_CHIP_ID_BCM4331    0x4331
+#define BCMA_CHIP_ID_BCM6362    0x6362
+#define BCMA_CHIP_ID_BCM4360    0x4360
+#define BCMA_CHIP_ID_BCM4352    0x4352
+
+/* Chip IDs of SoCs */
+#define BCMA_CHIP_ID_BCM4706    0x5300
+#define BCMA_CHIP_ID_BCM4716    0x4716
+#define  BCMA_PKG_ID_BCM4716    8
+#define  BCMA_PKG_ID_BCM4717    9
+#define  BCMA_PKG_ID_BCM4718    10
+#define BCMA_CHIP_ID_BCM47162   47162
+#define BCMA_CHIP_ID_BCM4748    0x4748
+#define BCMA_CHIP_ID_BCM4749    0x4749
+#define BCMA_CHIP_ID_BCM5356    0x5356
+#define BCMA_CHIP_ID_BCM5357    0x5357
+#define BCMA_CHIP_ID_BCM53572   53572
+
 struct bcma_device {
         struct bcma_bus *bus;
         struct bcma_device_id id;
@@ -215,6 +253,7 @@ struct bcma_bus {
         struct bcma_drv_cc drv_cc;
         struct bcma_drv_pci drv_pci;
         struct bcma_drv_mips drv_mips;
+        struct bcma_drv_gmac_cmn drv_gmac_cmn;
 
         /* We decided to share SPROM struct with SSB as long as we do not need
          * any hacks for BCMA. This simplifies drivers code. */
diff --git a/include/linux/bcma/bcma_driver_chipcommon.h b/include/linux/bcma/bcma_driver_chipcommon.h
index 8bbfe31fbac8..3c80885fa829 100644
--- a/include/linux/bcma/bcma_driver_chipcommon.h
+++ b/include/linux/bcma/bcma_driver_chipcommon.h
@@ -24,7 +24,7 @@
 #define   BCMA_CC_FLASHT_NONE           0x00000000      /* No flash */
 #define   BCMA_CC_FLASHT_STSER          0x00000100      /* ST serial flash */
 #define   BCMA_CC_FLASHT_ATSER          0x00000200      /* Atmel serial flash */
-#define   BCMA_CC_FLASHT_NFLASH         0x00000200
+#define   BCMA_CC_FLASHT_NFLASH         0x00000200      /* NAND flash */
 #define   BCMA_CC_FLASHT_PARA           0x00000700      /* Parallel flash */
 #define  BCMA_CC_CAP_PLLT               0x00038000      /* PLL Type */
 #define   BCMA_PLLTYPE_NONE             0x00000000
@@ -45,6 +45,7 @@
 #define  BCMA_CC_CAP_PMU                0x10000000      /* PMU available (rev >= 20) */
 #define  BCMA_CC_CAP_ECI                0x20000000      /* ECI available (rev >= 20) */
 #define  BCMA_CC_CAP_SPROM              0x40000000      /* SPROM present */
+#define  BCMA_CC_CAP_NFLASH             0x80000000      /* NAND flash present (rev >= 35 or BCM4706?) */
 #define BCMA_CC_CORECTL                 0x0008
 #define  BCMA_CC_CORECTL_UARTCLK0       0x00000001      /* Drive UART with internal clock */
 #define  BCMA_CC_CORECTL_SE             0x00000002      /* sync clk out enable (corerev >= 3) */
@@ -88,6 +89,11 @@
 #define  BCMA_CC_CHIPST_4313_OTP_PRESENT        2
 #define  BCMA_CC_CHIPST_4331_SPROM_PRESENT      2
 #define  BCMA_CC_CHIPST_4331_OTP_PRESENT        4
+#define  BCMA_CC_CHIPST_4706_PKG_OPTION         BIT(0) /* 0: full-featured package 1: low-cost package */
+#define  BCMA_CC_CHIPST_4706_SFLASH_PRESENT     BIT(1) /* 0: parallel, 1: serial flash is present */
+#define  BCMA_CC_CHIPST_4706_SFLASH_TYPE        BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
+#define  BCMA_CC_CHIPST_4706_MIPS_BENDIAN       BIT(3) /* 0: little, 1: big endian */
+#define  BCMA_CC_CHIPST_4706_PCIE1_DISABLE      BIT(5) /* PCIE1 enable strap pin */
 #define BCMA_CC_JCMD                    0x0030          /* Rev >= 10 only */
 #define  BCMA_CC_JCMD_START             0x80000000
 #define  BCMA_CC_JCMD_BUSY              0x80000000
@@ -117,10 +123,58 @@
 #define  BCMA_CC_JCTL_EXT_EN            2               /* Enable external targets */
 #define  BCMA_CC_JCTL_EN                1               /* Enable Jtag master */
 #define BCMA_CC_FLASHCTL                0x0040
+/* Start/busy bit in flashcontrol */
+#define  BCMA_CC_FLASHCTL_OPCODE        0x000000ff
+#define  BCMA_CC_FLASHCTL_ACTION        0x00000700
+#define  BCMA_CC_FLASHCTL_CS_ACTIVE     0x00001000      /* Chip Select Active, rev >= 20 */
 #define  BCMA_CC_FLASHCTL_START         0x80000000
 #define  BCMA_CC_FLASHCTL_BUSY          BCMA_CC_FLASHCTL_START
+/* Flashcontrol action + opcodes for ST flashes */
+#define  BCMA_CC_FLASHCTL_ST_WREN       0x0006          /* Write Enable */
+#define  BCMA_CC_FLASHCTL_ST_WRDIS      0x0004          /* Write Disable */
+#define  BCMA_CC_FLASHCTL_ST_RDSR       0x0105          /* Read Status Register */
+#define  BCMA_CC_FLASHCTL_ST_WRSR       0x0101          /* Write Status Register */
+#define  BCMA_CC_FLASHCTL_ST_READ       0x0303          /* Read Data Bytes */
+#define  BCMA_CC_FLASHCTL_ST_PP         0x0302          /* Page Program */
+#define  BCMA_CC_FLASHCTL_ST_SE         0x02d8          /* Sector Erase */
+#define  BCMA_CC_FLASHCTL_ST_BE         0x00c7          /* Bulk Erase */
+#define  BCMA_CC_FLASHCTL_ST_DP         0x00b9          /* Deep Power-down */
+#define  BCMA_CC_FLASHCTL_ST_RES        0x03ab          /* Read Electronic Signature */
+#define  BCMA_CC_FLASHCTL_ST_CSA        0x1000          /* Keep chip select asserted */
+#define  BCMA_CC_FLASHCTL_ST_SSE        0x0220          /* Sub-sector Erase */
+/* Flashcontrol action + opcodes for Atmel flashes */
+#define  BCMA_CC_FLASHCTL_AT_READ                       0x07e8
+#define  BCMA_CC_FLASHCTL_AT_PAGE_READ                  0x07d2
+#define  BCMA_CC_FLASHCTL_AT_STATUS                     0x01d7
+#define  BCMA_CC_FLASHCTL_AT_BUF1_WRITE                 0x0384
+#define  BCMA_CC_FLASHCTL_AT_BUF2_WRITE                 0x0387
+#define  BCMA_CC_FLASHCTL_AT_BUF1_ERASE_PROGRAM         0x0283
+#define  BCMA_CC_FLASHCTL_AT_BUF2_ERASE_PROGRAM         0x0286
+#define  BCMA_CC_FLASHCTL_AT_BUF1_PROGRAM               0x0288
+#define  BCMA_CC_FLASHCTL_AT_BUF2_PROGRAM               0x0289
+#define  BCMA_CC_FLASHCTL_AT_PAGE_ERASE                 0x0281
+#define  BCMA_CC_FLASHCTL_AT_BLOCK_ERASE                0x0250
+#define  BCMA_CC_FLASHCTL_AT_BUF1_WRITE_ERASE_PROGRAM   0x0382
+#define  BCMA_CC_FLASHCTL_AT_BUF2_WRITE_ERASE_PROGRAM   0x0385
+#define  BCMA_CC_FLASHCTL_AT_BUF1_LOAD                  0x0253
+#define  BCMA_CC_FLASHCTL_AT_BUF2_LOAD                  0x0255
+#define  BCMA_CC_FLASHCTL_AT_BUF1_COMPARE               0x0260
+#define  BCMA_CC_FLASHCTL_AT_BUF2_COMPARE               0x0261
+#define  BCMA_CC_FLASHCTL_AT_BUF1_REPROGRAM             0x0258
+#define  BCMA_CC_FLASHCTL_AT_BUF2_REPROGRAM             0x0259
 #define BCMA_CC_FLASHADDR               0x0044
 #define BCMA_CC_FLASHDATA               0x0048
+/* Status register bits for ST flashes */
+#define  BCMA_CC_FLASHDATA_ST_WIP       0x01            /* Write In Progress */
+#define  BCMA_CC_FLASHDATA_ST_WEL       0x02            /* Write Enable Latch */
+#define  BCMA_CC_FLASHDATA_ST_BP_MASK   0x1c            /* Block Protect */
+#define  BCMA_CC_FLASHDATA_ST_BP_SHIFT  2
+#define  BCMA_CC_FLASHDATA_ST_SRWD      0x80            /* Status Register Write Disable */
+/* Status register bits for Atmel flashes */
+#define  BCMA_CC_FLASHDATA_AT_READY     0x80
+#define  BCMA_CC_FLASHDATA_AT_MISMATCH  0x40
+#define  BCMA_CC_FLASHDATA_AT_ID_MASK   0x38
+#define  BCMA_CC_FLASHDATA_AT_ID_SHIFT  3
 #define BCMA_CC_BCAST_ADDR              0x0050
 #define BCMA_CC_BCAST_DATA              0x0054
 #define BCMA_CC_GPIOPULLUP              0x0058          /* Rev >= 20 only */
@@ -280,6 +334,15 @@
 
 /* 4706 PMU */
 #define BCMA_CC_PMU4706_MAINPLL_PLL0    0
+#define BCMA_CC_PMU6_4706_PROCPLL_OFF   4       /* The CPU PLL */
+#define  BCMA_CC_PMU6_4706_PROC_P2DIV_MASK      0x000f0000
+#define  BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT     16
+#define  BCMA_CC_PMU6_4706_PROC_P1DIV_MASK      0x0000f000
+#define  BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT     12
+#define  BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK   0x00000ff8
+#define  BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT  3
+#define  BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK  0x00000007
+#define  BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0
 
 /* ALP clock on pre-PMU chips */
 #define BCMA_CC_PMU_ALP_CLOCK           20000000
@@ -308,6 +371,19 @@
 #define BCMA_CC_PPL_PCHI_OFF            5
 #define BCMA_CC_PPL_PCHI_MASK           0x0000003f
 
+#define BCMA_CC_PMU_PLL_CTL0            0
+#define BCMA_CC_PMU_PLL_CTL1            1
+#define BCMA_CC_PMU_PLL_CTL2            2
+#define BCMA_CC_PMU_PLL_CTL3            3
+#define BCMA_CC_PMU_PLL_CTL4            4
+#define BCMA_CC_PMU_PLL_CTL5            5
+
+#define BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK        0x00f00000
+#define BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT       20
+
+#define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK     0x1ff00000
+#define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT    20
+
 /* BCM4331 ChipControl numbers. */
 #define BCMA_CHIPCTL_4331_BT_COEXIST            BIT(0)  /* 0 disable */
 #define BCMA_CHIPCTL_4331_SECI                  BIT(1)  /* 0 SECI is disabled (JATG functional) */
@@ -321,9 +397,18 @@
 #define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN    BIT(9)  /* override core control on pipe_AuxPowerDown */
 #define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN         BIT(10) /* pcie_auxclkenable */
 #define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN     BIT(11) /* pcie_pipe_pllpowerdown */
+#define BCMA_CHIPCTL_4331_EXTPA_EN2             BIT(12) /* 0 ext pa disable, 1 ext pa enabled */
 #define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4      BIT(16) /* enable bt_shd0 at gpio4 */
 #define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5      BIT(17) /* enable bt_shd1 at gpio5 */
 
+/* 43224 chip-specific ChipControl register bits */
+#define BCMA_CCTRL_43224_GPIO_TOGGLE            0x8000          /* gpio[3:0] pins as btcoex or s/w gpio */
+#define BCMA_CCTRL_43224A0_12MA_LED_DRIVE       0x00F000F0      /* 12 mA drive strength */
+#define BCMA_CCTRL_43224B0_12MA_LED_DRIVE       0xF0            /* 12 mA drive strength for later 43224s */
+
+/* 4313 Chip specific ChipControl register bits */
+#define BCMA_CCTRL_4313_12MA_LED_DRIVE          0x00000007      /* 12 mA drive strengh for later 4313 */
+
 /* Data for the PMU, if available.
  * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
  */
@@ -411,5 +496,6 @@ extern void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
                                         u32 offset, u32 mask, u32 set);
 extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc,
                                        u32 offset, u32 mask, u32 set);
+extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid);
 
 #endif /* LINUX_BCMA_DRIVER_CC_H_ */
diff --git a/include/linux/bcma/bcma_driver_gmac_cmn.h b/include/linux/bcma/bcma_driver_gmac_cmn.h
new file mode 100644
index 000000000000..def894b83b0d
--- /dev/null
+++ b/include/linux/bcma/bcma_driver_gmac_cmn.h
@@ -0,0 +1,100 @@
+#ifndef LINUX_BCMA_DRIVER_GMAC_CMN_H_
+#define LINUX_BCMA_DRIVER_GMAC_CMN_H_
+
+#include <linux/types.h>
+
+#define BCMA_GMAC_CMN_STAG0             0x000
+#define BCMA_GMAC_CMN_STAG1             0x004
+#define BCMA_GMAC_CMN_STAG2             0x008
+#define BCMA_GMAC_CMN_STAG3             0x00C
+#define BCMA_GMAC_CMN_PARSER_CTL        0x020
+#define BCMA_GMAC_CMN_MIB_MAX_LEN       0x024
+#define BCMA_GMAC_CMN_PHY_ACCESS        0x100
+#define  BCMA_GMAC_CMN_PA_DATA_MASK     0x0000ffff
+#define  BCMA_GMAC_CMN_PA_ADDR_MASK     0x001f0000
+#define  BCMA_GMAC_CMN_PA_ADDR_SHIFT    16
+#define  BCMA_GMAC_CMN_PA_REG_MASK      0x1f000000
+#define  BCMA_GMAC_CMN_PA_REG_SHIFT     24
+#define  BCMA_GMAC_CMN_PA_WRITE         0x20000000
+#define  BCMA_GMAC_CMN_PA_START         0x40000000
+#define BCMA_GMAC_CMN_PHY_CTL           0x104
+#define  BCMA_GMAC_CMN_PC_EPA_MASK      0x0000001f
+#define  BCMA_GMAC_CMN_PC_MCT_MASK      0x007f0000
+#define  BCMA_GMAC_CMN_PC_MCT_SHIFT     16
+#define  BCMA_GMAC_CMN_PC_MTE           0x00800000
+#define BCMA_GMAC_CMN_GMAC0_RGMII_CTL   0x110
+#define BCMA_GMAC_CMN_CFP_ACCESS        0x200
+#define BCMA_GMAC_CMN_CFP_TCAM_DATA0    0x210
+#define BCMA_GMAC_CMN_CFP_TCAM_DATA1    0x214
+#define BCMA_GMAC_CMN_CFP_TCAM_DATA2    0x218
+#define BCMA_GMAC_CMN_CFP_TCAM_DATA3    0x21C
+#define BCMA_GMAC_CMN_CFP_TCAM_DATA4    0x220
+#define BCMA_GMAC_CMN_CFP_TCAM_DATA5    0x224
+#define BCMA_GMAC_CMN_CFP_TCAM_DATA6    0x228
+#define BCMA_GMAC_CMN_CFP_TCAM_DATA7    0x22C
+#define BCMA_GMAC_CMN_CFP_TCAM_MASK0    0x230
+#define BCMA_GMAC_CMN_CFP_TCAM_MASK1    0x234
+#define BCMA_GMAC_CMN_CFP_TCAM_MASK2    0x238
+#define BCMA_GMAC_CMN_CFP_TCAM_MASK3    0x23C
+#define BCMA_GMAC_CMN_CFP_TCAM_MASK4    0x240
+#define BCMA_GMAC_CMN_CFP_TCAM_MASK5    0x244
+#define BCMA_GMAC_CMN_CFP_TCAM_MASK6    0x248
+#define BCMA_GMAC_CMN_CFP_TCAM_MASK7    0x24C
+#define BCMA_GMAC_CMN_CFP_ACTION_DATA   0x250
+#define BCMA_GMAC_CMN_TCAM_BIST_CTL     0x2A0
+#define BCMA_GMAC_CMN_TCAM_BIST_STATUS  0x2A4
+#define BCMA_GMAC_CMN_TCAM_CMP_STATUS   0x2A8
+#define BCMA_GMAC_CMN_TCAM_DISABLE      0x2AC
+#define BCMA_GMAC_CMN_TCAM_TEST_CTL     0x2F0
+#define BCMA_GMAC_CMN_UDF_0_A3_A0       0x300
+#define BCMA_GMAC_CMN_UDF_0_A7_A4       0x304
+#define BCMA_GMAC_CMN_UDF_0_A8          0x308
+#define BCMA_GMAC_CMN_UDF_1_A3_A0       0x310
+#define BCMA_GMAC_CMN_UDF_1_A7_A4       0x314
+#define BCMA_GMAC_CMN_UDF_1_A8          0x318
+#define BCMA_GMAC_CMN_UDF_2_A3_A0       0x320
+#define BCMA_GMAC_CMN_UDF_2_A7_A4       0x324
+#define BCMA_GMAC_CMN_UDF_2_A8          0x328
+#define BCMA_GMAC_CMN_UDF_0_B3_B0       0x330
+#define BCMA_GMAC_CMN_UDF_0_B7_B4       0x334
+#define BCMA_GMAC_CMN_UDF_0_B8          0x338
+#define BCMA_GMAC_CMN_UDF_1_B3_B0       0x340
+#define BCMA_GMAC_CMN_UDF_1_B7_B4       0x344
+#define BCMA_GMAC_CMN_UDF_1_B8          0x348
+#define BCMA_GMAC_CMN_UDF_2_B3_B0       0x350
+#define BCMA_GMAC_CMN_UDF_2_B7_B4       0x354
+#define BCMA_GMAC_CMN_UDF_2_B8          0x358
+#define BCMA_GMAC_CMN_UDF_0_C3_C0       0x360
+#define BCMA_GMAC_CMN_UDF_0_C7_C4       0x364
+#define BCMA_GMAC_CMN_UDF_0_C8          0x368
+#define BCMA_GMAC_CMN_UDF_1_C3_C0       0x370
+#define BCMA_GMAC_CMN_UDF_1_C7_C4       0x374
+#define BCMA_GMAC_CMN_UDF_1_C8          0x378
+#define BCMA_GMAC_CMN_UDF_2_C3_C0       0x380
+#define BCMA_GMAC_CMN_UDF_2_C7_C4       0x384
+#define BCMA_GMAC_CMN_UDF_2_C8          0x388
+#define BCMA_GMAC_CMN_UDF_0_D3_D0       0x390
+#define BCMA_GMAC_CMN_UDF_0_D7_D4       0x394
+#define BCMA_GMAC_CMN_UDF_0_D11_D8      0x394
+
+struct bcma_drv_gmac_cmn {
+        struct bcma_device *core;
+
+        /* Drivers accessing BCMA_GMAC_CMN_PHY_ACCESS and
+         * BCMA_GMAC_CMN_PHY_CTL need to take that mutex first. */
+        struct mutex phy_mutex;
+};
+
+/* Register access */
+#define gmac_cmn_read16(gc, offset)             bcma_read16((gc)->core, offset)
+#define gmac_cmn_read32(gc, offset)             bcma_read32((gc)->core, offset)
+#define gmac_cmn_write16(gc, offset, val)       bcma_write16((gc)->core, offset, val)
+#define gmac_cmn_write32(gc, offset, val)       bcma_write32((gc)->core, offset, val)
+
+#ifdef CONFIG_BCMA_DRIVER_GMAC_CMN
+extern void __devinit bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc);
+#else
+static inline void bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc) { }
+#endif
+
+#endif /* LINUX_BCMA_DRIVER_GMAC_CMN_H_ */