bcma: add support for BCM43142

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

2 files changed, 56 insertions, 0 deletions

diff --git a/include/linux/bcma/bcma.h b/include/linux/bcma/bcma.h
index 2e34db82a643..622fc505d3e1 100644
--- a/include/linux/bcma/bcma.h
+++ b/include/linux/bcma/bcma.h
@@ -144,6 +144,7 @@ struct bcma_host_ops {
 
 /* Chip IDs of PCIe devices */
 #define BCMA_CHIP_ID_BCM4313    0x4313
+#define BCMA_CHIP_ID_BCM43142   43142
 #define BCMA_CHIP_ID_BCM43224   43224
 #define  BCMA_PKG_ID_BCM43224_FAB_CSM   0x8
 #define  BCMA_PKG_ID_BCM43224_FAB_SMIC  0xa
diff --git a/include/linux/bcma/bcma_driver_chipcommon.h b/include/linux/bcma/bcma_driver_chipcommon.h
index b8b09eac60a4..c49e1a159e6e 100644
--- a/include/linux/bcma/bcma_driver_chipcommon.h
+++ b/include/linux/bcma/bcma_driver_chipcommon.h
@@ -330,6 +330,8 @@
 #define BCMA_CC_PMU_CAP                 0x0604 /* PMU capabilities */
 #define  BCMA_CC_PMU_CAP_REVISION       0x000000FF /* Revision mask */
 #define BCMA_CC_PMU_STAT                0x0608 /* PMU status */
+#define  BCMA_CC_PMU_STAT_EXT_LPO_AVAIL 0x00000100
+#define  BCMA_CC_PMU_STAT_WDRESET       0x00000080
 #define  BCMA_CC_PMU_STAT_INTPEND       0x00000040 /* Interrupt pending */
 #define  BCMA_CC_PMU_STAT_SBCLKST       0x00000030 /* Backplane clock status? */
 #define  BCMA_CC_PMU_STAT_HAVEALP       0x00000008 /* ALP available */
@@ -355,6 +357,11 @@
 #define BCMA_CC_REGCTL_DATA             0x065C
 #define BCMA_CC_PLLCTL_ADDR             0x0660
 #define BCMA_CC_PLLCTL_DATA             0x0664
+#define BCMA_CC_PMU_STRAPOPT            0x0668 /* (corerev >= 28) */
+#define BCMA_CC_PMU_XTAL_FREQ           0x066C /* (pmurev >= 10) */
+#define  BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK      0x00001FFF
+#define  BCMA_CC_PMU_XTAL_FREQ_MEASURE_MASK     0x80000000
+#define  BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT    31
 #define BCMA_CC_SPROM                   0x0800 /* SPROM beginning */
 /* NAND flash MLC controller registers (corerev >= 38) */
 #define BCMA_CC_NAND_REVISION           0x0C00
@@ -435,6 +442,23 @@
 #define  BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK  0x00000007
 #define  BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0
 
+/* PMU rev 15 */
+#define BCMA_CC_PMU15_PLL_PLLCTL0       0
+#define  BCMA_CC_PMU15_PLL_PC0_CLKSEL_MASK      0x00000003
+#define  BCMA_CC_PMU15_PLL_PC0_CLKSEL_SHIFT     0
+#define  BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK     0x003FFFFC
+#define  BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT    2
+#define  BCMA_CC_PMU15_PLL_PC0_PRESCALE_MASK    0x00C00000
+#define  BCMA_CC_PMU15_PLL_PC0_PRESCALE_SHIFT   22
+#define  BCMA_CC_PMU15_PLL_PC0_KPCTRL_MASK      0x07000000
+#define  BCMA_CC_PMU15_PLL_PC0_KPCTRL_SHIFT     24
+#define  BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_MASK    0x38000000
+#define  BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_SHIFT   27
+#define  BCMA_CC_PMU15_PLL_PC0_FDCMODE_MASK     0x40000000
+#define  BCMA_CC_PMU15_PLL_PC0_FDCMODE_SHIFT    30
+#define  BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_MASK    0x80000000
+#define  BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_SHIFT   31
+
 /* ALP clock on pre-PMU chips */
 #define BCMA_CC_PMU_ALP_CLOCK           20000000
 /* HT clock for systems with PMU-enabled chipcommon */
@@ -507,6 +531,37 @@
 #define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE       BIT(18)
 #define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE    BIT(19)
 
+#define BCMA_RES_4314_LPLDO_PU                  BIT(0)
+#define BCMA_RES_4314_PMU_SLEEP_DIS             BIT(1)
+#define BCMA_RES_4314_PMU_BG_PU                 BIT(2)
+#define BCMA_RES_4314_CBUCK_LPOM_PU             BIT(3)
+#define BCMA_RES_4314_CBUCK_PFM_PU              BIT(4)
+#define BCMA_RES_4314_CLDO_PU                   BIT(5)
+#define BCMA_RES_4314_LPLDO2_LVM                BIT(6)
+#define BCMA_RES_4314_WL_PMU_PU                 BIT(7)
+#define BCMA_RES_4314_LNLDO_PU                  BIT(8)
+#define BCMA_RES_4314_LDO3P3_PU                 BIT(9)
+#define BCMA_RES_4314_OTP_PU                    BIT(10)
+#define BCMA_RES_4314_XTAL_PU                   BIT(11)
+#define BCMA_RES_4314_WL_PWRSW_PU               BIT(12)
+#define BCMA_RES_4314_LQ_AVAIL                  BIT(13)
+#define BCMA_RES_4314_LOGIC_RET                 BIT(14)
+#define BCMA_RES_4314_MEM_SLEEP                 BIT(15)
+#define BCMA_RES_4314_MACPHY_RET                BIT(16)
+#define BCMA_RES_4314_WL_CORE_READY             BIT(17)
+#define BCMA_RES_4314_ILP_REQ                   BIT(18)
+#define BCMA_RES_4314_ALP_AVAIL                 BIT(19)
+#define BCMA_RES_4314_MISC_PWRSW_PU             BIT(20)
+#define BCMA_RES_4314_SYNTH_PWRSW_PU            BIT(21)
+#define BCMA_RES_4314_RX_PWRSW_PU               BIT(22)
+#define BCMA_RES_4314_RADIO_PU                  BIT(23)
+#define BCMA_RES_4314_VCO_LDO_PU                BIT(24)
+#define BCMA_RES_4314_AFE_LDO_PU                BIT(25)
+#define BCMA_RES_4314_RX_LDO_PU                 BIT(26)
+#define BCMA_RES_4314_TX_LDO_PU                 BIT(27)
+#define BCMA_RES_4314_HT_AVAIL                  BIT(28)
+#define BCMA_RES_4314_MACPHY_CLK_AVAIL          BIT(29)
+
 /* Data for the PMU, if available.
  * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
  */