arm/arm64: KVM: add virtual GICv3 distributor emulation

With everything separated and prepared, we implement a model of a
GICv3 distributor and redistributors by using the existing framework
to provide handler functions for each register group.

Currently we limit the emulation to a model enforcing a single
security state, with SRE==1 (forcing system register access) and
ARE==1 (allowing more than 8 VCPUs).

We share some of the functions provided for GICv2 emulation, but take
the different ways of addressing (v)CPUs into account.
Save and restore is currently not implemented.

Similar to the split-off of the GICv2 specific code, the new emulation
code goes into a new file (vgic-v3-emul.c).

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>

1 files changed, 8 insertions, 1 deletions

diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h
index ff04afd0d901..98c30168bce4 100644
--- a/include/kvm/arm_vgic.h
+++ b/include/kvm/arm_vgic.h
@@ -162,7 +162,11 @@ struct vgic_dist {
 
         /* Distributor and vcpu interface mapping in the guest */
         phys_addr_t             vgic_dist_base;
-        phys_addr_t             vgic_cpu_base;
+        /* GICv2 and GICv3 use different mapped register blocks */
+        union {
+                phys_addr_t             vgic_cpu_base;
+                phys_addr_t             vgic_redist_base;
+        };
 
         /* Distributor enabled */
         u32                     enabled;
@@ -224,6 +228,9 @@ struct vgic_dist {
          */
         struct vgic_bitmap      *irq_spi_target;
 
+        /* Target MPIDR for each IRQ (needed for GICv3 IROUTERn) only */
+        u32                     *irq_spi_mpidr;
+
         /* Bitmap indicating which CPU has something pending */
         unsigned long           *irq_pending_on_cpu;