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authorStephen Boyd <sboyd@codeaurora.org>2014-01-15 13:47:30 -0500
committerMike Turquette <mturquette@linaro.org>2014-01-16 15:01:04 -0500
commitd33faa9ead8da261e75815b74b41ac7ff265da9a (patch)
treeda3941b0bf6c55f19dd6fd250a169342b711bab7 /include/dt-bindings
parent6d00b56fe8c6f10076c9477e1cce99caf4568760 (diff)
clk: qcom: Add support for MSM8974's global clock controller (GCC)
Add a driver for the global clock controller found on MSM 8974 based platforms. This should allow most non-multimedia device drivers to probe and control their clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'include/dt-bindings')
-rw-r--r--include/dt-bindings/clock/qcom,gcc-msm8974.h320
-rw-r--r--include/dt-bindings/reset/qcom,gcc-msm8974.h96
2 files changed, 416 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8974.h b/include/dt-bindings/clock/qcom,gcc-msm8974.h
new file mode 100644
index 000000000000..223ca174d9d3
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-msm8974.h
@@ -0,0 +1,320 @@
1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _DT_BINDINGS_CLK_MSM_GCC_8974_H
15#define _DT_BINDINGS_CLK_MSM_GCC_8974_H
16
17#define GPLL0 0
18#define GPLL0_VOTE 1
19#define CONFIG_NOC_CLK_SRC 2
20#define GPLL2 3
21#define GPLL2_VOTE 4
22#define GPLL3 5
23#define GPLL3_VOTE 6
24#define PERIPH_NOC_CLK_SRC 7
25#define BLSP_UART_SIM_CLK_SRC 8
26#define QDSS_TSCTR_CLK_SRC 9
27#define BIMC_DDR_CLK_SRC 10
28#define SYSTEM_NOC_CLK_SRC 11
29#define GPLL1 12
30#define GPLL1_VOTE 13
31#define RPM_CLK_SRC 14
32#define GCC_BIMC_CLK 15
33#define BIMC_DDR_CPLL0_ROOT_CLK_SRC 16
34#define KPSS_AHB_CLK_SRC 17
35#define QDSS_AT_CLK_SRC 18
36#define USB30_MASTER_CLK_SRC 19
37#define BIMC_DDR_CPLL1_ROOT_CLK_SRC 20
38#define QDSS_STM_CLK_SRC 21
39#define ACC_CLK_SRC 22
40#define SEC_CTRL_CLK_SRC 23
41#define BLSP1_QUP1_I2C_APPS_CLK_SRC 24
42#define BLSP1_QUP1_SPI_APPS_CLK_SRC 25
43#define BLSP1_QUP2_I2C_APPS_CLK_SRC 26
44#define BLSP1_QUP2_SPI_APPS_CLK_SRC 27
45#define BLSP1_QUP3_I2C_APPS_CLK_SRC 28
46#define BLSP1_QUP3_SPI_APPS_CLK_SRC 29
47#define BLSP1_QUP4_I2C_APPS_CLK_SRC 30
48#define BLSP1_QUP4_SPI_APPS_CLK_SRC 31
49#define BLSP1_QUP5_I2C_APPS_CLK_SRC 32
50#define BLSP1_QUP5_SPI_APPS_CLK_SRC 33
51#define BLSP1_QUP6_I2C_APPS_CLK_SRC 34
52#define BLSP1_QUP6_SPI_APPS_CLK_SRC 35
53#define BLSP1_UART1_APPS_CLK_SRC 36
54#define BLSP1_UART2_APPS_CLK_SRC 37
55#define BLSP1_UART3_APPS_CLK_SRC 38
56#define BLSP1_UART4_APPS_CLK_SRC 39
57#define BLSP1_UART5_APPS_CLK_SRC 40
58#define BLSP1_UART6_APPS_CLK_SRC 41
59#define BLSP2_QUP1_I2C_APPS_CLK_SRC 42
60#define BLSP2_QUP1_SPI_APPS_CLK_SRC 43
61#define BLSP2_QUP2_I2C_APPS_CLK_SRC 44
62#define BLSP2_QUP2_SPI_APPS_CLK_SRC 45
63#define BLSP2_QUP3_I2C_APPS_CLK_SRC 46
64#define BLSP2_QUP3_SPI_APPS_CLK_SRC 47
65#define BLSP2_QUP4_I2C_APPS_CLK_SRC 48
66#define BLSP2_QUP4_SPI_APPS_CLK_SRC 49
67#define BLSP2_QUP5_I2C_APPS_CLK_SRC 50
68#define BLSP2_QUP5_SPI_APPS_CLK_SRC 51
69#define BLSP2_QUP6_I2C_APPS_CLK_SRC 52
70#define BLSP2_QUP6_SPI_APPS_CLK_SRC 53
71#define BLSP2_UART1_APPS_CLK_SRC 54
72#define BLSP2_UART2_APPS_CLK_SRC 55
73#define BLSP2_UART3_APPS_CLK_SRC 56
74#define BLSP2_UART4_APPS_CLK_SRC 57
75#define BLSP2_UART5_APPS_CLK_SRC 58
76#define BLSP2_UART6_APPS_CLK_SRC 59
77#define CE1_CLK_SRC 60
78#define CE2_CLK_SRC 61
79#define GP1_CLK_SRC 62
80#define GP2_CLK_SRC 63
81#define GP3_CLK_SRC 64
82#define PDM2_CLK_SRC 65
83#define QDSS_TRACECLKIN_CLK_SRC 66
84#define RBCPR_CLK_SRC 67
85#define SDCC1_APPS_CLK_SRC 68
86#define SDCC2_APPS_CLK_SRC 69
87#define SDCC3_APPS_CLK_SRC 70
88#define SDCC4_APPS_CLK_SRC 71
89#define SPMI_AHB_CLK_SRC 72
90#define SPMI_SER_CLK_SRC 73
91#define TSIF_REF_CLK_SRC 74
92#define USB30_MOCK_UTMI_CLK_SRC 75
93#define USB_HS_SYSTEM_CLK_SRC 76
94#define USB_HSIC_CLK_SRC 77
95#define USB_HSIC_IO_CAL_CLK_SRC 78
96#define USB_HSIC_SYSTEM_CLK_SRC 79
97#define GCC_BAM_DMA_AHB_CLK 80
98#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK 81
99#define GCC_BIMC_CFG_AHB_CLK 82
100#define GCC_BIMC_KPSS_AXI_CLK 83
101#define GCC_BIMC_SLEEP_CLK 84
102#define GCC_BIMC_SYSNOC_AXI_CLK 85
103#define GCC_BIMC_XO_CLK 86
104#define GCC_BLSP1_AHB_CLK 87
105#define GCC_BLSP1_SLEEP_CLK 88
106#define GCC_BLSP1_QUP1_I2C_APPS_CLK 89
107#define GCC_BLSP1_QUP1_SPI_APPS_CLK 90
108#define GCC_BLSP1_QUP2_I2C_APPS_CLK 91
109#define GCC_BLSP1_QUP2_SPI_APPS_CLK 92
110#define GCC_BLSP1_QUP3_I2C_APPS_CLK 93
111#define GCC_BLSP1_QUP3_SPI_APPS_CLK 94
112#define GCC_BLSP1_QUP4_I2C_APPS_CLK 95
113#define GCC_BLSP1_QUP4_SPI_APPS_CLK 96
114#define GCC_BLSP1_QUP5_I2C_APPS_CLK 97
115#define GCC_BLSP1_QUP5_SPI_APPS_CLK 98
116#define GCC_BLSP1_QUP6_I2C_APPS_CLK 99
117#define GCC_BLSP1_QUP6_SPI_APPS_CLK 100
118#define GCC_BLSP1_UART1_APPS_CLK 101
119#define GCC_BLSP1_UART1_SIM_CLK 102
120#define GCC_BLSP1_UART2_APPS_CLK 103
121#define GCC_BLSP1_UART2_SIM_CLK 104
122#define GCC_BLSP1_UART3_APPS_CLK 105
123#define GCC_BLSP1_UART3_SIM_CLK 106
124#define GCC_BLSP1_UART4_APPS_CLK 107
125#define GCC_BLSP1_UART4_SIM_CLK 108
126#define GCC_BLSP1_UART5_APPS_CLK 109
127#define GCC_BLSP1_UART5_SIM_CLK 110
128#define GCC_BLSP1_UART6_APPS_CLK 111
129#define GCC_BLSP1_UART6_SIM_CLK 112
130#define GCC_BLSP2_AHB_CLK 113
131#define GCC_BLSP2_SLEEP_CLK 114
132#define GCC_BLSP2_QUP1_I2C_APPS_CLK 115
133#define GCC_BLSP2_QUP1_SPI_APPS_CLK 116
134#define GCC_BLSP2_QUP2_I2C_APPS_CLK 117
135#define GCC_BLSP2_QUP2_SPI_APPS_CLK 118
136#define GCC_BLSP2_QUP3_I2C_APPS_CLK 119
137#define GCC_BLSP2_QUP3_SPI_APPS_CLK 120
138#define GCC_BLSP2_QUP4_I2C_APPS_CLK 121
139#define GCC_BLSP2_QUP4_SPI_APPS_CLK 122
140#define GCC_BLSP2_QUP5_I2C_APPS_CLK 123
141#define GCC_BLSP2_QUP5_SPI_APPS_CLK 124
142#define GCC_BLSP2_QUP6_I2C_APPS_CLK 125
143#define GCC_BLSP2_QUP6_SPI_APPS_CLK 126
144#define GCC_BLSP2_UART1_APPS_CLK 127
145#define GCC_BLSP2_UART1_SIM_CLK 128
146#define GCC_BLSP2_UART2_APPS_CLK 129
147#define GCC_BLSP2_UART2_SIM_CLK 130
148#define GCC_BLSP2_UART3_APPS_CLK 131
149#define GCC_BLSP2_UART3_SIM_CLK 132
150#define GCC_BLSP2_UART4_APPS_CLK 133
151#define GCC_BLSP2_UART4_SIM_CLK 134
152#define GCC_BLSP2_UART5_APPS_CLK 135
153#define GCC_BLSP2_UART5_SIM_CLK 136
154#define GCC_BLSP2_UART6_APPS_CLK 137
155#define GCC_BLSP2_UART6_SIM_CLK 138
156#define GCC_BOOT_ROM_AHB_CLK 139
157#define GCC_CE1_AHB_CLK 140
158#define GCC_CE1_AXI_CLK 141
159#define GCC_CE1_CLK 142
160#define GCC_CE2_AHB_CLK 143
161#define GCC_CE2_AXI_CLK 144
162#define GCC_CE2_CLK 145
163#define GCC_CNOC_BUS_TIMEOUT0_AHB_CLK 146