diff options
| author | Abhilash Kesavan <a.kesavan@samsung.com> | 2014-10-28 07:18:55 -0400 |
|---|---|---|
| committer | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2014-10-31 05:45:54 -0400 |
| commit | 932e98224d5602be17ed61d0e057e9326f12b59d (patch) | |
| tree | 70aca870f3702329c26701766c955cfd5c212fc4 /include/dt-bindings | |
| parent | 2ab2dfe5d4eef6bad8cdd90dc6bba5a7660273d4 (diff) | |
clk: samsung: exynos7: add gate clock for ADC block
Add clock support for the ADC interface in Exynos7.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/exynos7-clk.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h index f255bb7c64b3..8e4681b07ae7 100644 --- a/include/dt-bindings/clock/exynos7-clk.h +++ b/include/dt-bindings/clock/exynos7-clk.h | |||
| @@ -55,7 +55,8 @@ | |||
| 55 | #define PCLK_HSI2C11 9 | 55 | #define PCLK_HSI2C11 9 |
| 56 | #define PCLK_PWM 10 | 56 | #define PCLK_PWM 10 |
| 57 | #define SCLK_PWM 11 | 57 | #define SCLK_PWM 11 |
| 58 | #define PERIC0_NR_CLK 12 | 58 | #define PCLK_ADCIF 12 |
| 59 | #define PERIC0_NR_CLK 13 | ||
| 59 | 60 | ||
| 60 | /* PERIC1 */ | 61 | /* PERIC1 */ |
| 61 | #define PCLK_UART1 1 | 62 | #define PCLK_UART1 1 |