clk: samsung: exynos5433: Add clocks for CMU_ISP domain

This patch adds the mux/divider/gate clocks for CMU_ISP domain which
generates the clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

1 files changed, 88 insertions, 1 deletions

diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index 1b2d333c1786..fbc81e3424a6 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -116,6 +116,8 @@
 #define CLK_DIV_SCLK_USBDRD30           143
 #define CLK_DIV_SCLK_JPEG               144
 #define CLK_DIV_ACLK_MSCL_400           145
+#define CLK_DIV_ACLK_ISP_DIS_400        146
+#define CLK_DIV_ACLK_ISP_400            147
 
 #define CLK_ACLK_PERIC_66               200
 #define CLK_ACLK_PERIS_66               201
@@ -155,8 +157,10 @@
 #define CLK_ACLK_MSCL_400               235
 #define CLK_ACLK_MFC_400                236
 #define CLK_ACLK_HEVC_400               237
+#define CLK_ACLK_ISP_DIS_400            238
+#define CLK_ACLK_ISP_400                239
 
-#define TOP_NR_CLK                      238
+#define TOP_NR_CLK                      240
 
 /* CMU_CPIF */
 #define CLK_FOUT_MPHY_PLL               1
@@ -1026,4 +1030,87 @@
 
 #define HEVC_NR_CLK                                     19
 
+/* CMU_ISP */
+#define CLK_MOUT_ACLK_ISP_DIS_400_USER                  1
+#define CLK_MOUT_ACLK_ISP_400_USER                      2
+
+#define CLK_DIV_PCLK_ISP_DIS                            3
+#define CLK_DIV_PCLK_ISP                                4
+#define CLK_DIV_ACLK_ISP_D_200                          5
+#define CLK_DIV_ACLK_ISP_C_200                          6
+
+#define CLK_ACLK_ISP_D_GLUE                             7
+#define CLK_ACLK_SCALERP                                8
+#define CLK_ACLK_3DNR                                   9
+#define CLK_ACLK_DIS                                    10
+#define CLK_ACLK_SCALERC                                11
+#define CLK_ACLK_DRC                                    12
+#define CLK_ACLK_ISP                                    13
+#define CLK_ACLK_AXIUS_SCALERP                          14
+#define CLK_ACLK_AXIUS_SCALERC                          15
+#define CLK_ACLK_AXIUS_DRC                              16
+#define CLK_ACLK_ASYNCAHBM_ISP2P                        17
+#define CLK_ACLK_ASYNCAHBM_ISP1P                        18
+#define CLK_ACLK_ASYNCAXIS_DIS1                         19
+#define CLK_ACLK_ASYNCAXIS_DIS0                         20
+#define CLK_ACLK_ASYNCAXIM_DIS1                         21
+#define CLK_ACLK_ASYNCAXIM_DIS0                         22
+#define CLK_ACLK_ASYNCAXIM_ISP2P                        23
+#define CLK_ACLK_ASYNCAXIM_ISP1P                        24
+#define CLK_ACLK_AHB2APB_ISP2P                          25
+#define CLK_ACLK_AHB2APB_ISP1P                          26
+#define CLK_ACLK_AXI2APB_ISP2P                          27
+#define CLK_ACLK_AXI2APB_ISP1P                          28
+#define CLK_ACLK_XIU_ISPEX1                             29
+#define CLK_ACLK_XIU_ISPEX0                             30
+#define CLK_ACLK_ISPND_400                              31
+#define CLK_ACLK_SMMU_SCALERP                           32
+#define CLK_ACLK_SMMU_3DNR                              33
+#define CLK_ACLK_SMMU_DIS1                              34
+#define CLK_ACLK_SMMU_DIS0                              35
+#define CLK_ACLK_SMMU_SCALERC                           36
+#define CLK_ACLK_SMMU_DRC                               37
+#define CLK_ACLK_SMMU_ISP                               38
+#define CLK_ACLK_BTS_SCALERP                            39
+#define CLK_ACLK_BTS_3DR                                40
+#define CLK_ACLK_BTS_DIS1                               41
+#define CLK_ACLK_BTS_DIS0                               42
+#define CLK_ACLK_BTS_SCALERC                            43
+#define CLK_ACLK_BTS_DRC                                44
+#define CLK_ACLK_BTS_ISP                                45
+#define CLK_PCLK_SMMU_SCALERP                           46
+#define CLK_PCLK_SMMU_3DNR                              47
+#define CLK_PCLK_SMMU_DIS1                              48
+#define CLK_PCLK_SMMU_DIS0                              49
+#define CLK_PCLK_SMMU_SCALERC                           50
+#define CLK_PCLK_SMMU_DRC                               51
+#define CLK_PCLK_SMMU_ISP                               52
+#define CLK_PCLK_BTS_SCALERP                            53
+#define CLK_PCLK_BTS_3DNR                               54
+#define CLK_PCLK_BTS_DIS1                               55
+#define CLK_PCLK_BTS_DIS0                               56
+#define CLK_PCLK_BTS_SCALERC                            57
+#define CLK_PCLK_BTS_DRC                                58
+#define CLK_PCLK_BTS_ISP                                59
+#define CLK_PCLK_ASYNCAXI_DIS1                          60
+#define CLK_PCLK_ASYNCAXI_DIS0                          61
+#define CLK_PCLK_PMU_ISP                                62
+#define CLK_PCLK_SYSREG_ISP                             63
+#define CLK_PCLK_CMU_ISP_LOCAL                          64
+#define CLK_PCLK_SCALERP                                65
+#define CLK_PCLK_3DNR                                   66
+#define CLK_PCLK_DIS_CORE                               67
+#define CLK_PCLK_DIS                                    68
+#define CLK_PCLK_SCALERC                                69
+#define CLK_PCLK_DRC                                    70
+#define CLK_PCLK_ISP                                    71
+#define CLK_SCLK_PIXELASYNCS_DIS                        72
+#define CLK_SCLK_PIXELASYNCM_DIS                        73
+#define CLK_SCLK_PIXELASYNCS_SCALERP                    74
+#define CLK_SCLK_PIXELASYNCM_ISPD                       75
+#define CLK_SCLK_PIXELASYNCS_ISPC                       76
+#define CLK_SCLK_PIXELASYNCM_ISPC                       77
+
+#define ISP_NR_CLK                                      78
+
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */