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authorOlof Johansson <olof@lixom.net>2014-07-19 15:16:02 -0400
committerOlof Johansson <olof@lixom.net>2014-07-19 15:16:34 -0400
commit730346236af3fcd3324dbc26e4fa13955c59fa7e (patch)
tree8bdc0ac70d36636a26e2284670aee5f15b930831 /include/dt-bindings
parent1409f3fd5bdb548b0e11a109baa1087680b60c5a (diff)
parent8fe9346b945d76ddb3f08c00e34d701174c62fa0 (diff)
Merge tag 'zynq-dt-for-3.17' of git://git.xilinx.com/linux-xlnx into next/dt
Merge "Xilinx Zynq changes for v3.17" from Michal Simek: arm: Xilinx Zynq dt patches for v3.17 - Document and use new cadence serial binding * tag 'zynq-dt-for-3.17' of git://git.xilinx.com/linux-xlnx: ARM: zynq: DT: Migrate UART to Cadence binding tty: cadence: Document DT binding + Linux 3.16-rc5 Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'include/dt-bindings')
-rw-r--r--include/dt-bindings/clock/exynos5420.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 97dcb89d37d3..21d51ae1d242 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -63,7 +63,6 @@
63#define CLK_SCLK_MPHY_IXTAL24 161 63#define CLK_SCLK_MPHY_IXTAL24 161
64 64
65/* gate clocks */ 65/* gate clocks */
66#define CLK_ACLK66_PERIC 256
67#define CLK_UART0 257 66#define CLK_UART0 257
68#define CLK_UART1 258 67#define CLK_UART1 258
69#define CLK_UART2 259 68#define CLK_UART2 259
@@ -203,6 +202,8 @@
203#define CLK_MOUT_G3D 641 202#define CLK_MOUT_G3D 641
204#define CLK_MOUT_VPLL 642 203#define CLK_MOUT_VPLL 642
205#define CLK_MOUT_MAUDIO0 643 204#define CLK_MOUT_MAUDIO0 643
205#define CLK_MOUT_USER_ACLK333 644
206#define CLK_MOUT_SW_ACLK333 645
206 207
207/* divider clocks */ 208/* divider clocks */
208#define CLK_DOUT_PIXEL 768 209#define CLK_DOUT_PIXEL 768