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authorKever Yang <kever.yang@rock-chips.com>2014-11-13 02:22:36 -0500
committerHeiko Stuebner <heiko@sntech.de>2015-01-12 15:38:08 -0500
commit19ce828cbc08003ec35076f704f258bbecb1f721 (patch)
treef8aa0d3abe5aaec72142a2abd58f60947234e71b /include/dt-bindings
parent97bf6af1f928216fd6c5a66e8a57bfa95a659672 (diff)
clk: rockchip: add clock ID for usbphy480m_src
There are 3 different parent clock from different usbphy, all of them are fixed 480MHz, it is not able to auto select by clock core to the 2nd and the 3rd parent. For different use case for different board, we may need to select different usbphy clock out as parent manually. Add the clock ID for it so that we can use in dts. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'include/dt-bindings')
-rw-r--r--include/dt-bindings/clock/rk3288-cru.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
index f60ce72a2b2c..d6b59aeed553 100644
--- a/include/dt-bindings/clock/rk3288-cru.h
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -80,6 +80,7 @@
80#define SCLK_SDIO0_SAMPLE 119 80#define SCLK_SDIO0_SAMPLE 119
81#define SCLK_SDIO1_SAMPLE 120 81#define SCLK_SDIO1_SAMPLE 120
82#define SCLK_EMMC_SAMPLE 121 82#define SCLK_EMMC_SAMPLE 121
83#define SCLK_USBPHY480M_SRC 122
83 84
84#define DCLK_VOP0 190 85#define DCLK_VOP0 190
85#define DCLK_VOP1 191 86#define DCLK_VOP1 191