diff options
| author | Sonika Jindal <sonika.jindal@intel.com> | 2015-02-19 02:46:44 -0500 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-02-23 19:58:16 -0500 |
| commit | e045d20bef41707dbba676e58624b54f9f39e172 (patch) | |
| tree | 7dc915b341417a24cf970b3d1e5a7ea2fac52da0 /include/drm | |
| parent | c982bd90f58681d00363538167477e60e2c8f731 (diff) | |
drm: Adding edp1.4 specific dpcd macros
Adding dpcd macros related to edp1.4 and link rates
v2: Added DP_SUPPORTED_LINK_RATES macros
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Reviewed-by: Todd Previte <tprevite@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'include/drm')
| -rw-r--r-- | include/drm/drm_dp_helper.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 7e25030a6aa2..d4803224028f 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h | |||
| @@ -92,6 +92,9 @@ | |||
| 92 | # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ | 92 | # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ |
| 93 | # define DP_OUI_SUPPORT (1 << 7) | 93 | # define DP_OUI_SUPPORT (1 << 7) |
| 94 | 94 | ||
| 95 | #define DP_SUPPORTED_LINK_RATES 0x010 /*eDP 1.4*/ | ||
| 96 | #define DP_MAX_SUPPORTED_RATES 0x8 | ||
| 97 | |||
| 95 | #define DP_I2C_SPEED_CAP 0x00c /* DPI */ | 98 | #define DP_I2C_SPEED_CAP 0x00c /* DPI */ |
| 96 | # define DP_I2C_SPEED_1K 0x01 | 99 | # define DP_I2C_SPEED_1K 0x01 |
| 97 | # define DP_I2C_SPEED_5K 0x02 | 100 | # define DP_I2C_SPEED_5K 0x02 |
| @@ -101,6 +104,7 @@ | |||
| 101 | # define DP_I2C_SPEED_1M 0x20 | 104 | # define DP_I2C_SPEED_1M 0x20 |
| 102 | 105 | ||
| 103 | #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ | 106 | #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ |
| 107 | # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */ | ||
| 104 | #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ | 108 | #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ |
| 105 | 109 | ||
| 106 | /* Multiple stream transport */ | 110 | /* Multiple stream transport */ |
| @@ -221,6 +225,8 @@ | |||
| 221 | # define DP_UP_REQ_EN (1 << 1) | 225 | # define DP_UP_REQ_EN (1 << 1) |
| 222 | # define DP_UPSTREAM_IS_SRC (1 << 2) | 226 | # define DP_UPSTREAM_IS_SRC (1 << 2) |
| 223 | 227 | ||
| 228 | #define DP_LINK_RATE_SET 0x115 | ||
| 229 | |||
| 224 | #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ | 230 | #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ |
| 225 | # define DP_PSR_ENABLE (1 << 0) | 231 | # define DP_PSR_ENABLE (1 << 0) |
| 226 | # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) | 232 | # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) |
| @@ -332,6 +338,8 @@ | |||
| 332 | # define DP_SET_POWER_D3 0x2 | 338 | # define DP_SET_POWER_D3 0x2 |
| 333 | # define DP_SET_POWER_MASK 0x3 | 339 | # define DP_SET_POWER_MASK 0x3 |
| 334 | 340 | ||
| 341 | #define DP_EDP_DPCD_REV 0x700 | ||
| 342 | |||
| 335 | #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */ | 343 | #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */ |
| 336 | #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */ | 344 | #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */ |
| 337 | #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */ | 345 | #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */ |
