x86: add early quirk for reserving Intel graphics stolen memory v5

Systems with Intel graphics controllers set aside memory exclusively for
gfx driver use.  This memory is not always marked in the E820 as
reserved or as RAM, and so is subject to overlap from E820 manipulation
later in the boot process.  On some systems, MMIO space is allocated on
top, despite the efforts of the "RAM buffer" approach, which simply
rounds memory boundaries up to 64M to try to catch space that may decode
as RAM and so is not suitable for MMIO.

v2: use read_pci_config for 32 bit reads instead of adding a new one
    (Chris)
    add gen6 stolen size function (Chris)
v3: use a function pointer (Chris)
    drop gen2 bits (Daniel)
v4: call e820_sanitize_map after adding the region
v5: fixup comments (Peter)
    simplify loop (Chris)

Acked-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66726
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66844
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 32 insertions, 0 deletions

diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 7276a72710e2..3abfa6ea226e 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -36,4 +36,36 @@ extern bool i915_gpu_lower(void);
 extern bool i915_gpu_busy(void);
 extern bool i915_gpu_turbo_disable(void);
 
+/*
+ * The Bridge device's PCI config space has information about the
+ * fb aperture size and the amount of pre-reserved memory.
+ * This is all handled in the intel-gtt.ko module. i915.ko only
+ * cares about the vga bit for the vga rbiter.
+ */
+#define INTEL_GMCH_CTRL         0x52
+#define INTEL_GMCH_VGA_DISABLE  (1 << 1)
+#define SNB_GMCH_CTRL           0x50
+#define    SNB_GMCH_GGMS_SHIFT  8 /* GTT Graphics Memory Size */
+#define    SNB_GMCH_GGMS_MASK   0x3
+#define    SNB_GMCH_GMS_SHIFT   3 /* Graphics Mode Select */
+#define    SNB_GMCH_GMS_MASK    0x1f
+
+#define I830_GMCH_CTRL                  0x52
+
+#define I855_GMCH_GMS_MASK              0xF0
+#define I855_GMCH_GMS_STOLEN_0M         0x0
+#define I855_GMCH_GMS_STOLEN_1M         (0x1 << 4)
+#define I855_GMCH_GMS_STOLEN_4M         (0x2 << 4)
+#define I855_GMCH_GMS_STOLEN_8M         (0x3 << 4)
+#define I855_GMCH_GMS_STOLEN_16M        (0x4 << 4)
+#define I855_GMCH_GMS_STOLEN_32M        (0x5 << 4)
+#define I915_GMCH_GMS_STOLEN_48M        (0x6 << 4)
+#define I915_GMCH_GMS_STOLEN_64M        (0x7 << 4)
+#define G33_GMCH_GMS_STOLEN_128M        (0x8 << 4)
+#define G33_GMCH_GMS_STOLEN_256M        (0x9 << 4)
+#define INTEL_GMCH_GMS_STOLEN_96M       (0xa << 4)
+#define INTEL_GMCH_GMS_STOLEN_160M      (0xb << 4)
+#define INTEL_GMCH_GMS_STOLEN_224M      (0xc << 4)
+#define INTEL_GMCH_GMS_STOLEN_352M      (0xd << 4)
+
 #endif                          /* _I915_DRM_H_ */